A Coefficient Optimization and Architecture Selection Tool for SD Modulators Considering Component Non-Idealities M. Orkun Saglamdemir
Ömer Yetik
Selçuk Talay
Günhan Dündar
Bogaziçi University Dept. of Electrical and Electronics 34342 Bebek /Istanbul Turkey +90 212 3596414
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ABSTRACT In this paper, a tool generated in MATLAB environment for automatic modeling and architecture synthesis of sigma-delta (SD) modulators is described. The tool is capable of generating the parametric signal and noise transfer functions (STF and NTF) of an SD modulator of any order. After generating the transfer functions, it optimizes both the STF and the NTF of the system simultaneously in such a way to realize a desired frequency response. Most important of all, this tool is capable of taking component non-idealities into account and optimizing the coefficients so as to compensate the effects of non-idealities on the system. Integrator non-idealities (the switched capacitor mismatches and integrator leakage due to finite DC gain of the op-amp, etc.) are given as examples in the paper. The tool uses some criteria such as minimization of the number of signal paths of the architecture in order to obtain minimum possible complexity and avoiding of single closed loops without a delay. Also, another important aspect of the tool is that it spans the whole solution space according to this criterion and returns a set of several parametric solutions.
Categories and Subject Descriptors: J.6 [Computer Applications]: Computer-aided engineering - B.8.2 [Performance and Reliability]: Performance Analysis and Design Aids
General Terms: Design, Performance Keywords:
Sigma-delta converters, Mixed-Signal circuits, Design automation
1. INTRODUCTION Among various over-sampling analog-to-digital conversion (ADC) techniques available in the literature, sigma-delta (SD) conversion technique is becoming more and more popular. The use of SD based ADC's for the primary data conversion is very attractive, since it uses basic blocks and requires no sample and hold. The sampling rate employed is much faster than the highest frequency in the message signal itself. The high accuracy conversion is achieved as a result of the modulator, operating as a self-adaptive, fast limit cycling system [1], [2]. Besides the advantages of this technique, there are some difficulties in designing SD ADC's. One of the major difficulties is the determination of the appropriate SD structure, which provides the required performance. Since SD ADC's contain large number of connections between building blocks (quantizer(s), integrator(s), DAC) there exist more than one structure satisfying desired performance specifications. In order to decrease the complexity of
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the design procedure, design automation tools [3] have been developed [4], [5], [6]. Although all of these approaches have been successful in addressing some aspects of the SD converter design problem, none have been able to solve the architecture selection problem completely. A standard SD modulator system utilizes several signal feedforward and signal feedback paths. For every such signal path there exists an associated coefficient, which is the path gain. These coefficients are all related to each other and a small change in one of them may cause dramatic changes in the operation, response, and performance of the overall modulator. On the other hand, including or removing any of these paths corresponds to a different modulator topology. Another important issue is that there are many non-idealities in the SD modulator system in real-life, which should also be taken into account in the design process. These non-idealities may include the clock-jitter, kT/C noise, op-amp noise, and integrator non-idealities such as the finite DC gain (leakage), the switched capacitor mismatches, slew-rate limitation of the ap-amp, dc offset of the comparator, etc. [7] So, in designing an SD modulator, the challenge is not only the selection of a modulator topology from a large set of possibilities but also the optimization of the topology parameters‚ the coefficients‚ in such a way to satisfy the system specifications without ignoring the mentioned non-idealities. The design flow should include three basic steps: (1) determination of all possible SD modulator topologies of any order, which is capable of realizing a desired response, (2) selection of the optimum topology from these possibilities, (3) calculation of the topology coefficients, which satisfy the system specifications and still remain in considerable limits. As obvious from the above discussion, the optimum topology for a specific application can only be constructed by employing a design automation tool. Some versatile tools were previously developed in MATLAB environment as a solution to this design automation problem such as [8] and [9]. This work proposes a new design automation tool generated in MATLAB environment. The tool works independent of the modulator order and finds all possible SD modulator topologies satisfying a desired system response with minimum number of signal paths. Compared to the similar work in this area, this tool has several advantages. First of all it models most component non-idealities in the SD modulator. In this paper, integrator nonidealities are presented as an example, since they constitute the most of the non-idealities of the SD modulator architecture The tool also optimizes the coefficients not only for a desired signal transfer function (STF) or noise transfer function (NTF)
Figure 1. A generic second order SD modulator architecture with all possible connections. individually, but for both of them simultaneously and it provides the whole solution space satisfying a desired response. In the following sections, a generic second order SD modulator topology will be analyzed; the approach taken in generation of the tool will be discussed in detail. Then, the effects of the integrator non-idealities on the system will be mentioned and the extraction of these non-ideality parameters from a switched-capacitor integrator will be explained. Finally the application of the tool on a standard second order system including these extracted nonideality parameters (for both a low and a high-performance opamp) will be presented and these results will be analyzed in comparison to the ideal case.
2. THE STANDARD MODULATOR
ND
2
ORDER
The tool proposed takes a netlist of the following form (see Figure . 2), which describes the architecture in Figure 1 in the block level. According to this netlist, the tool generates a bunch of equations in symbolic variables, which describes the input/output relation for each individual block in the system. After solving these equations, the parametric STF and NTF are generated. The STF and NTF calculated for the standard second order topology in Figure 1 are as follows;
STF,NTF =
n 2 z 2 + n1 z + n 0 d 2 z 2 + d1 z + d 0
(1)
where
SD
n 2( STF ) = g6g5 " g1g8 + g1g6g2 " g7; ! n1( STF ) = ("bg11g8 " bg6g4 " bg15 " bg9g2 + 2g8c " 2g6g2c)g1 "bg9g5 + bg14g2g7 + 2cg7 " bg3g7 " bg11g7 + bg3g6g5 " 2cg6g5 " bg14g5g8; n1( NTF ) = b(g3 " g14g2 + g11) " 2c n 0( NTF ) = b 2 (g14g4 + g11g3) " bc(g3 + g11 + g14g2) + c 2 d 2( STF ,NTF ) = "g6g12 " g8g13 + g6g13g2 + g10 + 1 d1( STF ,NTF ) = (bg33 " 2c " bg14g2 + bg11)g10 " bg8g11g13 + bg3 " bg14g2 + bg11" bg9g13g2 " bg6g3g12 " bg15g13 + bg9g12 + 2g8g13c + bg14g8g12 " bg6g13g4 + 2g6g12c " 2c(g6g13g2 " 1)
Figure 2. The netlist of the modulator in Figure 1.
!
2.1 Generation of Parametric STF and NTF .
A standard second order SD modulator architecture is shown in Figure 1. The architecture comprises all the possible feedback and feed-forward connections with an associated coefficient for each of them, an ideal quantizer, an ideal digital-to-analog converter (DAC), and two delayed non-ideal integrators. The included nonideality parameters b and c model the non-ideal effects of the switched-capacitor integrator on the overall system performance. They include many effects such as the finite DC gain of the opamp of the integrator, the switch capacitor leakages, etc. These parameters will be mentioned in more detail in the following sections.
The denominator polynomials of both STF and NTF are the same as expected. Due to the complexity of the coefficients it was impossible to write down all 9 different coefficients here.
2.2 Generation of the All Possible Topologies with Minimum Number of Paths After calculating the parametric signal and noise transfer functions, the tool gets two numerical transfer functions from the user, one for STF and the other for NTF. These are the responses to be realized by the parametric STF and NTF. After taking these numerical transfer functions, the tool equates these numerical functions to the corresponding parametric functions and creates 9 equations (3 from the denominator of STF and NTF, 3 from the numerator of STF, and a final 3 from the numerator of NTF) in 15 variables since we have 15 coefficients in the architecture shown
in Figure 1 (g1, g2, g3,……, g15). Since the number of variables is greater than that of the equations, there is a great degree of freedom in the system, which means that several different topologies realizing the same numeric STF and NTF may be obtained. In solving these equations the tool has some priorities such as minimizing the number of paths in the system in order to decrease the complexity and avoiding any closed signal loops without a delay. Taking these priorities into account, different combinations of coefficients are assigned as zeros, which means that those paths are removed from the generic topology. The more is the number of different combinations, the higher is the degree of freedom, and the more is the number of different topologies. The whole solution space is spanned here and many different topologies are found. Even some topologies are found which look weird at the first glance but has been proven to be working .For example one solution set for the SD modulator shown in Figure 1 is; g1=0, g2=0, g3=-0.5, g4=1, g5=-2, g6=2, g7=-4, g8=0, g9=-1, g10=0, g11=0.5, g12=0, g13=-1, g14=0.25, g15=0. This solution does not seem logical at first, since the input signal is not fed directly to the first integrator, but has been proven to be working as good as a conventional standard second order SD modulator architecture, through behavioral simulation.
2.3 The Component Non-Idealities In a standard switched capacitor SD modulator loop there exists an inherent non-linearity due to the non-idealities of the components of the system. These non-idealities may be summarized as the clock jitter - occurring due to the variations of the clock period and causing non-uniform sampling; the integrator noise – including the thermal noise of the sampling switches (kT/C noise) and the op-amp noise; and the integrator nonidealities – integrator offset, the finite DC gain, the finite bandwidth, slew rate and saturation limitations of the op-amp, etc. Also there are some other non-idealities due to the other components such as the DAC and the comparator offsets [7].
A switched capacitor integrator is shown in Figure 3. As proposed in [10], all the integrator non-idealities, except the slew-rate and the saturation limitations, can be modeled with the following nonideal integrator transfer function:
CS (1" # 1 )(1" # 2 )z "1 C f (1" (1" # 3 )z "1 )(1" # 1# 2 )z "1
H (z) =
(2)
where,
!
CS : sampling capacitor (given as CS1= CS2) Cf : feedback capacitance (Cf1 = Cf2) δ1 : charging error δ2 : charge transfer error δ3 : finite gain error
The exact expression for the non-ideal integrator is rather complex as can be seen; but for the sake of simplicity, the higher order terms may be ignored and the transfer function in (2) can be estimated with the following one: bz "1 (3) H non"ideal (z) = 1" cz "1 where the parameters b and c are used to model the most of the integrator non-idealities mentioned before. ! For the behavioral simulation of a SD modulator with the integrator non-idealities included, one can easily extract the parameters b and c by simulation. Assuming that the relation between the output Y(z) and the input X(z) of a non-ideal integrator with the transfer function given in (3) is;
Y (z) =
bz "1 X (z) 1" cz "1
(4)
it can be shown that;
!
bx[ n " 1] = y[ n] " cy[ n " 1]
(5)
and this relation can be used to find the parameters b and c.
!
3. APPROACH AND SIMULATIONS 3.1 Design of a High-Performance Op-Amp
Figure 3. A switched capacitor integrator. Some of these non-idealities can be directly mapped to the transfer function describing the behavior of the SD modulator and . some of them cannot. This work will primarily be discussing those that can be mapped to the transfer function directly as a parameter or as an extra noise source in the system. As an example the modeling of the integrator non-idealities will be discussed and the performance of the tool proposed here, in generating SD topologies to compensate these non-ideal effects, will be demonstrated.
In order to test the performance of the tool proposed here in a standard second order system including the discussed integrator non-idealities, several behavioral simulations have been carried out. However, to be more realistic in choice of parameters, a high-performance fully differential folded cascode op-amp has been designed in Mentor Graphics AMS Design Architect environment initially. Figure 4 shows the schematic diagram of the designed op-amp. The specifications of this op-amp, with a load capacitance of 4 pF at each output are as follows: Gain = 76.5 dB, BW = 200 MHz, 3-dB cut-off = 55 kHz, slew-rate (SR) = 182,4 V/µs. The output DC level of the op-amp is 1.472 V and the bias voltages are Vbias1 = 2.1 V, Vbias2 = 1.83 V. Common mode feedback is not shown here for sake of simplicity. The op-amp has been designed as folded cascode, in order to have a high gain by using only a single stage, and consequently to avoid any need for frequency compensation, which decreases SR, and in turn the speed of the op-amp.
Figure 4. A fully differential folded cascode op-amp. By using this op-amp the switched capar integrator shown in Figure 3 has been implemented by selecting Cs1 = Cs2 = 1 pF and Cf1 = Cf2 = 2 pF. This integrator has been simulated by giving a differential input voltage of Vin = 100 mV. The integrator nonideality parameters have been extracted as b = 0.4994 and c = 0.9996 for this op-amp from this simulation.
3.2 Simulations The tool has been applied to the standard second order SD architecture shown in Figure 1 and has been tested for 3 different combinations of b and c, one of which was b=0.5, c=1 corresponding to an ideal op-amp, the other was b=0.4994, c=0.9996 corresponding to the op-amp discussed above, and the final was b=0.496, c=0.98 corresponding to a low-power, lowgain low-SR op-amp in which the non-idealities were more highly effective. The desired response was the case where STF was an all-pass response and NTF was a high-pass response as shown in (6.a) and (6.b) respectively. STF = 1/z2 NTF = (z-1)2/z2
(6.a) (6.b)
3.2.1 Ideal Op-Amp Case Here we have used the non-ideality parameters as b=0.5, and c=1. The tool has found 135 different topologies satisfying the response in (6). One simple solution was g1=1, g2=0, g3=-0, g4=2, g5=0, g6=0, g7=0, g8=0, g9=2, g10=0, g11=0, g12=2, g13=1, g14=0, g15=0. The SNR in this case has been found to be 101.5 dB.
3.2.2 High-Performance Op-Amp Case As mentioned before, we have found b=0.4994 and c=0.9996 for this op-amp. The tool has found 84 different topologies satisfying the desired response. One of the solutions corresponding to this standard case was g1=1, g2=0, g3=-0.0008, g4=2.0048, g5=0, g6=0, g7=0, g8=0, g9=2, g10=0, g11=-0.0008, g12=2.0024, g13=1, g14=0, g15=0. The coefficients differ from the ideal case just slightly. The main difference is the two local positive feedback paths, which the tool puts around the integrators in order to compensate for the leakage non-ideality. The most important
thing observed here was that; this op-amp has performed very . close to the ideal case even with the ideal case coefficients given in Section 3.2.1, with an SNR of 96.89 dB. We have also made simulations for two other cases with this op-amp, one with the coefficients calculated by the tool but the local feedback coefficients (g3 and g11) set to zero and one with all of the calculated coefficients included. The results were 98.7 dB and 100.8 dB respectively.
3.2.3 Low-Performance Op-Amp Case It has to be noted that, the power consumption of the op-amp used in the previous simulation is rather high in order to obtain such a high slew-rate. There may exist some applications in which power consumption may be a limiting factor and it may be necessary to use an op-amp with low power consumption. For such an op-amp, the effects of integrator non-idealities become more significant and there exists a higher deviation in the values of the parameters b and c compared to their ideal values. We have simulated this case by using b=0.496 and c=0.98 which corresponds to a lowperformance op-amp. The tool has found 82 different topologies satisfying the response in (6). One of the solutions corresponding to this case was g1=1, g2=0, g3=-0.0403, g4=2.0324, g5=0, g6=0, g7=0, g8=0, g9=2, g10=0, g11=-0.0403, g12=2.01613, g13=1, g14=0, g15=0. The deviation from the ideal case is higher compared to the highperformance op-amp case. The tool again puts two local positive feedback paths around the integrators to compensate for the leakage non-ideality. 3 different behavioral simulations have been carried on for this op-amp: with the ideal coefficients given in Section 3.2.1, with the calculated coefficients by the tool but the positive local feedback coefficients (g3 and g11) set to zero, and finally with all of the calculated coefficients here including the local feedback paths. These simulations resulted in SNR values of 74 dB, 84.14 dB and 100.74 dB respectively. The PSD plots for the first case (the low-performance op-amp and the ideal coefficients given in Section 3.2.1) and the last case (the lowperformance op-amp and all of the non-ideal coefficients calculated by the tool) is given in Figures 5 and 6 respectively. In the following section, two PSD plots for the low-performance op-amp case are given for illustration (see Figures 5 and 6) and
the SNR values for all simulations are summarized as a table (see Table 1).
4. RESULTS Several important results may be obtained from the simulation data presented here. If the SNR values in Table 1 are analyzed, it can be seen that the SNR value for the case of high-performance op-amp (b=0.9449, c=0.9996) with the ideal coefficient values is very close to the SNR value for the case of an ideal op-amp and the ideal coefficient set. This means that if the op-amp is designed in such a good way that the variation of b and c from their ideal values is very small; the SD modulator systems works pretty fine with the ideal system coefficients and no extra paths are necessary to obtain a satisfactory system performance. Rather more interesting and exciting results are obtained with the low-performance op-amp. In Figure 5, the PSD plot for an SD modulator with a low-performance op-amp (b=0.496, c=0.98) and ideal coefficient set is shown. It can easily be seen that the response is much worse than that of a standard second order SD modulator. The SNR value for this case (74 dB) is obviously much lower than that of the ideal system, which is 101.5 dB. These results give an estimate about how much the system response may degrade due to the component non-idealities.
characteristic, the effect of non-idealities on the system is not much already. However, things are different for the case of the low-performance op-amp. Omitting the extra coefficients decreases the SNR from 100.74 dB to 84.14 dB, which is a big loss. So it is not a good idea to omit these small extra coefficients in this case. Table 1. SNR [dB] values for different simulation scenario Parameter Sets b=0.5, c=1 b=0.4994, c=0.9996 b=0.496, c=0.98
Ideal 2nd order
Coefficient Sets Calc. Coeffs. No Local Feedback
All the Calc. Coeffs.
101.5
-
-
96.89
98.7
100.8
74
84.14
100.74
On the other hand, the PSD plot of the SD modulator with the low-performance op-amp and with the coefficients calculated by the tool proposed here is shown in Figure 6. As can be seen, the PSD is very close to that of an ideal second order system. The SNR value in this case is very close to the ideal value of 101.5 dB here. This means that the tool is very successful in modeling the non-idealities and proposing architecture to compensate their effects on the system performance. Another important issue to be questioned here was what would happen if the extra coefficients proposed by the tool (g3 and g11 here in our case) were omitted since their values are rather small compared to the other coefficients. The results show that, for the high-performance op-amp case, omitting them does not make such a big difference, the SNR decreases to 98.7 dB from 100.8 dB. But since the op-amp here has a very good performance
Figure 6. The PSD plot for the low-performance op-amp case (b=0.496, c=0.98 and calculated coefficients with local feedback included).
5. CONCLUSION In this work, a tool created in MATLAB environment for . automated design of SD modulator architectures has been proposed. The tool starts working on a generic SD modulator architecture as shown in Figure 1. There is no limit on the order or the complexity of this generic architecture.
Figure 5. The PSD plot for the low-performance opamp case (b=0.496, c=0.98 and ideal coefficients).
.
The parametric STF and NTF are calculated at first for this generic architecture. These symbolic transfer functions are matched to a set of numerical transfer functions describing a definite, desired response from the system. A bunch of equations is created by this way. Since the number of coefficients is always greater than the number of equations, there is a high degree of freedom in the system, which makes it possible to have a set of parametric solutions for the architecture coefficients. The tool makes use of this degree of freedom and finds all the possible SD modulator topologies satisfying the desired frequency responses. It even finds some architectures, which look weird at first glance but has been proven to be working through behavioral simulation. The tool uses some criteria in this process such as minimization of
the number of signal paths in the architecture, and avoiding the occurrences of closed signal loops that has no delay.
[3] S. Balkır, G. Dundar, and A. Ogrenci. “Analog VLSI Design Automation.” CRC Press, 2003.
Although there are several other tools proposed for the solution of the design automation problem of the SD modulators, this tool has many advantages over the others. First of all it optimizes both STF and NTF simultaneously, not only one at a time. Also it spans all the solution space according to the criteria mentioned above and returns parametric solutions not only a few strict numeric solutions.
[4] L. Williams. “Midas-a functional simulator for mixed digital and analog sampled data systems.” In Proc. IEEE Int. Symp. Circuit Syst., pages 2148–2151, San Diego, USA, May 1992.
The most important of all, this tool has the capability of taking the component non-idealities into account and optimizing the coefficients such a way to compensate the undesired effects of these non-idealities. Most of the component non-idealities can be mapped directly to the transfer function of the system and most of them a related to the switched capacitor integrator in the SD modulator system. For this reason, the modeling of the integrator non-idealities has been given as an example but the tool is capable of modeling the other component non-idealities such as the comparator offset, DAC offset , etc.
[6] F. Medeiro, B. Perez-Verdu, and A. Rodriguez-Vazquez. “Top-Down Design of High-Performance Sigma-Delta Modulators.” Kluwer Academic Publishers, Netherlands, 1999.
The results shown in the preceding sections prove that the tool works very well and manages to overcome the effect of these nonidealities just by adjusting the coefficients or introducing new paths where necessary.
6. REFERENCES [1] P. M.Aziz, H. V. Sorensen, and J. V. D. Spiegel. ”An overview of sigma-delta converters.” IEEE Signal Processing Magazine, pages 61–84, January 1996. [2] G. C. Temes and J. C. Candy. “A Tutorial Discussion of The Oversampling Method for A/D and D/A Conversion.” The IEEE Publications, 1990.
[5] K. Francken and G. E. Gielen. “A high-level simulation and synthesis environment for delta sigma modulators.” IEEE Trans. Computer-Aided Design, 22:1049–1061, August 2003.
[7] S.Brigati, F.Francesconi, P. Malcovati, D. Tonietto, A. Baschirotto, F. Maloberti. “Modeling Sigma-Delta Modulator Non-Idealities in Simulink.” Proceedings of ISCAS ’99. [8] J. Ruiz-Amaya, J. Rosa, F. Medeiro, F. Fernandez, R. Rio, B. Perez-Verdu, and A. Rodriguez-Vazquez. “An optimization based tool for the high-level synthesis of discrete-time and continuous-time ∑∆ modulators in the matlab/simulink environment”. In Proc. IEEE Int. Symp. Circuit Syst., pages 97–100, Vancouver, Canada, May 2004. [9] H. Tang and A. Doboli. “High-level synthesis of SD modulator topologies optimized for complexity, sensitivity, and power consumption.” IEEE Trans. Computer-Aided Design, pages 597 – 607, March 2006. [10] A. Robertini, W. Guggenbuhl. “Errors in SC Circuits Derived from Linearly Modeled Amplifiers and Switches.” IEEE Transactions on Circuits and Systems, Vol. 39, No.2, February 1992.
