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Journal of Circuits, Systems, and Computers Vol. 17, No. 4 (2008) 611–626 c World Scientific Publishing Company
UNIVERSAL LOW/MEDIUM SPEED I2 C-SLAVE TRANSCEIVER: A DETAILED FPGA IMPLEMENTATION
A. K. OUDJIDA∗ , A. LIACHA, D. BENAMROUCHE, M. GOUDJIL, R. TIAR and A. OUCHABANE Microelectronics Department, Centre de D´ eveloppement des Technologies Avanc´ ees — CDTA — Cit´ e du 20 aˆ out 1956, BP. 17, Baba Hassen, Algiers 16303, Algeria ∗a
[email protected] Revised 19 December 2007 Based on a recent market study of an important number of I2 C devices, all fully compliant with the Philips I2 C-bus specification, version 2.1, release January 2000, this paper introduces a detailed I2 C-slave VLSI-architecture that incorporates all necessary features required by modern ASIC/SoC applications, except high speed mode. The design is a general purpose solution offering viable ways to controlling I2 C-bus and highly flexible to suit any particular needs. The purpose of this paper is to provide a full description of an up-to-date I2 C-slave FPGA implementation. All related issues, starting from the elaboration of initial specifications, till the final verifications and synthesis, are comprehensively discussed and justified. This includes all issues from basic architectural operations to final software drivers and application. The whole design code, either for synthesis or verification, is implemented in Verilog 2001 (IEEE 1365). The synthesis design code is technology independent and was simulated at both RTL and gate level with timing back annotation using ModelSim SE 5.8e and synthesized using both Leonardo Spectrum V2001 1d.45 and Xilinx’s XST 6.1i. Keywords: Inter integrated circuit (IIC); serial interface; intellectual property (IP); system-on-chip (SoC).
1. Introduction The Inter-IC bus,1−4 commonly known as the I2 C “eye-squared-see” bus, is a control bus that provides the communications link between integrated circuits in a system. Developed by Philips in the early 1980s, this simple two-wire bus (Fig. 1) with a software-defined protocol has evolved to become the de facto worldwide standard (Table 1) for system control, finding its way into everything from temperature sensors and voltage level translators to EEPROMs, general-purpose I/O, A/D and D/A converters, CODECs, and microprocessors of all kinds. The I2 C specification has been meticulously defined on many web pages 5, 6 and especially in Philips Semiconductor data sheets.1−3 Consequently, it will not be defined here. 611
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VCC
Pullup Rp Rp
Master …
Slave …
Slave … Master
SDA SCL
Fig. 1. Table 1.
I2 C-bus configuration.
Speed of various connectivity standards.
CAN (1 Wire) I2 C (“Industrial”, and SMBus) SPI CAN (fault tolerant) I2 C CAN (high speed) I2 C “High Speed Mode” USB (1.1) SCSI (parallel bus) Fast SCSI Ultra SCSI-3 Firewire/IEEE1394 HI-Speed USB (2.0)
33 KHz (typ) 100 KHz 110 KHz (original speed) 125 KHz 400 KHz 1 MHz 3.4 MHz 1.5 MHz or 12 MHz 40 MHz 8–80 MHz 18–160 MHz 400 MHz 480 MHz
Although the literature on I2 C protocol is so extensive and the topic is so old (early 1980), to the best of the authors’ knowledge there is no comprehensive analysis of the I2 C problem. By comprehensive analysis, we mean a treatment that starts from Philips’s 2.1 I2 C specifications and goes down to the actual ASIC/FPGA implementation, discussing all relevant architectural aspects and providing all implementation details. In our attempt to implement a universal I2 C-slave, we first made a market study of an important number of recent commercialized I2 C devices (datasheets) from different vendors to look at the requirements and what features to be included to satisfy modern ASIC/SoC applications. For the most part, the ones investigated are quite efficient, but unfortunately none of them provides details on the VLSI implementation. Besides, some of them are either far more complex than needed,8,9 or targeted to a specific application,10 or not including some of the recent requirements for today’s SoC applications,11−20 or have one or more of these disadvantages.7 The key features required for a universal I2 C-slave as a result of the market study are summarized in Table 2. This paper deals with a fully detailed VLSI implementation of a universal low/medium speed I2 C-slave transceiver based on the above-mentioned specifications. The presented architecture is configurable in that it allows the users to tailor the I2 C-slave to suit their application by setting certain parameters to enable/disable features. All main choices throughout the design process are deeply discussed and justified. The paper is organized as follows.
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Universal Low/Medium Speed I2C-Slave Transceiver Table 2.
613
I2 C-slave key features.
Global features
Key features
Data transfer
• Data transfers up to 100 Kbps in standard mode, and up to 400 Kbps in fast-mode • Fixed data width of 8 bits • Frame data-transfer (unlimited number of bytes) • Bidirectional data transfer • Software programmable acknowledge bit • Repeated START detection • Interrupt mode and polling mode transfer
Addressing
• Software programmable address (to be used in different application fields) • Own address and General Call address detection • 7-bit and 10 bit addressing format (reduce the risk of conflicting slave addresses)
Synchronization
• User defined Wait-states insertion period (clock stretching)
Host side interface
• Simple and basic handshaking protocol easily adaptable to any standard SoC bus21 via a wrapper22
Transfer error
• Transfer error recovery (status flags, use of a timer)
Data integrity
• Spike filtering (removing input spikes shorter than a certain number of clock cycles)
Performance
• User defined multiple-bytes write and read buffer (FIFO) to improve transfer performance (reduce wait state occurrences)
Parametrizable functionalities
• • • •
Implementation and test
• Strictly synchronous design with positive edgeclocking for straightforward scan-path insertion
I2 C transmitter/receiver Address mode 7 bits/10 bits With/without FIFO With/without digital filter
In this section we showed the requirement specifications of a recent market study for a modern I2 C-slave. Section 2 discusses the functional aspect of the whole architecture and its building blocks. Section 3 describes the interface of the design. Section 4 deals with the high-level design. Section 5 gives an idea on the verification plan and on the software side (drivers and application). Section 6 presents some implementation results. And finally some concluding remarks. 2. Functional Specifications 2.1. Noise filter unit To guarantee high noise immunity in case of motor system applications, the two I2 C lines (SDA & SCL) are first passed through a Schmitt trigger (PAD level) and then passed to a digital filter unit (Fig. 2). The result of this circuitry is that pulses shorter than a certain user-defined-number of CLK periods are considered as noise spikes and are automatically ignored. When the filter unit is disabled (ENFU = “0”) or iic filter reg content is equal to zero (reset value), the two I2 C lines pass directly without being filtered.
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low_wate nfull high_wate nempty Data Low-Level I2C Noise Filter Unit Unit Slave Protocol Unit iic_tx_data_reg
iic_rx_data_reg
SDA_low
digital filter
sda
address/data IO shift register
iic_filter_reg
iic_address_reg
digital filter
scl SCL_low
Transmitter-FIFO
Control Unit
Receiver-FIFO
iic_tx_no_reg
FSM
iic_tx_low_water_reg
clk
iic_tx_timeout_reg
iic_control_reg
iic_rx_no_reg
iic_status_reg
iic_rx_high_water_reg
iic_recover_reg
iic_rx_timeout_reg
nreset
Host Side Interface Unit
iic_timeout_now_reg
cs
Register-address decoder
iic_trans_status_reg
8
8
rw 5
din dout adr Fig. 2.
I2 C-slave-transceiver block diagram.
Example: CLK = 50 MHz ⇔ CLKT = 20 ns, and ENFU = “1”. If we consider that pulses shorter than 60 ns are considered as noise-spikes to be rejected, the value (60/20) = 3 must be put into the iic filter reg. 2.2. Low-level I 2C-slave protocol unit This unit fully implements Philips’s I2 C-slave protocol (Fig. 3) as specified in Ref. 1. When the I2 C-slave is in standby-state, the unit checks if the received address byte which is present in the address-IO-shift-register matches the unique 7/10-bits address stocked in the iic address reg. Upon an address match, the I2 C-slave enters either into transmit-state (slave transmitter) or into receive-state (slave receiver). The addressing protocol is as follows: • The first byte after START determines the slave to be addressed • Some exceptions to the rule: — 10-bit slave addressing: 1111 0XX + R/W — General call address (all devices are addressed): 0000 000 + R/W
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615
7-bit addressing S XXXXXXX R/W A DATA … receive-state Only one device will acknowledge 10-bit addressing DATA … S 11110XX R/W A1 XXXXXXXX A2 Sr 11110XX R A DATA XX= the 2 MSBs The 8 remaining bits transmit-state More than one device Only one device can acknowledge will acknowledge The 7 bits
Fig. 3.
Addressing modes.
2.3. Data unit Once in transmit or receive state, the data-IO-shift-register contains the data associated with the current transfer. During receive state; data is shifted in from the SDA line. After a byte has been read the contents are copied into the receiverFIFO. During transmit state, the Transmitter-FIFO contents are copied into the data-IO-shift-register and are then transmitted onto the SDA line. 2.3.1. Receive state The only condition for the I2 C-slave to accept the transfer is that the receiverFIFO must not be full. If such condition is not respected during address-decoding phase, a not acknowledge signal will be issued to the master transmitter. In case the slave receiver accepts the transfer (ack), the receiver-FIFO interrupts (nempty and high water), already enabled at initialization phase, will ensure the data transfer between the slave host and the receiver-FIFO nempty interrupt (low priority) informs the slave host that there is at least one byte to be read, while the high water interrupt (high priority) signals a critical level before the receiver-FIFO becomes full. If the receiver-FIFO becomes full, the slave receiver will no longer accepts bytes and SCL is pulled down (clock stretching) during a user-defined timeout stocked in iic rx timeout reg. If after this period, the FIFO still remains full, the SCL line is released and a not acknowledge will be issued to the master transmitter and the receiver-FIFO will be reset (data lost). Timeout is the period allowed for the slave host to read a byte when the receiverFIFO is full. The slave host can stop the reception of data by positioning the command register bit NACK to “1”. In this case, the slave receiver will not acknowledge the byte transfer by not pulling down the SDA line and the receiver-FIFO is reset (data lost). It is noteworthy that many short frames can be present at the same time into the receiver-FIFO.
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2.3.2. Transmit state After address match with r/w = “1”, the transmitter-FIFO interrupts (nfull and low water) are enabled by setting the command register bit TIEN to “1”. nfull interrupt (low priority) informs the slave host that there is at least one free location to be filled, while the low water interrupt (high priority) signals a critical level before the transmitter-FIFO becomes empty. If the transmitter-FIFO becomes empty while the master is still requiring data (ack), the SCL line is pulled down (clock stretching) during a user-defined timeout stocked in iic tx timeout reg. If after this period, the FIFO still remains empty, the SCL line is released and the latest FIFO data transmitted will be transmitted again (data duplication) since the slave host has no possibility to stop the transfer. This process is maintained as long as the master has not issued a nack. When a nack is detected, the transmitter-FIFO is reset (data lost) and interrupts are disabled. Algorithm 1. Receiver A - I 2 C slave in “standby state” - after address match (r/w = 0) - if receiver-FIFO full → issue a nack “busy state” → goto A B - transfer the byte from data-IO-shift-register to the receiver-FIFO “reception state” - if slave host has set NACK = “1” → issue an nack → reset the receiver-FIFO (data lost)∗ → goto A - if receiver-FIFO become full and stop bit detected → goto C - if receiver-FIFO become full and stop bit not detected → pull down SCL line during timeout “busy state” - if receiver-FIFO become not full before timeout is finished → release the SCL line → goto B - if timeout finished and receiver-FIFO full → release the SCL line → send a nack → reset the receiver-FIFO (data lost) → goto A C - run timeout - if address match during timeout → send nack “busy state” - if receiver-FIFO become not full before timeout is finished → goto A - if timeout finished and receiver-FIFO full → reset receiver-FIFO (data lost) → goto A (*): only when the receiver-FIFO is not empty
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Universal Low/Medium Speed I2C-Slave Transceiver
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Algorithm 2. Transmitter AB C -
D-
I2 C slave in “standby state” after address match (r/w = 1) enable transmitter-FIFO interrupts (nfull & low water) → TIEN = “1” if transmitter-FIFO is empty → goto D transfer a byte from transmitter-FIFO to data-IO-shift-register “transmit state” if nack from master → disable interrupts TIEN = “0” → reset the FIFO → goto A goto B pull down SCL line during timeout “busy state” if transmitter-FIFO becomes not empty before timeout is finished → transfer a byte “transmit state” if transmitter-FIFO is still empty after timeout → transfer the latest transmitted byte “transmit state” (data duplication) goto C
2.4. Host side interface unit Three types of operations (Fig. 4) are allowed on the interface unit: read, write, and passive read, i.e., read with no consequences. Read/write operations are taking place in one clock cycle as described by the following timing diagram: • Every time CS = “1” and RW = “1” at rising edge of CLK will be considered a complete read cycle. • Every time CS = “1” and RW = “0” at rising edge of CLK will be considered a complete write cycle.
CLK CS RW ADR DIN Write DOUT Passive Read Fig. 4.
Read
Passive Read
Read/write and passive read operations.
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• A passive read is independent of CLK, CS, and RW. It depends only on ADR. DOUT reflects the contents of the register at ADR without changing the state of the module. 2.5. Control unit The control logic generates the control signals for serial byte handling. A set of predefined status codes put into iic status reg covers the different states that the I2 C-slave can be in when an event occurs. Only seven (07) states are possible: • Sleep: the I2 C interface is disconnected from the system. SCL and SDA lines are put into high Z. • Standby: waiting to be addressed by an I2 C master. • Transmit : frame transmission in progress. • Receive: frame reception in progress. • Busy Rec R: unable to receive a new frame but can transmit frames. • Busy Rec Trm R: unable to receive or transmit frames (wait states insertion). • Busy Rec Trm T : unable to receive or transmit frames (wait states insertion). The suffixes R and T at the end of Busy-state names denote the origin of inactivity: R due to a Reception and T due to a Transmission. To help recover transfer errors, a set of predefined values put into iic recover reg informs the master host on the termination of the transfer. Because of the use of a FIFO, data can be lost since certain latency is necessary for the transmitted byte to move through the FIFO to the receiver. Only five (05) states are possible (Table 3). 2.6. Timing considerations All the issues are to determine the minimal sampling frequency (CLKmin ) for a proper data transfer and to set the necessary timing conditions to make the standard-mode slave-interfaces upward compatible, i.e., can be able to communicate safely with the fast-mode master ones, knowing that these later are downward compatible. Table 3.
Recover register.
Recover register
Description
0x0 0x1
Normal transfer termination Transfer aborted by the slave host (NACK). Bytes in the receiver-FIFO are lost No response from the slave host. From the master side, the frame has been transmitted entirely. After timeout, all bytes in the FIFO (full) are lost No response from the slave host. The master has not yet terminated the transfer. After timeout, transfer is explicitly aborted According to I2 C specifications, the slave host has no possibility to abort the transfer once in transmit state, but in case of no response (after timeout), the last transmitted byte is retransmitted again
0x2 0x3 0x4
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Universal Low/Medium Speed I2C-Slave Transceiver Table 4. Present state
Status register
619
Control-unit FSM.
Transition condition
Possible next state(s)
Sleep
0x0
ENABLE = “1”
Standby
0x1
Address match + W Receive Address match + R + FIFO Transmit not empty Address match + R + FIFO empty Busy Rec Trm T
Receive
0x2
STOP Condition from Master NACK = “1” from Slave Host Receiver-FIFO full + STOP Receiver-FIFO full + not STOP
Busy Rec R Busy Rec Trm R
Recover register
Standby
0x0
Standby
Transmit
0x3
Nack from Master Transmitter-FIFO empty
Standby Busy Rec Trm T
Busy Rec R
0x4
Address match + R End of timeout Receiver FIFO not full
Transmit Standby
0x0/0x1 data lost*
0x0
0x2 data lost 0x0
Busy Rec Trm R
0x5
End of timeout Receiver FIFO not full
Standby Receive
0x3 data lost 0x0
Busy Rec Trm T
0x6
End of timeout
Transmit
0x4 data duplicated 0x0
Transmitter-FIFO not empty Note: (*) recover-register = 0x1 and data lost only when receiver-FIFO is not empty.
The I2 C-bus timing specifications (Fig. 5) define two different transfer rate ranges: • Standard Mode: up to 100 Kbits/s ⇔ SCLmax = 10 µs/bit, • Fast Mode: up to 400 Kbits/s ⇔ SCLmax = 2.5 µs/bit. CLKmin must be able to sample the shortest events tHD;STA , tSU;STA and tSU;STO . This means that CLKmin = min(tHD;STA , tSU;STA , tSU;STO ) which gives the following values: • CLKmin = 4 µs (standard mode), • CLKmin = 0.6 µs (fast mode).
Fig. 5.
Timing for F/S-mode devices on the I2 C bus.
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Fig. 6.
Minimal sampling frequency.
Consequently, we can conclude that • CLKmin = (10/4) SCLmax = 3 SCLmax (standard mode), • CLKmin = (2.5/0.6) SCLmax = 5 SCLmax (fast mode). The only condition (Fig. 6) for a standard-mode slave-interface to be upward compatible is to be able to run at a minimum-clock-frequency (CLKmin ) of 2 MHz so that it can detect the shortest (0.6 µs) fast-mode events (tHD;STA , tSU;STA , tSU;STO ). 3. Interface Specifications The external core interface and a detailed pin description are respectively given by Fig. 7 and Table 6, while Table 5 comprises the configurable parameters of the FIFO. clk nreset din dout adr rw cs
8 8 5
I2C Slave Transceiver
scl Fig. 7.
Table 5. Compile time constants tx fifo length rx fifo length
nempty high_water nfull low_water
sda Core symbole.
Compile time constants. Description Define the size of the transmitter-FIFO Define the size of the receiver-FIFO
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Universal Low/Medium Speed I2C-Slave Transceiver Table 6. Name
Type
621
Pin description.
Bus size
Description
Control Signals clk I nreset I
1 1
External system clock Asynchronous external system reset
I 2 C signals scl sda
I/O I/O
1 1
I2 C bus serial clock line I2 C bus serial data line
Host side interface din I dout O adr I rw I cs I
8 8 5 1 1
Data received from an I2 C-slave device Data to be transmitted to an I2 C-slave device Read/write address for internal registers Read/write operation (“0” = > write; “1” = > read) Chip select
Transfer interrupts nempty O
1
high water
O
1
nfull
O
1
low water
O
1
Asserted when the receiver-FIFO contains at least one data to be read by an I2 C-slave device Asserted when the receiver-FIFO level is equal to or greater than a user defined value high water level Asserted when the transmitter-FIFO contains at least one free position to be filled by an I2 C-slave device Asserted when the transmitter-FIFO level is equal or lower than a user defined value high water level
Note: Signals starting with “n” are low active.
4. Low-Level-Design 5. Verification Plan To ensure that the implemented design fully meet the initial specifications, the design has undergone two types of verification: at core level (cycle accurate test bench) and at board level (C-software test bench.) 5.1. Core level verification Each unit of the architecture is tested separately. First, each unit is challenged against a set of severe special cases, and then against a very large number of random patterns. Once all units tested successfully, the same test process is repeated for the whole I2 C-slave core. For ease of verification, a fully automated verification procedure (self-checking HDL test bench) is used (Fig. 8). For this purpose, we used Unix Gawk tool to generate a parametrizable number of random-pattern files, which are submitted to both the synthetizable RTL code and to the behavioral test bench code for simulation. The simulator (Modelsim), which runs in batch mode, performs a comparison between the delivered results and issues an error if any. In case of error, the Tcsh process is stopped and a visual simulation (wave mode) is performed on the
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Register description.
Register name iic filter reg
Description Spikes shorter than user-defined number of CLK periods are filtered out
iic address reg 7/10 bits user programmable I2 C-salve address Bit6-0: 7 LSB address bits. In case of 7-bits addressing mode, only these bits are considered Bit9-7: 3 MSB address bits for 10-bits addressing mode iic control reg Bit0: ENABLE — when set to “0”, the I2 C-slave enters into a sleep mode, scl & sda lines are put into high impedance state. In this case the slave device is disconnected from the I2 C interface and only the host side interface remains active. Once Enable set to “1”, the I2 C slave enters into standby mode Bit1: RIEN — this bits enables/disables “1”/“0” the outgoing receiver-FIFO interrupts nempty and high water Bit2: TIEN — this bits enables/disables “1”/“0” the outgoing transmitter-FIFO interrupts nfull and low water Bit3: NACK — once in the receive mode, this bit serves to acknowledge the reception of the successive bytes. If set to “1” the I2 C slave receiver will not acknowledge the byte transfer by not pulling down the sda line Bit4: FUEN — enable/disable “1”/“0” the noise-filter-unit Bit7-5: unused
Modelsim Gawk Behavioral Testbench Code Random Pattern Files
Comparison Syntetisable RTL Code
Fig. 8.
Error File
Yes
Visual Simulation
No Tcsh
Automated verification procedure.
responsible pattern-file to localize the bug. In case of no error, the whole process is reiterated using Tcsh (Unix shell tool). 5.2. Board level verification The hardware (evaluation board) used for the SoC application is represented by the PCB of Ref. 23. The system includes an ARM9TDMI as central 32-Bits CPU and different standard IO ports like 10/100 Ethernet and USB 1.1 together with a standard memory bus connecting SRAM, SDRAM, and FLASH to the CPU. A free programmable FPGA for the implementation of approx. 30,000 gates allows any additional digital I/O interface. The system runs under a mini Real Time Operating
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Universal Low/Medium Speed I2C-Slave Transceiver Table 7. Register name
623
(Continued ) Description
iic status reg
0x0: 0x1: 0x2: 0x3: 0x4: 0x5: 0x6:
Sleep Standby Transmit Receive Busy Rec R Busy Rec Trm R Busy Rec Trm T
iic recover reg
0x0: 0x1: 0x2: 0x3: 0x4:
normal transfer data lost (reception) data lost (reception) data lost (reception) data duplication (transmission)
iic trans status reg
iic tx data reg
Bit0: tx low water Bit1: tx nfull Bit3-2: unused Bit4: rx high water Bit5: rx nempty Bit7-6: unused “1” ⇔ event is being signaled Writing to this register puts a new element into the transmitter FIFO
iic tx no reg
Number of elements in the transmitter FIFO [log2(tx length)..0]
iic tx low water reg
A critical user-defined-level of the transmitter FIFO [log2(tx length)..0]
iic tx timeout reg
User-defined-timeout for wait state insertion during the transmit mode
iic timeout now reg iic rx data reg
Current remaining time for wait state insertion before the end of timeout Reading this register extracts the oldest value from the receiver FIFO
iic rx no reg
Number of elements in the receiver FIFO [log2(tx length)..0]
iic rx high water reg A critical user-defined-level of the receiver FIFO [log2(tx length)..0] iic rx timeout reg
User-defined-timeout for wait state insertion during the receive mode
System. A standard ARM based software development toolkit (assembler, compiler, debugging tools etc.), is applied to the system. Concerning the simulation of the total system, all modules are available in a common data base as HDL file or PLI file (for ARM9TDMI) as well as at the gate net list level, in a readable or encrypted version. This system has been used to validate our I2 C core at board level. We wrote a C interrupt-driven application using nempty and nfull interrupts that verifies that the frame-transfers between a software FIFO and our I2 C transceiver FIFO are correct. To make the C application independent from the hardware, drivers have been developed (Table 8).
6. FPGA Implementation The implemented I2 C-slave core is configurable, allowing the user to enable/disable features. The synthesis of the I2 C core with all features enabled, including two
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Function name Writable registers iic slave set filter reg iic slave set address reg iic slave set control reg iic slave set tx low water reg iic slave set tx timeout reg iic slave set rx timeout reg iic slave set rx high water reg iic slave disable
I2 C-slave drivers. Description
iic slave transmit byte
Write a value into iic filter reg Write a value into iic address reg Write a value into iic control reg Write a value into iic tx low water reg Write a value into iic tx timeout reg Write a value into iic rx timeout reg Write a value into iic rx high water reg Set the Bit0 of iic slave control reg to “0”, the I2 C slave enters into a sleep mode Set the Bit0 of iic slave control reg to “1”, the I2 C slave enters into a standby mode Set the Bit1 of iic slave control reg to “0”, disable the outgoing receiver-FIFO interrupts nempty & high water Set the Bit1 of iic slave control reg to “1”, enable the outgoing receiver-FIFO interrupts nempty & high water Set the Bit2 of iic slave control reg to “0”, disable the outgoing transmitter-FIFO interrupts nfull & low water Set the Bit2 of iic slave control reg to “1”, enable the outgoing transmitter-FIFO interrupts nfull & low water Set the Bit3 of iic slave control reg to “0”, the slave receiver will acknowledge the reception of data Set the Bit3 of iic slave control reg to “1”, the slave receiver will not acknowledge the reception of data Set the Bit4 of iic slave control reg to “0”, disable the noise-filter-unit Set the Bit4 of iic slave control reg to “1”, enable the noise-filter-unit Put a new element into the transmitter FIFO
Readable registers iic slave get status reg iic slave get recover reg iic slave get trans status reg iic slave get transmitter status iic slave get receiver status iic slave get tx no reg iic slave get tx low water reg iic slave get timeout now reg iic slave get rx no reg iic slave get rx high water reg iic slave read byte
Read the content of iic status reg Read the content of iic recover reg Read the content of iic trans status reg Read the content of Bit0 and Bit1 of iic trans status reg Read the content of Bit4 and Bit5 of iic trans status reg Read the content of iic tx no reg Read the content of iic tx low water reg Read the content of iic timeout now reg Read the content of iic rx no reg Read the content of iic high water reg Extract the oldest value from the receiver FIFO
iic slave enable iic slave rx int disable iic slave rx int enable iic slave tx int disable iic slave tx int enable iic slave rx ACK iic slave rx NACK iic slave filter disable iic slave filter enable
4-bytes FIFOs, consumes 431 slices of a Xilinx’s VirtexII FPGA (Table 9) and exhibits a time-to-setup delay of 12 ns which corresponds to a clock rate of 83 MHz. Two instances of Filter and FIFO modules are used. The FIFO module is based on a reconfigurable bank of registers (ring buffer) with dynamic read/write pointers for low power consumption. The whole design code either for synthesis or verification is written in Verilog 2001 (IEEE 1365). The synthesis design code is technologyindependent.
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Universal Low/Medium Speed I2C-Slave Transceiver Table 9.
625
Number of slices per module.
Module Filter FIFO I2 C-slave low level protocol I2 C-slave
Number of slices 12 70 104 431
7. Concluding Remarks Based on a recent market investigation of a significant number of I2 C devices (datasheets) from different vendors, this paper addressed the design and implementation of an up-to-date universal low/medium-speed I2 C-slave-transceiver including all necessary features that might be required by modern ASIC/SoC applications, except the high-speed mode. We went through all necessary VLSI-implementation steps, starting from the elaboration of initial specifications, till verification, and synthesis. All decisions concerning relevant implementation issues have been thoroughly discussed and justified through a set of tables and figures, making the whole design easily reproductible.
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