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A High-Performance Multicell Topology Based on Single-Phase Power Cells for Three-Phase Systems Operating Under Unbalanced AC Mains and Asymmetrical Loads Carlos R. Baier, Student Member, IEEE, José R. Espinoza, Member, IEEE, Javier A. Muñoz, Student Member, IEEE, Luis A. Morán, Fellow, IEEE, and Pedro E. Melín
Abstract—This paper presents a multicell converter topology composed of N single-phase power cells per phase and a multipulse power transformer. The topology achieves high-powerquality waveforms in three-phase applications under the presence of severe unbalanced ac mains. Moreover, the power cells are properly arranged in order to achieve high-performance ac supply current waveforms under asymmetrical loads. The configuration is based on single-phase power cells that feature a pulsewidthmodulation rectifier in order to achieve an overall unitary displacement power factor and a controlled dc-link voltage at the power-cell level. The configuration is implemented, and different experimental tests are performed where unbalance and distortion indexes are computed. Index Terms—AC–AC power conversion, insulated-gate bipolar transistor, multicell single-phase topology, multilevel system, power electronics, variable-speed drives.
I. I NTRODUCTION
M
ULTILEVEL topologies based on series connection of power cells are an attractive alternative for mediumvoltage levels where power quality is of main concern. They can operate at high power levels by using standard semiconductors and feature high reliability indexes [1]–[5]. As an alternative, 1φ-input/1φ-output power cells have been reported recently [6]–[11] where lesser power valves are required as compared with 3φ-input/1φ-output power cells. However, little discussion has addressed the importance of how to connect them with the multipulse transformer, aiming to improve the overall performance, particularly under unbalanced ac mains and asymmetrical loads.
Manuscript received March 14, 2009; revised August 7, 2009; accepted October 5, 2009. Date of publication November 20, 2009; date of current version July 14, 2010. This work was supported by the Chilean Government under Project FONDECYT 108-0247. C. R. Baier is with the Department of Electrical Engineering, University of Concepción, Concepción 160-C, Chile, and also with the Department of Industrial Technologies, University of Talca, Talca 747-C, Chile (e-mail:
[email protected]). J. R. Espinoza, J. A. Muñoz, L. A. Morán, and P. E. Melín are with the Department of Electrical Engineering, University of Concepción, Concepción 160-C, Chile (e-mail:
[email protected];
[email protected];
[email protected];
[email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TIE.2009.2036637
On the other hand, the increment in the number of singlephase loads and, thus, asymmetrical (or unbalanced) threephase loads, such as electric welding machines, electric cookers, electrified trunk lines, and electrostatic precipitators, have increased the problems related with voltage unbalances and harmonic pollution [12]–[14]. This is mainly due to the fact that asymmetrical loads produce voltage unbalances in the distribution system because of the asymmetrical drop across the distribution line. To overcome these problems, new singlephase sources that use two-phase transformers and single-phase induction motors have been proposed [12]. In commercial distribution systems, an uninterruptible power supply could be used in order to confine the load current unbalance at the load side and behave as an overall balanced system to the ac mains, and static power converters have been proposed for electrified railroads [13]. The commercial converter based on 3φ-input/1φ-output power cells [1]–[3] is capable of feeding, with one of its output phases, a single-phase load while keeping balanced overall input ac currents. The multilevel converter based on 1φ-input/1φ-output power cells presented in [8] is improved in this paper in order to feed asymmetrical loads and admit simultaneously unbalanced ac supply voltages with high overall input and output quality indexes. In particular, the regulated dc-link voltage in the power cells minimizes the load voltage unbalance under ac mains unbalances, and the proper rearrangement of the power cells mitigates the ac supply current unbalance under asymmetrical loads. II. M ULTICELL C ONVERTER BASED ON S INGLE -P HASE -I NPUT /S INGLE -P HASE -O UTPUT P OWER C ELLS A power converter based on 1φ-input/1φ-output power cells permits several alternatives to assemble the power cells. In particular, when N power cells are used to form one phase of the load [Fig. 1(a) and (b)] for N = 3, there is an interesting option that is proposed in this paper, shown in Fig. 1(b), which is based on the already reported configuration [Fig. 1(a)]. This paper shows that both topologies are best suitable for unbalanced ac mains; however, the proposed arrangement is the best option for unbalanced ac mains and asymmetrical loads [15]. This is
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BAIER et al.: HIGH-PERFORMANCE MULTICELL TOPOLOGY BASED ON SINGLE-PHASE POWER CELLS
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Fig. 1. Three-phase indirect ac-to-ac topology based on 1φ-input/1φ-output power cells. (a) Conventional arrangement. (b) Proposed arrangement. (c) 1φ-input/1φ-output power cell with one-switch boost rectifier. (d) 1φ-input/1φ-output power cell with four-switch boost rectifier.
due to the even distribution of the load asymmetry throughout the primary windings of the power transformer, which results in balanced ac mains currents. Similarly, unbalanced ac mains voltages are symmetrically distributed across the load voltages without the need for compensating the negative sequence at the converter level. This paper also shows two types of 1φ-input/1φ-output power cells, as shown in Fig. 1(c) and (d), that can regulate the dc-link voltage as required by the proposed power cell [Fig. 1(b)]. Thus, the dc-link voltage is equal to a given reference and allows the operation at a unitary displacement power factor. Hence, the topology behaves as a buffer for the ac supply voltage unbalances. The 1φ-input/1φ-output power cell shown in Fig. 1(c) is composed of a diode-based rectifier, a single power valve in order to regulate the dc-link voltage, and an inverter that finally produces the desired load voltage contribution. This alternative allows the control of the input displacement power factor and compensates the voltage unbalance that may exist in the ac mains, which causes sags/swells at the input of the 1φ-input/ 1φ-output power cells [16]. This compensation is done at the dc-link-voltage level by regulating its value to a given reference. The second 1φ-input/1φ-output power cell [Fig. 1(d)] is a regenerative type of cell. Similarly, this configuration allows the control of the dc-link voltage and the input displacement
power factor by means of the controlled rectifier. Additionally, it allows the bidirectional power flow, which is an advantage as compared with the previous 1φ-input/1φ-output power cell [Fig. 1(c)]. However, an important drawback is the reduced reliability due to the four commutated power valves as compared with just one commutated power valve of the 1φ-input/ 1φ-output power cell shown in Fig. 1(c). In this paper, the cell shown in Fig. 1(c) is finally implemented. However, the analysis is done for both configurations and can be easily extended to an arbitrary number of cells (N = 1, 2, 3, . . .). Similarly, the voltage unbalance is compensated by regulating the dc-link voltage to a given reference value. III. C ONTROL S TRATEGY FOR THE P OWER C ELL BASED ON THE S INGLE -S WITCH R ECTIFIER The voltage unbalance produces different dc-link voltages in the power cell that considers a diode-based rectifier stage [8]. Hence, if each cell keeps the dc-link voltage constant regardless of the ac mains unbalance, then the topology becomes immune to unbalanced ac supply voltages. An additional objective is to achieve a high input displacement power factor. There are several alternatives to control the single-switch-based rectifier [Fig. 1(c)] that can achieve the two previous objectives as found in [16]–[20].
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Fig. 3. Characteristic input current waveforms in hysteresis control (a) for nominal operation and (b) for 50% sag in the ac mains.
IV. T OPOLOGY U NDER AN U NBALANCED AC M AINS Fig. 2. Control scheme for one-switch boost rectifier [Fig. 1(d)].
The hysteresis control presents advantages such as the simplicity to be implemented, stability, and the possibility to work at very low switching frequencies. Although the switching frequency is variable, the power topology configuration allows working with a wide hysteresis band because the residual current harmonics are finally mitigated at the power transformer stage, as confirmed later on. The control scheme shown in Fig. 2 consists of a master– slave strategy where the slave loop is the hysteresis current loop. This slave loop uses, as the higher hysteresis band, the PI block Cv output times the absolute value of the supply voltage of the respective cell. The lower limit of the hysteresis band is given by B, as shown in Fig. 2. It is important to point out that the hysteresis band (given by B) and the size of the dc-link capacitor of the power cell are designed considering a nominal supply voltage and nominal load power. In particular, the dc-link capacitor must be designed to assure a given dc voltage ripple (< 10%) that is mainly defined by the second current harmonic injected by the operation of both the 1φ inverter and 1φ rectifier. Additionally, for higher supply currents (due to a higher load power or a supply voltage sag), the higher and lower limits of the hysteresis bands get increased proportionally. This is an advantage as higher current levels will reduce the switching frequency. This important feature can be verified in the simulated results shown in Fig. 3. Clearly, the supply current in the power cell is nearly sinusoidal; however, the current ripple due to the switching frequency imposes some restrictions in the power transformer design as the K-factor becomes close to three (as found according to extensive simulated results). With respect to the selection of Cv , the dynamics of this controller is limited only by the size of the dc-link capacitor, because the inner hysteresis current loop is considerably faster.
The conventional and proposed arrangements present nearidentical performance indexes in both the ac mains currents and load voltages when unbalanced ac mains and symmetrical loads are considered. This is due to the presence of the dclink-voltage control loop making each power cell operate as a constant power type of load. For typical unbalance factors in the ac mains voltages (less than 5%), the supply currents remain almost balanced and without an important increment of the harmonic distortion, as shown in the following. A. Analysis for Unbalanced AC Mains For the delta–wye part of the power transformer, one can write ⎤ ⎡ ⎤⎡ a⎤ ⎡ a v(+30) 1 −1 0 vs ⎦ =g⎣ 0 ⎦ ⎣ vsb ⎦ ⎣ v b 1 −1 (+30) c vsc −1 0 1 v(+30) ⎡ a⎤ vs = gT+30 ⎣ vsb ⎦ (1) vsc ⎡ a ⎤ ⎤ ⎡ ⎤ ⎡i a is(+30) (+30) 1 0 −1 ⎢i b ⎥ ⎥ ⎢ b 0 ⎦ ⎣i(+30) ⎣ s(+30) ⎦ = g ⎣ −1 1 ⎦ 0 −1 1 i c i c s(+30) (+30) ⎡ a ⎤ i(+30) ⎢i b ⎥ T = gT+30 ⎣ (+30) ⎦ (2) i c (+30) where g is the voltage ratio, vsa , vsb , and vsc are the phase volta b c , v(+30) , and v(+30) are the phase ages at the ac mains, v(+30) a b c , i , and i are the line voltages at the wye side, i (+30)
(+30)
(+30)
a b c , is(+30) , and is(+30) are currents in the wye side, and is(+30) the contributions of the wye side currents to the delta side.
BAIER et al.: HIGH-PERFORMANCE MULTICELL TOPOLOGY BASED ON SINGLE-PHASE POWER CELLS
For simplicity, but without losing generality in the analysis, if the phase a voltage features a different voltage, one can write ⎡ a⎤ ⎛ ⎞ vs (Vsa , ∠0◦ ) ⎣ vsb ⎦ = ⎝ (V, ∠ −120◦ ) ⎠ . (3) vsc (V, ∠120◦ ) Using (1), the secondary voltages can be written as ⎡
⎤
⎡
a v(+30) ⎢ ⎢ ⎣ v b ⎦ = g⎢ (+30) ⎢ c ⎣ v(+30)
(Vsa )2
(Vsa )2
+V
+V
Vsa
√
+V
2 , ∠atan
◦
3V, ∠ −90
Vpa
+ V 2 , ∠ −atan
√
3V 2Vsa +V
√
⎤
3V 2Vsa +V
⎥ ⎥ ⎥ ⎥ ⎦ (4)
where V is the rms voltage of phases b and c and Vsa is the rms voltage of phase a of the ac mains. Considering the cell lossless, that it behaves as a constant power type of load, and the input displacement power factor near unity due to the hysteresis controller, then the supply line currents can be written as a = I(+30)
Pox = a N Vs(+30)
Ng
Pox
b = I(+30)
Pox Pox √ = b N V(+30) N g 3V
c I(+30) =
Pox = c N V(+30)
Ng
(5)
(Vsa )2 + V Vsa + V 2 (6) Pox
(7)
(Vsa )2 + V Vsa + V 2
a b c where I(+30) , I(+30) , and I(+30) are the rms currents in the wye side of the power transformer, N is the number of cells per phase, and Pox is the output power in any phase of the converter as a symmetrical three-phase load is being considered. Because the unity displacement power factor is ensured by the hysteresis controller, there is no phase shift between the phase voltages and the respective line currents. Thus, using the secondary currents given by (5)–(7) and the respective phases given by (4) as a function of the unbalanced voltages of the ac mains, the ac mains currents can be found as a contribution of the wye side of the power transformer using (2). These are x Po 2Vsa + V ◦ i a , ∠0 (8) s(+30) = N g (Vsa )2 + V Vsa + V 2 ⎞ ⎛ ⎛ ⎞ 2 x 2 a a 7V + V Vs + (Vs ) b i b ⎠ ⎝Po ⎝ ⎠, ∠θs(+30) s(+30) = 2 Ng 2 a a 2 3V (V ) + V V + V s
s
(9) ⎛ ⎞ ⎞ 2 x 2 a a 7V + V Vs + (Vs ) c i c ⎠ ⎝Po ⎝ ⎠, ∠θs(+30) s(+30) = 2 Ng 2 a a 2 3V (V ) + V V + V ⎛
s
s
(10)
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b c = − θs(+30) θs(+30)
⎞ 2 (Vsa )2 + 2V Vsa + 5V 2 ⎠ − 180◦ √ = atan⎝ 3 (2Vsa V + V 2 ) ⎛
(11)
a b c where is(+30) , is(+30) , and is(+30) are the phasors of the line currents contributed by the delta–wye winding of the power transformer. Using these expressions, the sequence components and, thus, the unbalance factor can be obtained as i n (Vsa )2 −2V Vsa +V 2 s(+30) ◦ = , ∠180 . (12) uis(+30) = p i (Vsa )2 +4V Vsa +4V 2 s(+30)
The contributions of the other secondaries can be found using a similar analysis as presented in [5], the resulting expressions are i n (Vsa )2 − 2V Vsa + V 2 s(+30) ◦ = , ∠60 (13) uis(+10) = p i (Vsa )2 + 4V Vsa + 4V 2 s(+30) i n (Vsa )2 − 2V Vsa + V 2 s(+30) uis(+50) = p = , ∠ − 60◦ . a )2 + 4V V a + 4V 2 i (V s s s(+30) (14) It is possible to see that the magnitude of the unbalance factor for the ac mains currents is the same in the three secondaries (12)–(14). This magnitude becomes the maximum possible where a constant power type of load is being assumed and is given by Ui_ max =
(Vsa )2 − 2V Vsa + V 2 . (Vsa )2 + 4V Vsa + 4V 2
(15)
Additionally, considering (3) and its decomposition in sequence components, the magnitude of the unbalance factor for the ac mains voltages can be written as
n (Vsa )2 − 2V Vsa + V 2 V Uv = sp = . (16) Vs (Vsa + 2V ) Using (15) and (16), a relation between the maximum unbalance factor for ac mains currents Ui_ max and the unbalance factor for ac mains voltages Uv in per unit is found to be Ui_ max = Uv2 .
(17)
Furthermore, the multiple phase-shifted secondaries allow the different negative sequence currents (present in unbalanced conditions) to be added with different phase angles at the primary side of the transformer; on the contrary, the positive sequence currents are added with the same angle. This feature leads to a natural compensation of the negative sequence currents present in the secondaries and, therefore, of the unbalanced load currents [8] (specifically (20)–(23) and Fig. 3). Therefore, there would be a lower value for the unbalance factor in ac mains currents than the value given by (17) and shown in Fig. 4. Considering that typical industrial ac mains unbalances
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and the magnitude as a function of the output powers is n is(+30)
=
(Pou )2 + (Pov )2 + (Pow )2 − Pou Pov − Pov Pow − Pow Pou √ . NV 3 (22)
Due to the angles of the secondary voltages, the magnitude of the negative sequence in the ac mains becomes as shown in (23) at the bottom of the page. Computing the positive sequence, the magnitude of the unbalance factor can be calculated as a function of the load powers resulting in Fig. 4. Unbalance factor of the primary currents versus the unbalance factor of the ac mains voltages for symmetrical loads.
do not go beyond 5% [21], the resulting current unbalance could be negligible.
uis = 0.84 ⎞ ⎛ (Pou )2 +(Pov )2 +(Pow )2 − Pou Pov − Pov Pow − Pow Pou ⎠. ×⎝ Pou +Pov +Pow (24)
B. Asymmetrical Loads in the Conventional Arrangement The conventional and proposed arrangements behave differently under an asymmetrical load (unbalanced load) as compared with the performance under an unbalanced ac mains. This is mainly due to the different load power sharing produced in the power-cell arrangements. If the ac mains voltages are balanced with an rms value V and considering the power cells lossless (the average input and output powers are identical), the secondary currents in the conventional arrangement become Pou NV Pv = o NV Pw = o NV
a a a I(+10) = I(+30) = I(+50) =
(18)
b I(+10)
(19)
b = I(+30)
=
b I(+50)
c c c = I(+30) = I(+50) I(+10)
This result confirms that the conventional arrangement presents current unbalance at the ac mains stage under asymmetrical loads. C. Asymmetrical Loads in the Proposed Arrangement In the proposed arrangement implemented with power cells featuring a controlled dc-link voltage and considering similar conditions than the previous analysis, one can write for the secondary currents a b c I(+10) = I(+10) = I(+10) =
Pou NV
(25)
a b c I(+30) = I(+30) = I(+30) =
Pov NV
(26)
a b c = I(+50) = I(+50) = I(+50)
Pow NV
(27)
(20)
where Pou , Pov , and Pow are the active powers in the output phases u, v, and w of the topology. The expressions (18)–(20) show that the rms currents are proportional to the active powers being taken in each phase. The secondary currents are in phase with the supply voltages due to the hysteresis control, and thus, it is possible to compute the negative sequence component contributed to the primary side of the power transformer. The results show that the contributions are the same in terms of magnitude, i.e., n n n (21) = is(+50) is(+10) = is(+30)
and because there is no unbalance in any secondary of the multipulse transformer, the magnitude of the negative sequence in all three secondaries is equal to zero. This is true even if the three phases deliver different active powers. Thus n n n (28) i(+10) = i(+30) = i(+50) = 0. Finally, due to the null value of the negative sequence component in all secondaries, the unbalance factor for the ac mains current is just zero.
⎛ ⎞ u )2 + (P v )2 + (P w )2 − P u P v − P v P w − P w P u (P o o o o o o o o o n ⎠ √ is = 2.532 ⎝ NV 3
(23)
BAIER et al.: HIGH-PERFORMANCE MULTICELL TOPOLOGY BASED ON SINGLE-PHASE POWER CELLS
Fig. 5. Experimental setup. (a) Programmable power source. (b) Multipulse transformer. (c) Multicell arrangement. (d) Single- and three-phase motors as loads. (e) PC host for the DSP-based system. (f) Data acquisition and oscilloscopes.
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Fig. 7. Currents for an 8% unbalanced ac mains in both arrangements. (a) Currents in the wye-side. (b) Primary current as a contribution of the wye-side currents. (c) AC mains current considering all contributions from the secondaries. (d) Spectra of (a). (e) Spectra of (b). (f) Spectra of (c).
Fig. 8. Test for an 8% unbalanced ac mains voltage in both arrangements. (a) AC mains voltages. (b) Input currents. (c) Output voltages. (d) Spectra of (a). (e) Spectra of (b). (f) Spectra of (c).
Fig. 6. Nine-cell converter. (a) Multicell arrangement. (b) Power cell with single-phase one-switch boost rectifier. (c) PC host for the DSP-based system and fiber-optic driver. (d) Nine isolated sources to feed rectifiers. (e) Nine isolated sources to feed inverters. (f) Data acquisition and oscilloscopes.
V. E XPERIMENTAL R ESULTS Both topologies shown in Fig. 1 have been implemented, and a general view is shown in Fig. 5. The multicell prototype, shown in Fig. 6, was designed to deliver a maximum of 1.5 kVA. The rectifiers in the cells [Fig. 6(b)] have an independent analog control implemented according to Fig. 2. For the multilevel inverter, the modulating technique and control algorithms are implemented in a DSP-based system [Fig. 5(e)]. The gating signals [Fig. 6(c)] are sent to the driver of each power cell via fiber optic in order to electrically isolate the
control and power stage and to reduce the noise-based troubles. Each cell [Fig. 6(a)] works with a switching frequency of 550 Hz in the inverter stage. This leads to a first set of unwanted harmonics at 2 · 3 · 550 Hz = 3.300 Hz in the load voltages due to the appropriate carrier-signal phase shift used by the modulating technique algorithms [1]. Fig. 7 shows the effects of having an 8% voltage unbalance in the ac mains in the secondary currents [Fig. 7(a)], in the primary currents contributed by the wye-side currents [Fig. 7(b)], and in the currents in the ac mains [Fig. 7(c)]. The results show that the ripple and unbalance present in the secondary windings is reduced due to the magnetic coupling of the power transformer. Fig. 8 shows the null effect on the load voltages and ac mains currents. Figs. 9 and 10 show, for the conventional and proposed arrangements, respectively, the key waveforms for an 8%
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Fig. 9. Key waveforms for the conventional arrangement [Fig. 1(a)] under unbalanced ac mains and asymmetrical loads. (a) AC mains voltages. (b) Input currents. (c) Output voltages. (d) Load currents. (e) Spectra of (a). (f) Spectra of (b). (g) Spectra of (c). (h) Spectra of (d).
7.2% overall unbalance factor. The reduction in the total harmonic distortion for this case (Table I) is due to the hysteresis control that increases the switching frequency as the current being controlled decreases. This phenomenon, combined with the effect produced by the contribution of several secondaries, explains the cleaner ac mains currents (Fig. 3). Fig. 10 shows the key waveforms for the proposed arrangement for an 8% unbalanced ac mains voltage while feeding an asymmetrical load that presents a 20% impedance unbalance (and identical conditions as used for the conventional arrangement). The results shown in Table I indicate an identical residual unbalance factor of the ac mains currents of about 0.7% in both symmetrical and asymmetrical loads. This is mainly due to the unbalance in the ac mains voltages. Finally, Fig. 11 shows how an asymmetrical load impact affects the currents of the ac mains. In both cases, the two converters have a considerable load impedance asymmetry of about 38% before the impact in one phase of the load. The asymmetry is about 58% at the load side after the load impact. For the conventional arrangement [Fig. 11(b)], the results show that the ac mains currents present a 20% overall unbalance factor before the load impact and 24% after the load impact. In the case of the proposed arrangement [Fig. 11(c)], despite the asymmetrical load in the converter, this presents balanced currents in the ac mains after and before the same asymmetrical load impact. Moreover, during the transient, the ac mains current remains also balanced. VI. C ONCLUSION
Fig. 10. Key waveforms for the proposed arrangement [Fig. 1(b)] under unbalanced ac mains and asymmetrical loads. (a) AC mains voltages. (b) Input currents. (c) Output voltages. (d) Load currents. (e) Spectra of (a). (f) Spectra of (b). (g) Spectra of (c). (h) Spectra of (d).
unbalanced ac mains voltage while feeding an asymmetrical load that presents a 20% impedance unbalance. The results are summarized in Table I. Fig. 9 and Table I show the results for the conventional arrangement and indicate that the ac mains currents present a
This paper studies a multicell topology based on 1φ-input/ 1φ-output power cells. The power cells feature a unitary displacement power factor and a regulated dc-link voltage that minimizes the load voltage unbalance under ac mains unbalances and a proper rearrangement of the power cells that minimizes the ac supply current unbalance under asymmetrical loads. Experimental results confirm that, under an 8% ac mains voltage unbalance, the residual supply current unbalance is at most 0.7% and features a 6.1% harmonic distortion (for a balanced three-phase load). An additional test included the presence of an asymmetrical three-phase load—with 20% unbalanced impedances—while keeping the 8% ac mains voltage unbalance. In this case, the conventional arrangement presents a 7.2% unbalance factor in the ac mains currents and a 5.7% harmonic distortion; on the contrary, the proposed arrangement presents just a 0.7% unbalance factor in the ac mains currents and a 5.7% harmonic distortion. Additionally, experimental results show that the ac mains currents in the proposed arrangement either increase or decrease symmetrically when the load presents asymmetrical impacts. The conventional arrangement is a simpler topology as the power cells require lesser power valves; however, its performance is reduced under asymmetrical loads. Instead, the proposed arrangement can handle unbalanced ac mains voltages as well as asymmetrical loads keeping high-power-quality indexes requiring a multiple of three power cells per phase.
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TABLE I R ESULTS OF THE S IMULATION T ESTS ON D IFFERENT C ONNECTIONS AND C ONDITIONS
Fig. 11. Input currents during an asymmetrical load impact for the conventional and proposed arrangements under a balanced ac mains. (a) Load currents. (b) Conventional-arrangement input currents. (c) Proposed-arrangement input currents.
ACKNOWLEDGMENT The authors would like to thank the Applied Digital Control Laboratory, Universidad de Concepción, Chile, for the technical support. R EFERENCES [1] P. W. Hammond, “A new approach to enhance power quality for medium voltage ac drives,” IEEE Trans. Ind. Appl., vol. 33, no. 1, pp. 202–208, Jan./Feb. 1997. [2] P. Hammond, “Enhancing the reliability of modular medium-voltage drives,” IEEE Trans. Ind. Appl., vol. 49, no. 5, pp. 948–954, Oct. 2002. [3] J. Rodríguez, P. Hammond, and J. Pontt, “Operation of a medium-voltage drive under faulty conditions,” IEEE Trans. Ind. Electron., vol. 52, no. 4, pp. 1080–1085, Aug. 2005. [4] M. A. Pérez, J. Espinoza, J. Rodríguez, and P. Lezana, “Regenerative medium-voltage ac drive based on a multicell arrangement with reduced energy storage requirements,” IEEE Trans. Ind. Electron., vol. 52, no. 1, pp. 171–180, Feb. 2005. [5] J. Wang and Y. Li, “PWM rectifier in power cell of cascaded H-bridge multilevel converter,” in Proc. Int. Conf. Elect. Mach. Syst., Seoul, Korea, Oct. 8–11, 2007, pp. 18–21.
[6] P. Lezana, J. Rodríguez, and D. Oyarzún, “Cascaded multilevel inverter with regeneration capability and reduced number of switches,” IEEE Trans. Ind. Electron., vol. 55, no. 3, pp. 1059–1066, Mar. 2008. [7] P. Lezana, J. Rodríguez, D. Rojas, and J. Pontt, “Novel cell based on reduced single-phase active front end for multicell converters,” in Proc. 31st IEEE IECON, Raleigh, NC, Nov. 6–10, 2005. [8] C. R. Baier, J. Guzmán, J. Espinoza, M. A. Pérez, and J. Rodríguez, “Performance evaluation of a multicell topology implemented with singlephase nonregenerative cells under unbalanced supply voltages,” IEEE Trans. Ind. Electron., vol. 54, no. 6, pp. 2969–2978, Dec. 2007. [9] P. Lezana, J. Rodríguez, M. A. Pérez, and J. Espinoza, “Input current harmonics in a regenerative multi-cell inverter with single-phase active rectifiers,” IEEE Trans. Ind. Electron., vol. 56, no. 2, pp. 408–417, Feb. 2009. [10] P. Lezana, C. Silva, J. Rodríguez, and M. A. Pérez, “Zero steady-state error input current controller for regenerative multilevel converters based on single-phase cells,” IEEE Trans. Ind. Electron., vol. 54, no. 2, pp. 733– 740, Apr. 2007. [11] M. D. Manjrekar, P. K. Steimer, and T. Lipo, “Hybrid multilevel power conversion system: A competitive solution for high-power applications,” IEEE Trans. Ind. Appl., vol. 36, no. 3, pp. 834–841, May/Jun. 2000. [12] C. Zhu, X. Wang, H. Zhong, X. Zhang, and R. Zhang, “Analysis and design of a new single-phase power source,” in Proc. 8th ICEMS, vol. 3, pp. 1784–1787.
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[13] T. A. Kneschke, “Control of utility system unbalance caused by singlephase electric traction,” IEEE Trans. Ind. Appl., vol. IA-21, no. 6, pp. 1559–1570, Nov/Dec. 1985. [14] P. E. Sutherland, G. L. Hostetter, and J. W. Hughes, “Harmonic filter design for mixed single-phase three-phase load,” in Proc. IEEE/IAS Ind. Commercial Power Syst. Tech. Conf./ICPS, 2008, pp. 1–9. [15] C. R. Baier, J. R. Espinoza, L. A. Morán, C. Sepulveda, and L. Landaéta, “A convenient form to connect single-phase cells to multi-pulse transformer in unbalanced system,” in Proc. IEEE 39th Power Electron. Spec. Conf., Jun. 15–19, 2008, pp. 3748–3753. [16] B. Singh, B. Singh, A. Chandra, K. Al-Haddad, A. Pandey, and D. Kothari, “A review of single-phase improved power quality ac–dc converters,” IEEE Trans. Ind. Electron., vol. 50, no. 5, pp. 962–981, Oct. 2003. [17] M. Kazerani, P. D. Ziogas, and G. Joos, “A novel active current waveshaping technique for solid-state input power factor conditioners,” IEEE Trans. Ind. Electron., vol. 38, no. 1, pp. 72–78, Feb. 1991. [18] G. MacNee and B. Andreycak, “Zero voltage switched power factor correction techniques for industrial applications,” in Proc. HFPC, Jun. 1991, pp. 46–60. [19] M. Morimoto, K. Oshitani, K. Sumito, S. Sato, M. Ishida, and S. Okuma, “New single-phase unity power factor PWM converter–inverter system,” in Proc. IEEE Power Electron. Power Conf., 1989, pp. 585–589. [20] J. Salmon, “Circuit topologies for single-phase voltage-doubler boost rectifiers,” IEEE Trans. Power Electron., vol. 8, no. 4, pp. 521–529, Oct. 1993. [21] A. von Jouanne and B. Banerjee, “Assessment of voltage unbalance,” IEEE Trans. Power Del., vol. 16, no. 4, pp. 782–790, Oct. 2001.
Carlos R. Baier (S’08) was born in Temuco, Chile, in 1979. He received the B.S. and M.Sc. degrees in electrical engineering from the University of Concepción, Concepción, Chile, in 2004 and 2006, respectively, where he is currently working toward the Ph.D. degree in electrical engineering. Since 2009, he has been a Professor with the Department of Industrial Technologies, University of Talca, Talca, Chile, where he is teaching in the areas of automatic control and power electronics. His research interests include improved control techniques for multicell converters and the implementation of low-cost control systems for medium-voltage converters.
José R. Espinoza (S’92–M’97) received the Eng. degree in electronic engineering and the M.Sc. degree in electrical engineering from the University of Concepción, Concepción, Chile, in 1989 and 1992, respectively, and the Ph.D. degree in electrical engineering from Concordia University, Montreal, QC, Canada, in 1997. Since 2006, he has been a Professor with the Department of Electrical Engineering, University of Concepción, where he is engaged in teaching and research in the areas of automatic control and power electronics. He has authored and coauthored more than 100 refereed journal and conference papers and contributed to one chapter in the Power Electronics Handbook (Academic Press, 2008). Dr. Espinoza is an Associate Editor of the IEEE T RANSACTIONS ON I NDUSTRIAL E LECTRONICS and the IEEE T RANSACTIONS ON P OWER E LECTRONICS.
Javier A. Muñoz (S’08) was born in Concepción, Chile, in 1983. He received the Eng. degree in electronic engineering (with honors) and the M.Sc. degree in electrical engineering from the University of Concepción, Concepción, in 2007 and 2008, respectively, where he is currently working toward the D.Sc. degree in electrical engineering in the area of digital control of multicell power converters.
Luis A. Morán (S’79–M’81–SM’94–F’05) was born in Concepción, Chile. He received the Eng. degree in electrical engineering from the University of Concepción, Concepción, in 1982 and the Ph.D. degree in electrical engineering from Concordia University, Montreal, QC, Canada, in 1990. Since 1990, he has been with the Department of Electrical Engineering, University of Concepción, where he is currently a Professor. He has extensive consulting experience in the mining industry, particularly in the application of medium-voltage ac drives, large-power cycloconverter drives for semiautogenous grinding mills, and power-quality issues. His main research areas are in ac drives, power quality, active power filters, flexible ac transmission systems, and power protection systems. He has written and published many papers on active power filters and static VAR compensators in IEEE Transactions. Dr. Morán was the Associate Editor of the IEEE T RANSACTIONS ON P OWER E LECTRONICS from 1997 to 2001. He was the recipient of the IEEE Outstanding Paper Award from the Industrial Electronics Society in 1995 for the Best Paper published in the IEEE T RANSACTIONS ON I NDUSTRIAL E LECTRONICS and the City of Concepción Medal of Honour for Achievement in Applied Research in 1998. He was recently appointed as a Distinguished Lecturer of IEEE for the period 2008–2009.
Pedro E. Melín was born in Chillán, Chile, in 1982. He received the Eng. degree in electronic engineering from the University of Concepción, Concepción, in 2006, where he is currently working toward the M.Sc. and D.Sc. degrees in electrical engineering in the area of multilevel current-source converter topologies.
