A hybrid multilevel inverter system based on

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TPEL-Reg-2012-08-1152.R1

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A hybrid multilevel inverter system based on dodecagonal space vectors for medium voltage IM drives Jaison Mathew, Member IEEE, Mathew K., Member IEEE, Najath Abdul Azeez, Rajeevan P.P. and Gopakumar K., Fellow IEEE  Abstract— Dodecagonal (12-sided) space vector PWM schemes are characterized by the complete absence of (6n±1)th order harmonics (for odd n) in the phase voltages, within the linear modulation range and beyond, including over-modulation. This paper presents a new topology suitable for the realization of such multilevel inverter schemes for induction motor (IM) drives, by cascading two-level inverters with flying-capacitor-inverter fed floating H-bridge cells. Now, any standard IM may be used to get the dodecagonal operation which hitherto was possible only with open-end winding IM. To minimize the current THD, a strategy for synchronous PWM is also proposed. It is shown that the proposed method is capable of obtaining better THD figures, compared to conventional dodecagonal schemes. The topology and the PWM strategy are validated through analysis and subsequently verified experimentally. Index Terms— multilevel inverters, flying capacitor, THD, induction motor drive, dodecagonal space vector, space vector modulation.

I. INTRODUCTION ultilevel inverters are often considered for high-power applications as the power stage may be realized using devices rated at lower voltages. As the step waveform produced by multilevel operation is closer to a sinusoid, the harmonic distortion in the load current is quite low. For a given current distortion, a higher number of voltage levels will permit lower switching frequencies. The additional benefits of multilevel inverters are lower common-mode voltages and reduced EMI. Grid-connected applications such as reactive power compensation and photovoltaic interconnections also benefit, as the filter requirement is less stringent, due to the improved voltage quality. With all the above advantages, multilevel inverters are gaining popularity in diverse applications [1]. The most popular multilevel inverter families are the diode-clamped (NPC), flying capacitor (FC) and the cascaded H-bridge (CHB) topologies [1-3]. In addition to these basic topologies, many interesting configurations have been reported in literature over the years [4-8]. The space vector structures due to most of these multilevel inverter topologies are hexagonal in shape and for multilevel

M

Manuscript received August 21, 2012; revised September 30, 2012. The authors are with Department of Electronic Systems Engineering (Formerly Centre for Electronics Design and Technology), Indian Institute of Science, Bangalore-560012, India. (e-mail: [email protected]; [email protected]; [email protected]; [email protected]; [email protected])

operation; it is subdivided into many triangular regions. Even though the harmonic performance of these multilevel inverters is better than its two-level counterpart, it is found that for low switching frequencies or during over-modulation, there are substantial amounts of fifth and seventh harmonic components in the load current, resulting in losses associated with current and torque ripples. Further, in these cases, the current-control schemes become less accurate and additional control schemes may be necessary to get satisfactory performance [9]. To take care of this issue, a dodecagonal space vector structure was proposed in [10], which eliminates all (6n±1)th order harmonics (for odd n) for the entire modulation range. Multilevel inverters based on dodecagonal space vector diagram were presented in [11] and [12] which relied upon open end winding induction motors as the load because the open end winding schemes allowed the required phase voltage levels to be generated quite easily by feeding it from both ends of the windings. The topology reported in [11] used diode clamped multilevel inverter and that in [12] used flying capacitor based inverters for the generation of dodecagonal space vectors. The proposed topology utilizes cascade connection of flying capacitors and floating H-bridge cells in combination with basic two level inverters to generate the same phase voltage levels as that in [11] and [12] for the generation of dodecagonal space vectors thus allowing any standard induction motor as the load. The disadvantage of open end winding induction motor is that six wires are to be drawn from the inverter terminals to the motor, which is not possible in certain applications/the voltage reflections in the wires are excessive. Of the methods used for the speed control of induction motors, namely sine-triangle PWM and space vector PWM, the latter that provides extra modulation range is naturally preferred. The idea of injecting a common-mode voltage in the reference phase voltages to enhance the modulation range was introduced in [13]. Reference [14] discusses the concept of space vector modulation based on space vector theory in detail. A simple method for space vector modulation for two-level inverters based on sampled amplitudes of the reference voltages was proposed in [15]. The space vector PWM (SVPWM) technique illustrated in [12] discussed how the technique may be extended to dodecagonal space vectors. It is a well-understood fact that the way in which the PWM switching sequences are applied has a significant influence on the harmonic performance of the drive. However, this topic was not discussed in [12]. In this paper, this aspect is also taken into account and the notion of ‘harmonic flux trajectories’ and ‘stator flux ripple’ proposed in [16] and [17] respectively, are used to analyze the harmonic

Copyright (c) 2011 IEEE. Personal use is permitted. For any other purposes, permission must be obtained from the IEEE by emailing [email protected].


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Fig. 1. (a) The proposed topology for the generation of Multilevel dodecagonal space Vectors (b) Multilevel Dodecagonal Space Vector Diagram used

performance of the various PWM switching patterns. Although the PWM method used in the present work is similar to that in [12], the modification in the switching sequence in the PWM algorithm yields significant improvements in harmonic performance. The proposed topology and PWM scheme are extensively simulated and experimentally verified. II. THE PROPOSED INVERTER TOPOLOGY A. Description of the topology and space vector diagram The proposed topology for nine-level (asymmetric) pole voltage generation is shown in Fig. 1a. Each leg of the inverter system consists of a six-level inverter cascaded with a floating capacitor H-bridge cell to achieve a nine-level inverter. The six-level inverter in turn consists of a three-level flying capacitor inverter stacked between two 2-level inverters. The nominal voltage of the capacitors in the flying capacitor cells (C1,C2 and C3) is 0.5 VDC and that of the capacitors in the H-bridge cells (C4,C5,C6) is 0.183 VDC where VDC is the dc link voltage of the system. The switches in the two level inverters are to be rated to block reverse voltage of 0.366VDC. The switches in the flying capacitor inverter are to be rated for 0.5 VDC and that in the floating H-bridge cells are to be rated for 0.183 VDC. The pole-voltage levels and the corresponding switching combinations for a phase leg are given in Table 1. An attractive feature of this topology would be that faulty H-bridge cells maybe effectively bypassed to give a six-level inverter. i.e., with all the H-bridge cells bypassed, we can still have the pole voltage levels 0, 0.366VDC, 0.5VDC, 0.866VDC, VDC and 1.366VDC (6 levels). With these voltage levels, we can generate 3 dodecagons instead of 6 dodecagons and have dodecagonal space vector based multilevel operation. But the PWM algorithm must be modified to take this eventuality. Likewise,

if there are faults elsewhere in the converter circuit, the converter cannot generate dodecagonal space vector based multilevel operation, but hexagonal based multilevel operation is possible with much reduced power outputs. Both capacitor voltages in a leg are controlled by utilizing the switching state redundancies in a PWM cycle, as explained later. Of the set of all space vectors given by Eqn. 1, those vectors whose tips lie on the vertices of twelve sided polygons (dodecagons) are selected to obtain the space vector diagram shown in Fig. 1 b. 



VR  Vao  Vbo e j120  Vco e j 240 (1) where Vao,Vbo and Vco represent the pole voltages of the system. As mentioned earlier, the PWM based on dodecagonal space vectors gives better harmonic performance when the switching frequency is low or the operation is in the over-modulation region. Compared to [11] and [12], the outer regions in the space vector diagram (corresponding to 35.7Hz-50Hz) in this work is subdivided into different triangular regions such that in a carrier period, vectors nearest to the reference vector are applied at all times. The asymmetrical dc link voltages required for the topology can be easily obtained from the power supply scheme shown in Fig. 2, where the particular type of transformer winding connections will improve the source side power factor also [11][22]. But at low speeds of operation, the improvement in power factor is not significant. B. The generation of different voltage levels and the algorithm for capacitor voltage balancing As mentioned earlier, all the capacitor voltages in a phase leg may be controlled using switching state redundancies. Depending on the direction of load current and the voltage in each capacitor, the switches in a phase leg are operated to charge the capacitors to proper voltages so that the required pole-voltage levels are obtained [12]. Fig. 3 shows how a

Fig. 2. Scheme for the generation of the asymmetrical dc link voltages Fig. 3. Four different ways of generating the pole voltage level 0.683VDC (Vc1=0.5VDC, Vc4=0.183VDC) Copyright (c) 2011 IEEE. Personal use is permitted. For any other purposes, permission must be obtained from the IEEE by emailing [email protected].


TPEL-Reg-2012-08-1152.R1 pole-voltage of 0.683VDC may be obtained using different switching combinations. Table I gives the switching combinations required to keep the capacitor voltage at the correct level for phase-A while providing the required pole voltages. The switching states have been selected so as to give the lowest voltage stress across the devices also. For example, for S2=0, S1 state can very well be a ‘don’t care’ state. But when we look at the reverse voltage for the device S2, we can see that the switch state S1=0 (S1’=1) will yield lower reverse voltage across the switch S2. As the capacitor voltage control occurs once in every sampling period and the capacitor voltage is controlled using switching state redundancies, stiff voltage control can be achieved in all modulation ranges irrespective of the load power factor, provided the switching frequency is sufficiently high for the chosen capacitor values. III. SPACE VECTOR PWM FOR THE TOPOLOGY A. PWM timing computation from the sampled amplitude of the reference voltages A method based on the sampled amplitudes of the reference voltages is used in this paper to eliminate the complex matrix

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manipulations and look-up table operations required in conventional space vector PWM methods [14]. Although fully carrier-based implementations of space vector modulation are in use [15][18], these approaches do not allow choice of the switching combination. The choice of switching sequence in a subcarrier cycle has a major role in the THD performance of the system [19]. The method used in this paper offers the flexibility of choosing the switching sequences as desired, while also maintaining the simplicity of carrier-based space vector methods. The analysis of the influence of switching sequences on the harmonic performance of the system is provided in the next section. It is clear that the locus of the reference voltage space vector (Vref) in the space vector diagram is decided by the speed requirement of the motor (See Fig. 4a). The three-phase reference voltages corresponding to this space vector trajectory may be obtained using the transformation, 0  Va   2 / 3 V    1 / 3 1 / 3  V  (2)  V   b  Vc   1 / 3 1 / 3      

TABLE I THE AVAILABLE POLE VOLTAGES AND THE REQUIRED SWITCHING COMBINATION FOR PHASE-A Pole voltage Levels

Current Direction

0.183VDC

+ + -

0.366VDC

0.5VDC

0.683VDC

0.866VDC

+ + + + + + + + -

1VDC

1.183VDC

1.366VDC 0

+ + -

VC1

VC4

S1

S2

S3

S4

S5

S6

NA NA NA NA unaffected more less more less more more less less more more less less more less more less unaffected NA NA NA NA unaffected unaffected

more less more less

0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 0 0 0 1 1 0 1 0

0 0 0 0 0 0 1 1 0 0 0 1 1 1 1 0 0 0 1 1 0 1 1 1 1 1 1 0

0 0 0 0 0 1 0 0 1 1 1 0 0 0 0 1 1 1 0 0 1 1 1 1 1 1 1 0

0 1 1 0 1 0 1 1 0 0 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 0

0 1 1 0 0 0 0 0 0 0 1 0 1 1 0 1 0 0 0 0 0 0 0 1 1 0 0 0

1 0 0 1 0 0 0 0 0 1 0 1 0 0 1 0 1 0 0 0 0 0 1 0 0 1 0 0

NA NA NA NA more less more less more less more less NA NA NA NA more less more less

Notes: + –> current direction is towards motor more –> capacitor voltage is more than rated NA–> Not affected S1 & S1’ are complementarily switched. S2 & S2’, S3 & S3’, S4 & S4’, S5 & S5’ and S6 &S6’ are also switched in a similar manner. The nominal voltage of C1 is 0.5 VDC and that of C4 is 0.183 VDC



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Fig. 4: (a) The hexagonal sectors S1 to S6 and the locus of the voltage reference vector, Vref. (b) The derivation of the hexagonal sector timings from the reference voltage waveform.

where Vα and Vβ are obtained by projection of the reference space vector on to the α and β axes respectively. Consider the resulting three-phase waveform as shown in Fig. 4b. The hexagonal sector in which the reference vector is located, may be identified using the sampled amplitudes of the reference voltages. For example, if Va>Vb>Vc then the sector is identified as sector-I (S1), if Vb>Vc>Va, then sector-II and so on. Further, the timings of the active vectors T1Hex and T2Hex for a hexagonal sector in conventional 2-level space vector modulation may also be computed from the sampled amplitudes of the reference voltages. For odd numbered sectors (See Fig. 4a),  T1Hex  Ts Vmax  Vmid  (3) T     2 Hex  V1Hex Vmid  Vmin  For even numbered sectors,  T1Hex  Ts  Vm id  Vmin  T     2 Hex  V1Hex Vmax  Vmi d 

(4)

where Ts denotes the sampling period, Vmax, Vmid and Vmin represent the maximum, mid and minimum amplitudes of the reference voltage respectively. V1Hex is the radius of the outermost hexagonal pattern of the space vector diagram which is the same as the dc link voltage (1.366 VDC). If the reference vector is inside a particular hexagon sector, say the first sector S1, then it can be further inferred that for T1Hex  T2 Hex , the reference vector is inside the first 30° region (dodecagonal sector) of the hexagon sector. Else, it will be in the second half of the hexagon sector. Fig. 5 shows the first 30° region of the hexagonal sector S1 enclosed within the vectors V1Dod and V2Dod, which are fictitious vectors having the same vector length as V1Hex . The respective timings T1Dod and T2Dod of the vectors V1Dod and V2Dod can be obtained by equating the real and imaginary parts of the following equation. Vref Ts  (| V1Hex | 0) T1Hex  (| V2 Hex | 60) T2 Hex

 (| V1Dod | 0) T1Dod  (| V2 Dod | 30) T2 Dod (5) Now, for multilevel operation, the space vector diagram is partitioned to many triangular regions as shown in Fig. 1b.From the above discussion, it may be noted that the computation of the hexagonal sector timing from the sampled amplitudes of the reference voltage is quite similar to that of carrier based techniques. But the PWM timing required for each triangle that falls in a 15° region to realize the reference vector in an average sense is computed based on vector

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Fig. 5: The hexagonal sector S1 and its first 30˚ region, shown as enclosed within the vectors V1Dod and V2Dod

approach. i.e., the magnitude and angle of the vectors (which we already know from the vector locations) making up a triangle is used to compute the required vector switchingtimings. For example, if the reference vector is inside a triangle (See Fig. 5), it is a straightforward task to get the timings from the already computed vector timing using the concept of volt second balance as used in Eqn.(5) and as detailed in [12]. After such mapping of the hexagonal vector timings in to the inner triangles, the triangle which gives positive values for its vector-timings can be identified as the only triangle, the vectors of which can realize the reference vector in an average manner. Since the algorithm requires only a few scaling operations, summations and comparisons, the method is much faster compared to conventional multilevel space vector modulation algorithms. A more detailed description of the PWM method may be found in [12]. B. Harmonic analysis using the concept of stator flux ripple This section illustrates the analytical method used to compare the PWM switching strategies used in connection with the proposed topology. Based on this analysis, it is shown the next section that a variation in the switching sequence in a PWM carrier period could yield improvements in the THD performance in certain frequency ranges. In fact, the PWM modulation scheme along with the proposed switching strategy can be used in the case of other multilevel inverters also to get better harmonic performance. As the reference voltage vector is realized using the available voltage vectors only in an average sense, there exists an instantaneous error between the reference and the applied voltage vectors which results in a ripple in addition to the fundamental voltage. The load seen by harmonic voltages is largely the leakage inductance of the motor, as the slip tends to be much higher at these frequencies. The line current ripple is therefore proportional to the integral of the voltage ripple, which was termed as ‘stator flux ripple’ in [17]. Various synchronous PWM techniques may be compared on basis of the stator flux ripple. The analysis presented here also uses the definition of harmonic flux trajectory (HFT) from [16], in which the harmonic flux (stator flux ripple) in the Nth carrier cycle is defined as: ~



( N 1)Ts



(Vk  Vref ) dt

( 6)

NTs

where, Ts denotes the switching interval; Vref, the reference vector and Vk, the space vector used.



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Fig. 6(a) The voltage vectors V1,V2,V3, the reference vector Vref and the corresponding error vectors (b) The harmonic flux trajectories in a half-carrier cycle for the position of the reference voltage Vref (dotted lines: when the sequence 3123 is used, solid lines: when the sequence 1231 is used)

While a per-carrier cycle analysis of the HFT provides information regarding the peak and local stresses on the power devices, a per-fundamental cycle analysis of the same is required for the computation of current ripple, torque ripple and associated losses [16]. Consider the case when the reference vector located inside the triangular region formed by vectors 25, 13 and 26 in Fig. 1b as shown in Fig. 6a.The voltage errors are ~

7

V1  V1  Vref ~

8

~

9

V2  V2  Vref V3  V3  Vref

Fig. 6b shows the HFTs for two PWM sequences for a given half-carrier-cycle. Since the HFT for the second-half-carrier cycle shall be symmetric to that for the first half, it is sufficient to analyze a single half-carrier cycle. The RMS ~

~

~

~

value of the stator flux ripple  (where     j  ) over a half-carrier cycle may be easily computed by its resolution into alpha and beta components as shown in Fig. 6b and in Fig. 7. The flux ripple values for the conventional SVPWM sequence 3-1-2-3, where 1, 2 and 3 represent vectors V1, V2 and V3 respectively, when different voltage vectors applied are: ~

~

~

~

1  V1 T1 | V1 | cos(V1 )T1 ~

~

~

~

2  V2 T2 | V2 | cos(V2 )T2 ~

~

 3  V 3 ~

~

~ ~ T T3 | V3 |co s ( V3 ) 3 2 2 ~

~

1  V1 T1 | V1 | sin ( V1 )T1 ~

~

~

~

2   V2  T2 | V2 | sin ( V2 )T2 ~

~

10 

Fig. 7. The decomposition of flux ripple in to their alpha and beta components when the sequence 3123 is used

~

~

~

~

~

~

Qa  3 , Qb  3  1 , Qc  3  1  2 ~

~

~

~

~

(16)

~

Qd  3  , Qe  3  1 , Q f  3   1  2 

(17)

The α-axis and β-axis flux ripples that are piece-wise linear functions of time when squared, become parabolic and the area under these parabolic sections is to be evaluated to get their mean square values. Thus, ~ T 1 (  ) 2  [Qa 2 3  (Qa 2  Qa Qb  Qb 2 )T1  3Ts 2 T (Qb 2  Qb Qc  Qc 2 )T2  Qc 2 3 ] (18) 2 ~ T 1 ( ) 2  [Qd 2 3  (Qd 2  Qd Qe  Qe 2 )T1  3Ts 2 T (Qe 2  Qe Q f  Q f 2 )T2  Q f 2 3 ] (19) 2 Therefore, ~

( RMS ) 2  ~

(

RMS

)2 

Ts

1 Ts

~

2  ( ) dt

1 Ts

0 Ts

(20)

~

2  ( ) dt

(21)

0

The per-carrier cycle RMS value of the harmonic flux may be then calculated as: ~

~

~

11

 RMS 

1 2 

Due to the 12-fold symmetry, the per-fundamental cycle RMS harmonic flux for the dodecagonal case may be calculated as:

13  14 

~ ~ T T3 | V3 | sin(V3 ) 3 15 2 2 The timings T1, T2 and T3 correspond to the vectors V1, V2 and V3. It may be noted that the first and last vectors are applied for equal time duration in a half carrier cycle. Fig. 7 illustrates the development of α and β components of the stator flux ripple for a half-carrier cycle, where the magnitudes Qa, through Qf are representative values of the ripple flux for the switching sequence and may be written as:

3  V3

5

~

( RMS )2  (



 F , RMS 

1 

6



RMS

)2

(22)

~

(RMS )2 d

(23)

6 0

Where d  corresponds to the angular movement of the reference vector in the space vector diagram. The perfundamental cycle RMS value of harmonic flux, usually represented in per unit, is termed as the harmonic distortion factor (HDF). ~

 F , RMS HDF  1

(24)



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Fig. 8. Four locations of the reference space vector in a triangular region TABLE II PER-CARRIER CYCLE HARMONIC FLUX RIPPLE CORRESPONDING TO DIFFERENT POSITIONS OF THE REFERENCE VOLTAGE

~

 RMS ( volt-sec) p.u. Location

Vref

Proposed PWM sequence

Conventional SVPWM sequence

a

1.1