A Java Processor for Mobile Devices

10.4-4 A Java Processor for Mobile Devices Tan Y i p , Lo Kai Man, Mok Pak Lun, Yu Wing Shing and Anthony S. Fong, Senior Member, IEEE City University of Hong Kong, Kowloon, Hong Kong

ALslract-This paper presents a novel Java processor named jHISC for mobile devices, which is a RISC based processor with some Object-Oriented (00)feature enhancements and supports 00 related operations in hardware directly. Compared with PicoJava n, its performance is improved deeply.

I. INTRODUCTION As a result of its 00 features and corresponding advantages o f security, robustness and platform independence, Java is widely applied in mobile devices, such as PDA, mobile phone, Palm PC and TV set-up box 111, [ 2 ] ,which also stimulates researchers to develop high-performance Java processors [ 3 ] [SI. Until now, these solutions are mainly based on three ways to support bytecodes: replacing Java virtual machine by a hardware stack machine, hardware translation and coprocessor. But almost all of them execute 00 related bytecodes by software traps or microcode which may cost several ten clock cycles [ 5 ] .Thus the executions of 00 related operations have significant impact on the overall performance of Java program due to their distributions about 15% of all operations [9], especially in mobile devices, where real-time operations and low power consumption are required in the case of limited memory. Furthermore, with so many application programs written by other programming languages available now, it may be desirable to have a general-purpose processor with enhanced architecture features to support object-oriented programming in hardware directly, which leads us to develop JHISC, a Java processor supporting 00 related operations at hardware level. 11. OBJECT REPRESENTATION

the base address of object header after object is resolved. In object context, each component is stored with a constant address offset to the object header, thus some components can be accessed in parallel to reduce the access overhead. 111. INSTRUCTION SET AND SYSTEM ARCHlTECTURE Basically, jHISC is a RISC based processor with some 00 features enhancement and its instruction set i s compatible with MIPS 32 except the memory-register data transfer and 00 instructions. In jHISC, all data are encapsulated into objects and the bound control checks will be performed before data are accessed to avoid the security holes caused by accessing memory directly in traditional computers. In addition, jHISC also provides object manipulation instructions to handle &he related operations. Excluding 64-bit operation instructions, Java bytecodes are full supported, with 91% of bytecodes and 75% of 00 related bytecodes implemented in hardware directly. The other performance sensitive bytecodes not implemented in hardware are executed through software traps, such as “new”, “newarray”, etc. Since its instruction set is compatible with MIPS 32, the application program written by other programming languages can run on jHISC platform. The block diagram of the whole system is shown in Fig. I, which is implemented by 5 pipelines, including instruction fetch, instruction decoding, data fetch, execution and writeback. . .5

,I i1 , 1 1ns;ti;m W1 Instruction Fetch Unit

Instructions

Object representation method is a key factor to improve the access speed to an object. In jHISC, an object i s represented by hardware readable data structure -object context, which consists of object header, data space and corresponding descriptor tables, etc. An instance context includes object header, instance header and instance data space. A class context consists of object header, class header, class operand and property descriptor table, class data space. And a method context includes object header, method header, method code space and local variable frame for local variable storage. In addition, when applied to represent an array, an instance context also includes array data area. Typically, each object has a unique object context and a reference always points to

Prediction

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Register

Fig. 1. Block diagram of system architecture This work was supported i n part by City University of Hong Kong under Strategic Research Grant 7001548.

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Iv. PERFORMANCE ESTIMATION A prototype of processor core has been made by FPGA to verify our concept and the corresponding chip is currently under development. Since the time cost by instruction executions is not exact in P G A , the performance analysis results in this section are mainly based on estimates, partly from simulations of the back annotated layout. And PicoJava I1 is also chose to analyze the performance for it is an open source and a full functional Java processor. To compare the execution performance between jHISC and PicoJava 11, we count the clock cycle number needed by some main object-oriented related bytecode executions in both systems. It is assumed in the course of counting that, (1) all the objects are resolved, and ( 2 ) all data are hit in data cache. Also, for PicoJava I1 each instruction included into software traps assumably consumes only one clock cycle and the time cost by 00 related instructions handler (such as exception handling, etc.) is ignored. The comparison results are shown in table I in detail. TABLE I

THE NUMBER OF CLOCK CYCLES NEEDED BY SOME MAIN 00

to locate and check the related fields of object in constant pool in sequence. However, in jMSC, the related fields of object are accessed in parallel due to their constant offset to object header. At the same time, the field and access checking are also done by hardware. All these help to improve the performance in jHISC.

v.

CONCLUSION

jHISC architecture provides efficient and secure platform for Java applications. Firstly, both the hardware implementation of complex 00 related bytecodes and parallel access of object information contribute to the overall performance improvement since it uses hardware readable data structure to represent object and each filed of object is stored in a specific address. Secondly, built-in bounds checking to guarantee no out-of-boundary accessing objects results in the enhancement of security because all information is encapsulated into objects and no operations access memory directly. Thirdly, both NSC-based architecture with enhanced features to support direct hardware object-oriented programming and instruction set compatible with MIPS 32 make it possible for the application programs written by other object-oriented programming languages to run on jHISC. REFERENCE

[I] M. Watheq, E. Kharashi, F. Gebali, K. F. Li and Fang Zhang, “The JAFARDD Processor: A Java processor based on a folding algorithm, with reservation stations, dynamic translation and dual processing,” IEEE Transactions on Consumer Electronics, vol. 48, no. 4, November 2002, pp. 1004-1015 iretum

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If we normalize the clock cycles needed by each bytecode execution and its distribution weighting 191, the overall performance of PicoJava I1 and jHISC are shown in table 11.

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TABLE II

ave; ;mber of clock cles for each bytecode execution in PicoJava ll The average number of clack cycles for each bytecode execution in ‘HISC The average number of clock cycles for each main 00 related b eccde execution in PicoJava If The average number of clack cycles for each main 00 related b cccde execution in ‘HISC

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From the above tables, the efficiency of executing main 00 related operations is speeded up 11.4 times and the overall performance is improved about 575% by jHISC. When an 00 related bytecode is executed in FicoJava 11, much time is cost

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[2] Y. M. Lee, B. C. Tak, H. S . Maeny, S. D. Kim, “Realtime Java virtual machine for information appliances,” IEEE Transactions on Consumer Electronics, vol. 46, no. 4, November 2000, pp. 949-957 [3] J. Michael O’Connor, M. Tremblay, “PicoJava I: the Java virtual machine in hardware,” IEEE MICRO, March, 1997, pp. 45-53. [4] H. McChan, J. Michael OConnor, “PicoJava: A direct execution engine for Java Bytecode,” Computer, October 1998, pp. 22-30. [5] Sun Microsystems, “PicoJava-11: Java processor core,” Sun Microsystems data sheet, April 1998. [6] dile Systems, Inc, “aJ-100 real-time low power JavaTM processor,” aJ-IOOTM Reference Manual, version 2.1, December 2001. [7] ARM, “Jazelle technology for Java application (Data Sheet),” May 2001. [8] NAZOMI Communications Inc, “SA108 - multimedia application processor (Product Brief),” 2003. [9] P. L. Mok, A. S. Fong, K. W. Hau., “Object-oriented processor requirements with instruction analysis of Java programs,” ACM SIGARCH Computer Architecture News archive, vol. 31, issue 5, December 2003, pp. 1015.