A Low-Cost FPGA-based Embedded Fingerprint Verification and
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A Low-Cost FPGA-based Embedded Fingerprint Verification and Matching System Maitane Barrenechea Jon Altuna Miguel San Miguel Signal Theory and Communications Group Department of Electronics University of Mondragon
A Low-Cost FPGA-based Embedded Fingerprint Verification and Matching System
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SW Architecture
Software Implementation on a Leon2 Platform
Custom version of the MINDTCT and BOZORTH3 packages (NIST2). Only those modules required for XYT formatted minutiae output set generation have been used. Input fingerprint image format modified Æ RAW Used fingerprint images fulfil the conditions set for an optimum performance 500 dpi 256 greyscale Bare-C Cross-Compiler GRMON debug monitor
A Low-Cost FPGA-based Embedded Fingerprint Verification and Matching System
7
SW Architecture
Minutiae Extraction Algorithm Input Fingerprint RAW Image
Low Contrast Map Direction Map
Image Maps Binarization
Low Flow Map High Curve Map Quality Map
Minutiae Detection Remove False Minutiae Assess Minutiae Quality Output Minutiae in XYT Format
A Low-Cost FPGA-based Embedded Fingerprint Verification and Matching System
8
SW Architecture
Image Maps
Low Contrast Map: Marks low contrast areas in the image. Direction Map: Represents the main ridge flow direction. Low Flow Map: Identifies image areas with a weak ridge structure.
High Curve Map: Flags high curvature areas in the image.
Quality Map: Assigns a quality level to each block in the image. z Poor quality z Fair quality z Good quality z Very good quality z Excellent quality
A Low-Cost FPGA-based Embedded Fingerprint Verification and Matching System
9
SW Architecture
Binarization & Minutiae Extraction
Binarization A pixel is assigned a binary value based on the ridge flow direction associated with the block the pixel is within. Minutiae Extraction Identify certain pixel patterns Ridge Ending Bifurcation
A Low-Cost FPGA-based Embedded Fingerprint Verification and Matching System
10
SW Architecture
False Minutiae Removal & Quality Assessment
Remove False Minutiae Assess Minutia Quality Two factors are combined to produce a quality measure: Quality Map Pixel Intensity Statistics
z Poor quality z Fair quality z Good quality z Very good quality z Excellent quality
A Low-Cost FPGA-based Embedded Fingerprint Verification and Matching System
A Low-Cost FPGA-based Embedded Fingerprint Verification and Matching System
13
HW Architecture
Initial System Architecture
BOOT PROM I/F
BOOT ROM
SDRAM I/F
SDRAM
APB BUS
Initial system architecture LEON-2 soft-processor GR-XC3S1500 board with the following embedded CACHE DATA INSTR. INTEGER UNIT AHB I/F modules: Leon2 processor 50 MHz AHB CONTROLLER Cache system: AHB BUS 8 KB (data and instruction) AHB/APB Fingerprint Capture IPBRIDGE MEMORY Fujitsu MBF200 fingerprint sensor CONTROLLER UART FINGERPRINT CAPTURE IP
PC
FINGERPRINT SENSOR
GRXC-3S1500 A Low-Cost FPGA-based Embedded Fingerprint Verification and Matching System
14
HW Architecture
Initial System Architecture
Why Leon2? High configurability VHDL code availability (under LGPL license). High performance Best performance per clock cycle High usability Tkconfig graphical configuration tool
A Low-Cost FPGA-based Embedded Fingerprint Verification and Matching System
15
HW Architecture
Running the application on the initial system
The execution of the algorithm is successful in terms of the matching results. Yet the execution time is excessive. MINDTCT occupies 75% of the computation time. MINDTCT acceleration: Mainly floating-point operations Leon2 is a fixed-point processor Leon2 compatible FPUs: LTH Meiko IEEE-754 compliant GRFPU A Low-Cost FPGA-based Embedded Fingerprint Verification and Matching System
FPU
16
HW Architecture
FPU tests
FPU insertion Great increase in the amount of logic Reduce clock frequency Reduce cache sizes Three different system configurations under test 31 MHz and 8KB cache memory. 37 MHz and 8KB cache memory. 40 MHz and 4KB cache memory.
A Low-Cost FPGA-based Embedded Fingerprint Verification and Matching System
17
HW Architecture
FPU tests
Stanford benchmark Measures the execution time in ms for ten small programs. A
Paranoia benchmark Test the compliance with the IEEE-754 floating-point standard A Low-Cost FPGA-based Embedded Fingerprint Verification and Matching System
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HW Architecture
Introducing the GRFPU in the design LEON-2 soft-processor
AHB CONTROLLER
INTEGER UNIT
DATA
INSTR.
FPU AHB BUS
AHB/APB BRIDGE
MEMORY CONTROLLER BOOT PROM I/F
BOOT ROM
SDRAM I/F
SDRAM
APB BUS
AHB I/F
CACHE
UART FINGERPRINT CAPTURE IP
PC
FINGERPRINT SENSOR
GRXC-3S1500 A Low-Cost FPGA-based Embedded Fingerprint Verification and Matching System
19
HW Architecture
Introducing the GRFPU in the design
94.14% execution time reduction (40MHz / 4KB cache). Program completion delay is yet excessive.
A Low-Cost FPGA-based Embedded Fingerprint Verification and Matching System
24
Conclusions Implementation of a fingerprint minutiae extraction and
matching algorithm Spartan3 based low-cost system Embedded Leon2 soft-processor. Minutiae extraction process has been accelerated in a 94.14%. HW co-processor is estimated to speed-up the MINDTCT algorithm up to a 97.89%. Commercial systems use very high frequency clocks. Extrapolating results (400MHz) Æ Minutiae extraction performed in 0’3 s.
A Low-Cost FPGA-based Embedded Fingerprint Verification and Matching System
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A Low-Cost FPGA-based Embedded Fingerprint Verification and Matching System
