A Low-Voltage CMOS Rail-to-Rail Class-AB Input/Output OpAmp With ...

A Low-Voltage CMOS Rail-to-Rail Class-AB Input/Output OpAmp with Slew-Rate and Settling Enhancement Chi-Hung Lin and Mohammed Ismail Department of Electrical Engineering , The Ohio State University, Columbus, OH 43210, USA email: [email protected]

Abstract-A low-voltage CMOS rail-to-rail OpAmp with high slew-rate and fast-settling is presented. The input stage is composed of the complementary differential pairs, a pair of modified current-mode maximum selecting circuits (Maximum Current Selecting Circuit 11) and a class-AB feedback loop circuit. It achieves rail-to-rail operation, constant-gm, high slewrate and fast-settling. With this OpAmp topology, the design can be easily performed for a wide-range of capacitive loads with a large bandwidth-to-powerconsumption ratio. With 2pm and 0.5pm technology respectively, the OpAmp has a high DC gain (>84dB), and has a bandwidth-to-power-consumption ratio of 13.6MHzImW and 25.8MHzImW with capacitive loads of 20pF, 86V/ps, 9OV/ps slew-rate and 159ns, 36x1s settling-time.

I. INTRODUCTION With advanced VLSI technologies, low-voltage lowpower circuits have become increasingly important in analog and mixed-signal VLSI systems. OpAmp is a basic block in analog and mixed-signal-processing circuits, such as AID, D/A circuits and switched-capacitor circuits and filters. Low-voltage rail-to-rail OpAmps usually consume more power because of complicated biasing circuits. This results in a low power-efficiency (GBW x Cload/mW), particularly compared with the digital part of mixed-signal VLSI. For a non-inverting or buffer OpAmp dedicated to large off-chip or interface loads, rail-to-rail input/output , high output-driving and fast-settling are mandatory. In low-voltage applications, a rail-to-rail operation is considered for keeping a wider input/output signal swing range and good signal-to-noise ratio (SNR). In order to reduce signal-distortion and compensation problems, constant-g, over the entire rails becomes necessary for high performance. A modified universal constant-g, approach (MCSC 11) [l]is used to achieve this requirement. High bandwidth and high CMRR over the entire rails are realized by MCSC I1 with lower power dissipation. For enhancing the speed of the OpAmp and maintaining low quiescent power, a class-AB input stage is often needed. So far, many class-AB or slew-rate enhanced input architectures [2]-[6]may not be suitable for low-voltage applica0-7803455-3/98/%10.00 0 1998 IEEE

tions because of stacked or composite transistors. A novel low-voltage class-AB feedback bias circuit [7] is used together with the modified universal constant-g, approach to implement a LV/LP OpAmp with high performance levels at higher speed. In section 11, the basic operation principles and circuit inplementations are introduced. Simulation results and comparisons with the other different low-voltage rail-torail OpAmp topologies are analyzed and presented in section 111.

11. OPERATION PRINCIPLE AND CIRCUIT IMPLEMENTATIONS There are many methodologies [1][8]-[16] to realize constant-g, for achieving easy compensation and low signal distortion. But most of them need either a complicated bias circuit to control tail currents of complementary pairs or a large bias current for a compact bias circuit [8][9]. This means a high-frequency deterioration and more power consumption. Especially for wide-bandwidth and high-speed design, a larger bias current is usually necessary for obtaining this requirement. Of course, this costs more power dissipation in the circuit. It seems to be a painful trade-off between wide-band, high-speed and low-power. For resolving the above problems, a modified Maximum-Current-Selecting-Circuit (MCSC 11) [l] (see Fig.1) has been proposed. Two additional NMOS transistors, in dashed-line block, can be added to steer two, l o u t l a ) to output stage. Thus, times signal current (Ioutl compared with the conventional approach by increasing two-times bias current for higher unity-gain-frequency and slew-rate, two-times gm for small-signal and twotimes slew current for large-signal can be obtained by the methodology (MCSC 11) without increasing the bias current and much more power in the input stage. Repeating the approach (see the dashed-line transistors in Fig.l), low-power consumption can be realized without deteriorating the required performance [l]. Also, MCSC I1 can accommodate high-frequency operation because of its current-mode signal processing. Two high-swing cascode PMOS current mirrors are utilized for high-frequency stability. On the other hand, the offset voltage may be larger

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~

because of the process mismatch in MCSC 11s and PMOS current mirrors, so statistical model analysis [17] is recommended for the layout design.

In some high-speed applications, high slew-rate and fast-settling is required. Increasing the bias current can obtain the effect, but the power consumption grows tremendously. A simple low-voltage class-AB feedback loop circuit [7] is introduced into the input stage to promote the slew-rate and settling. Overall input stage in Fig.2 can operate at a minimum supply-voltage of 2V. The current sources of the differential pairs are connected with the feedback loop. For a small input-signal, the feedback loop still balances two voltage-nodes, V,, and Vj2. So constant-g, behavior is maintained (see Fig.3). While a large input-signal is used instead of the small inputsignal, the minimum-selecters (see the dashed-line blocks) incites Vf, and V,,. Therefore, large slew-currents charge the differential pairs to output (see Fig.4). High slew-rate for the large signal and fast-settling and constant-g, for the small signal can be set properly.

A compact class-AB buffer output gain stage [lo] (see Fig.5) is used t o drive in-parallel resistive and capacitive loads. The class-AB characteristics consumes less quiescent power and has a faster response for transient signals. Because of the cascode class-AB control with gain stage, the minimum supply-voltage of the rail-to-rail output stage is 2.7V. Other class-AB output stages [1][12]can be accommodated with the input stage for lower supplyvoltage (>2V)applications.

entia1 pairs going into thle output stage are fairly constant by using MCSC 11. Many rail-to-rail constant-g, OpAmps [$I-[16] would encounter a reduced CMRR problem [18] at the entire common-mode input rails because of the summing constant-g, approach. Since this low-voltage class-AB feedback bias circuit controls the current-source transistors of the complementary differential pairs, only three constant-g, approaches [1][8][9]may co-operate with this class-AB feedback bias circuit. In addition tal [l],constant-g, approaches of the other two OpAmps [8][9] need 8 times bias current to have the same 9, level at output as well [l]. They should consume more power than this proposed methodology for achieving the same performance. Although another low-voltage rail-to-rail class-AB OpAmp [19] has good performance, several aspects may not be optimal for low-voltage and constant-g, applications. Since it uses a stack of transistors in tlhe input stage, low power-supply (more less than 3V) may not work in this case. On the other hand, its g, variation percentage is around 28%, this "approximate" summing constant-g, approach also reduces CMRR in rails. Its CMRR at low-frequency just exceeds 70dB. Its total power dissipation is 0.95mW with 3.3V power supply and 5MHZ unity-gain-frequency. The proposed OpAmp has 0.84mW power dissipation for 3.3V power supply and 7MH:z unity-gain-frequency. Both of them drive lOOpF capacitive output loads.

IV. CONCLUSION

111. THESIMULATION RESULTSAND

COMPARISONS OF

DIFFERENTLOW-VOLTAGE RAIL-TO-RAIL OPAMPSTOPOLOGIES The two-stage OpAmp drives a resistive load, 2.5kR, and a capacitive load, 20pF, in parallel. The variation of unity-gain-frequency at entire common-mode input rails is around 12%. The performance of the QpAmp in 2pm and 0.5pm process-model simulation is listed in Table I. Unity gain buffer is used to simulate THD with VC,=1.5V and almost 3V output signals swing. Because the OpAmp with 2pm process model has the dominant pole at lower frequency than the OpAmp with 0.5pm process model, this results in the increased THD with reduced gain at 100kHz.

A low-voltage rail-to-rail class-AB input/output OpAmp has been presented. This OpAmp has a superior performance to achieve different requirements, such as wide-bandwidth, high slew-rate and fast-settling. For high-speed circuits, the OpAmp can optimize the overall performance. With sub-micron technology (LO.5pm), the proposed OpAmp can be easily applied in VHF applications.

Table I1 shows that the comparisons between different low-voltage rail-to-rail OpAmps topologies. Clearly, the performance of the proposed OpAmp is excellent in every aspect, such as power-effiency, slew-rate, settling and CMRR. CMRR of the proposed OpAmp is always maintained high within the entire common-mode input voltage range (see Fig.6), because two tail currents of N-PMOS differ-

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Fig. 1.

Fig. 2. The input stage of rail-to-rail class-AB input/output OpAmp

REFERENCES [l] C.-H. Lin and M. Ismail, “A Low-Voltage Low-Power CMOS OpAmp with Rail-to-Rail Input and Output,” Pmc. of 1997 IEEE 40th Midwest Symposium on Circuits and Systems , Sacramento, August, 1997. [2] R. Klinke, B. J. Hosticka, and H.-J. Pfleiderer, ” A Very-HighSlew-Rate CMOS Operational Amplifier,” IEEE J. Solid-state Circuits , vol. 24, no. 3, pp. 744-746, June, 1989. [3] E. Seevinck and R. F. Wassenaar, ”A Versatile CMOS Linear Transconductor/Square-Law Function Circuit,” IEEE J . SolidState Circuits, vol. SC-22, no. 3, pp. 366-377, June, 1987 [4] B. W. Lee and B. J. Sheu, ”A High Slew-Rate CMOS Amplifier for Analog Signal Processing,” IEEE J . Solid-state Circuits, vol. 25, no. 3, pp. 885-889, June, 1990 [5] S. Sen and B. Leung, ” A Class-AB High-speed Low-Power Operational Amplifier in BiCMOS Technology,” IEEE J . SolidState Circuits, vol. 31, no. 9, pp. 1325-1330, September., 1996 [6] M. E. Pulkin and 3. A. Connelly, ”A NEW CMOS DIFFERENTIAL AMPLIFIER CIRCUIT FOR IMPROVED SLEW RATE PERFORMANCE,” Proc. of 1996 IEEE Midwest Symposium on Circuits and Systems, vol. 3, pp. 961-964, 1996 [7] V. N. Ivanov, M. V. Ivanov and M. Ismail, I’ High Slew Rate Micropower CMOS OTA with Class AB Input Stage,” Pmc. of 1997 IEEE Midwest Symposium on Circuits and Systems, August, 1997. [8] R. Hogervorst, 3. P. Tero and J. H. Huijsing, ” Compact CMOS Constant-g, Rail-to-Rail Input Stage with g,-Control by an Electronic Zenor Diode,” IEEE J. of Solid-state Circuits , vol. 31. no. 7, pp. 1035-1040, July, 1996. [9] V. I. Prodanov and M. M. Green, ”Simple Rail-to-Rail Constant-Transconductance Input Stage Operating in Strong Inversion,” Pmc. of 1996 IEEE Midwest Symposium on Circuits and Systems, vol. 2 , pp. 957-960, 1996 [lo] R. Hogervorst, J. P. Tero, R. G . H. Eschauzier, and J. H. Huijsing, ”A Compact Power-Efficient 3V CMOS Rail-to-Rail Input/Output Operational Amplifier for VLSI Cell Libraries,” IEEE J. of Solid-state Circuits, vol. 29, no. 12, pp. 1505-1513, December, 1994. [ll] E. Peeters, M. Steyaert, W. Sansen, ”A fully differential 1.5V low-power CMOS operational amplifier with a rail-to-rail current-regulated constant-g, input stage,” IEEE Custom Integrated Circuits Conference , pp. 75-78, 1997. [12] K.-J. de Langen and J. H. Huijsing, ”Compact 1.8V Low-Power CMOS Operational Amplifier Cells for VLSI,” IEEE ISSCC97 Digest of Technical Papers, pp. 346-347, 1997 [13] G . Ferri and W. Sansen, ”A 1.3V Op/amp in Standard 0.7pm CMOS with Constant-gm and Rail-to-Rail Input and Output

5 -

2.6

Fig. 3. The transconductance, gmn, g m p , gmt, of the input stage

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TABLE I1 The comparisons between different low-voltage rail-to-rail OpAinp topologies

I T e L I Slew-Rate I

OpAmps

I

Settling

CMRR

I

VDI)

I Operation I

Tech

I

strong MOS t r a n s l i n e ~ r ~ l 5 1I I-switch/I-mirror [16] I

I I

4.2 1.2

-

I

0.5

-

1

I

-

1

-

I

53

-

80

2.5 - 3 I 3.3

I I

strong strong

I I

10 10

TABLE I The performance of t h e OpA.mp with 2pm and 0 S p m process-model (Rr.= 2 . 5 k n , C =20pF, ~ VDD -Vss=3V) x

,

lo-'

[

performance parameter

I

t

Slew rate I

i

OpAmp(2pm)

I

OpAmp(0.5pm)

]

. . . . , .. .

i

23.6

90

CMRR @, 1kHz 43

1

vills

- 58 dB

Positive PSRR I -0.12

-0.i5

-0:1

-0.05

Fig. 4. Slew-currents,

0

0.06

vhw

h l , In2r

0.1

0.15

0.2

I P l , Ip2, of the input stage

Iout2

Ioutl

o--

c

I1

I-

180

-

180

-

iCC'

Vbl

Icbias

[I

,,

1-

cc2

C Vb2

-I

4 C . I-

Ioutla 0-

I Iout2a

11

ir

c

I

-01.5

-1

-0.6

0

Vcm 0

0.5

1

J

1.5

Fig. 6. Common Mode Rejection Ratio of the rail-to-rail class-AB input/output OpAmp

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