node for virtually unlimited Height. (MESH) Capacitor Aiming at sub 70nm DRAMs. *Dae-Hwan Kim, J.Y. Kim, M. Huh, Y.S. Hwang, J.M. Park,. H.S. Kim, W.T. ...
A Mechanically Enhanced Storage node for virtually unlimited Height (MESH) Capacitor Aiming at sub 70nm DRAMs *Dae-Hwan Kim, J.Y. Kim, M. Huh, Y.S. Hwang, J.M. Park, H.S. Kim, W.T. Choi, G.Y. Jin, Y.G. Park and Kinam Kim Advanced Technology Development Team, Semiconductor R&D Div. , Samsung Electronics Co
Contents Introduction : Background - Capacitor evolution - Problems
Key technologies of MESH capacitor - Define - Process scheme - Key processes
Characteristics - Electrical characterization, TEM - Reliability
Conclusions
Introduction The evolution of DRAM capacitor MIS (TIS)
MIM (TIT)
POLY-Si
SiGe or W
TiN DIELECTRICS POLY-Si
TiN DIELECTRICS TiN
SIS POLY-Si DIELECTRICS POLY-Si
0.23 μm NO, SIS S-STACK
1.5-2.0 μm
1 μm
1 μm
0.18 μm NO, SIS DHOCS
0.18-0.1 μm NO, ALO, SIS ALO MIS S-OCS
1.7 μm
0.09 μm AHO MIS RSOCS
< 0.08 μm
Introduction How to obtain high capacitance? Why 30fF/cell ? - Data retention time - signal margin for S/A operation How to obtain sufficient cell cap.? - New high-k materials : TIT - area increase : HSG, tall cylinder 50 Teq 25Å Teq 23Å Teq 20Å Teq 23Å, HSG 20%
45
20 23
35 30
25
25
2.5 μm @ TEQ 23Å
15 10 14
16
18
20
3.2 μm
40
40
20
Teq=23Å Teq=20Å
45
22
24
SN Height (kÅ)
26
28
30
SN Height (kÅ)
Cell Capacitance (fF/cell)
50
35
2.5 μm
30 25
2.7 μm
20
2.1 μm
15 10 90
80
70
Design Rule (nm)
Cylinder height for 30fF/cell
60
Introduction Problems Leaning : a bending of bottom electrode Factors : thermal stress, surface tension, aspect ratio Leaning begins to appear severely at height of 1.5μm @80nm tech.
Contents Introduction : Background - Capacitor evolution - Problems
Key technologies of MESH capacitor - Define - Process scheme - Key processes
Characteristics - Electrical characterization, TEM - Reliability
Conclusions
Key technologies Robust OCS : Forming supporter
Supporter Supporter
*LERI *J.M. Park et al., in Symp. on VLSI Tech., p. 34 (2004)
MESH
Key technologies Define What is MESH capacitor? 1. Mechanically Enhanced Storage node for virtually unlimited Height 2. Each SN is linked by meshes made of Si3N4 which prevent touching among the nodes
Key technologies Process flow (1) Play a role of a ‘Wet stopper’
MESH Si3N4
(a) PR patterning
(b) openings after hole etch
(c) deposition of (d) partial wet strip first electrode after node separation
Key technologies A?
Process flow (2)
A-A
B-B
B?
c
Definition of B direction (A-A & B-B)
‘c/2 < t < d/2’ A-A
B-B
A-A
d
A
B-B
t
MESH Si3N4 opens
(e) deposition of MESH spacer
MESH Si3N4 remains
(f) supporter dry etch
(g) wet lift–off of sacrificial oxide and MESH spacer
Key technologies Process flow (SEM) Poly Si 1st electrode Exposed MESH Si3N4
MESH SPACER
A B
MESH supporter etch
Partial wet strip Spacer deposition Remained MESH Si3N4 Overlap (final)
Overlap (before)
Spacer etch
MESH Supporter
HSG
Poly Si
MESH Supporter (Ring + Beam type) Poly Si
After full lift-off : Top view and slanted View
Vertical view
Key technologies Typical dimension of MESH supporter 55 a
10 b
35nm
10nm 55nm
35
c
Good Example of nano-patterning technology a
Key technologies Integration issue (1) Non-uniform mesh supporter formation
edge
center
Key technologies Integration issue (2) Wet chemical penetration
Inner hole filling ability of masking oxide is important
Wet penetration
TEM image
Thinning of SN bottom
Key technologies ALD spacer Masking oxide : ALD SiO2 Outer
Poly Si Masking oxide
Inner
Cutting direction MESH Si3N4
TEM images of MESH spacer showing good step-coverage
CENTER
EDGE
Key technologies Comparison of LERI and MESH MESH
LERI
Lithography add?
No
No
Supporter
Silicon nitride / other
Silicon nitride
Key concept
Using a masking oxide after partial wet strip
Using wet enlargement after partial etch
Node separation
Etch back / CMP
CMP preferred
Hole etch mask
PR
Hard mask (Poly-Si)
Supporter position
Below the top SN
Top of the SN
Process controllability
Very easy
Moderate
Key technologies Distinctive process (D80 512M DDR DRAM) a
c
RCAT
MESH b
TSC
Contents Introduction : Background - Capacitor evolution - Problems
Key technologies of MESH capacitor - Define - Process scheme - Key processes
Characteristics - Electrical characterization, TEM - Reliability
Conclusions
Characteristics AHO step coverage Bottom
Top TiN HfO2 Al2O3 PN Poly-Si
MESH supporter
MESH Si3N4
Poly-Si Poly-Si
HfO2
MESH Si3N4
TOP(%)
Al2O3 TiN
BOTTOM(%)
PN
AlO
HfO
TiN
PN AlO
100
100
100
100
92
93
MESH WING(%)
HfO
TiN
AlO
HfO
TiN
89
83
93
90
80
Characteristics
1E-6 1E-7 1E-8 1E-9 1E-10 1E-11 1E-12 1E-13 1E-14 1E-15 1E-16 1E-17 1E-18 1E-19 1E-20
40
Conventional OCS
30
Fail Bit (ea)
Lekage Current (A/Cell)
Leakage current, Vp behavior
MESH Cap. Normal OCS -5
-4
-3
-2
-1
0
1
2
3
20
0.3V UP MESH
10
0
4
5
Cell Plate Volatge (V)
Leakage current characteristics
0.3
0.6
0.9
1.2
1.5
1.8
2.1
Aplied Voltage (V)
Vp take off characteristics
Characteristics Cell capacitance, data retention time 105
Distribution (%)
80
MESH
60 40 20
Cumulative Bit Failure
Conventional OCS
100
104
Conventional OCS MESH
103
102
101
MESH with HSG
0
10 MESH with HSG 30 35 40 0
5
10
15
20
25
Cell Capacitance (fF/cell)
The cell capacitance distributions
Normalized Data Retention Time [a.u.]
The comparison of retention time
Characteristics Full integration yield
100
MESH
OCS (16k) 8 7
60
6
Normalized Yield
Distribution (%)
80
40 20
5
7 times
4 3 2 1
0
0
OCS (16k)
0
100
200
300
400
MESH (25k)
500
Two Bit Failure (ea)
TYPICAL BIT FAIL MAP
2-BIT FAIL DISTRIBUTION
600
Contents Introduction : Background - Capacitor evolution - Problems
Key technologies of MESH capacitor - Define - Process scheme - Key processes
Characteristics - Electrical characterization, TEM - Reliability
Conclusions
Conclusions Distinctive features of MESH capacitor
Lean-free High retention time High Capacitance Enlarged process margin
MESH Capacito r
Nanopatterning
Small dimension
Compatibility
Conclusions Fully reliable lean-free MESH Capacitor has been successfully developed on 80nm technology 512Mb DRAMs We expect that our success in capacitors with increased height will give great influence on the future DRAM technology. We think that the success of MESH supporter showing extremely small dimension is an amazing result in the area of nano-patterning.
