A Nonvolatile Programmable Solid-Electrolyte ... - Semantic Scholar

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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 1, JANUARY 2005

A Nonvolatile Programmable Solid-Electrolyte Nanometer Switch Shunichi Kaeriyama, Member, IEEE, Toshitsugu Sakamoto, Hiroshi Sunamura, Masayuki Mizuno, Member, IEEE, Hisao Kawaura, Tsuyoshi Hasegawa, Kazuya Terabe, Tomonobu Nakayama, and Masakazu Aono

Abstract—In this paper, a reconfigurable LSI employing a nonvolatile nanometer-scale switch, NanoBridge, is proposed, and its basic operations are demonstrated. The switch, composed of solid -nm contact diameter and electrolyte copper sulfide, has a - on-resistance. Because of its small size, it can be used to create extremely dense field-programmable logic arrays. A 4 4 crossbar switch and a 2-input look-up-table circuit are fabricated with 0.18- m CMOS technology, and operational tests with them have confirmed the switch’s potential for use in programmable logic arrays. A 1-kb nonvolatile memory is also presented, and its potential for use as a low-voltage memory device is demonstrated.

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Index Terms—Crossbar switch, FPGA, nonvolatile memory, reconfigurable logic, solid electrolyte switch.

INTRODUCTION

Fig. 1.

D

EMAND is increasing for reconfigurable LSIs, which enable a designer to change a circuit locally and avoid the need for any refabrication. Conventional reconfigurable LSIs, however, such as field programmable gate arrays (FPGAs) as illustrated in Fig. 1, are more expensive and slower in operation than cell-based ICs. This is because their programmable switch circuits, which are used to reconfigure LSI circuits, and which are composed of a pass transistor combined with either an SRAM-cell or a flip-flop circuit, have a large area (100 F –200 F , where F is the minimum feature size) and a high on-resistance (1 k –2 k ). Furthermore, conventional FPGAs have to use coarse-grain logic cells because of their large switch area. The coarse-grain logic cell wastefully occupies a large area even if only a primitive logic function is assigned to the cell [1]. Therefore, it decreases logic cell utilization efficiency, resulting in larger chip area, and increases the length of wires between logic cells, resulting in larger parasitic capacitance on wires. The large area requirement means higher fabrication costs, and the high on-resistance and the large parasitic capacitance mean slower operating speeds. Manuscript received April 13, 2004; revised May 28, 2004. This work was supported in part by Solution Oriented Research for Science and Technology of the Japan Science and Technology Agency (JST). S. Kaeriyama, H. Sunamura, and M. Mizuno are with the System Devices Research Laboratories, NEC Corporation, Sagamihara, Kanagawa 229-1198, Japan (e-mail: [email protected]). T. Sakamoto and H. Kawaura are with the Fundamental and Environmental Research Laboratories, NEC Corporation, Tsukuba, Ibaraki 305-8501, Japan, and are also with the Japan Science and Technology Agency (JST), Kawaguchishi, Saitama 332-0012 Japan. T. Hasegawa, K. Terabe, T. Nakayama, and M. Aono are with the Nanomaterials Laboratory, National Institute for Materials Science (NIMS), Tsukuba, Ibaraki 305-0003, Japan, and are also with the Japan Science and Technology Agency (JST), Kawaguchi-shi, Saitama 332-0012 Japan. Digital Object Identifier 10.1109/JSSC.2004.837244

Conventional reconfigurable LSI.

Half the chip area of an FPGA is generally occupied by a sea of SRAM-based or flip-flop-based switch circuits, and maximum operating speed is mainly determined by the RC delay of the interconnection with the switch circuit, rather than by the gate delay. This means that the switch circuit will be the key element in trying to reduce chip costs and to overcome the speed limitations in reconfigurable LSIs. One possible candidate for solving this problem is our newly developed NanoBridge [2]. It uses the switching effect of a nanoscale metal bridge, in which the stimulation of electrochemical reaction in a solid electrolyte results in the stretching or shrinking of a metallic bridge, thereby creating or dissolving an electrically conductive channel. The NanoBridge can be located on the silicon substrate on which transistors have been formed. Since it can be formed within the area of a via hole between two metal layers, the area required for its arrangement at the crosspoint of two wires is only 4 F . Further, the potential area savings for this device are actually even greater because multiple NanoBridges can be stacked one upon another. Moreover, the conductive channel formed by the metal bridge makes it possible for the on-resistance to be reduced to 50 . The compactness of the NanoBridge reconfiguration switch not only helps to reduce chip area requirements, it also allows the coarse-grain logic cells to be replaced with fine-grain logic cells, which increase logic cell utilization efficiency (i.e., usable logic cells are fully utilized) and decrease the RC delay of interconnections between logic cells. Fig. 2 shows logic cell versus unit logic cell density area. Higher logic cell density indicates that there are more logic gates in an area, and lower density means that there are less logic gates in the area and the area is almost occupied by switches. The slash-designated area on the right is for a

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KAERIYAMA et al.: A NONVOLATILE PROGRAMMABLE SOLID ELECTROLYTE NANOMETER SWITCH

Fig. 2.

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Logic cell density.

conventional SRAM-based FPGA. We assumed each logic cell to be connected to from 50 to 200 switches, and that each switch would have an area of 120 F . For logic cell density to be high, each logic cell has to have high functionality and have coarse granularity. If fine-grain logic cells such as D-flip-flops (DFFs), multiplexers (MUXs), or primitive gates were used as logic cells in a conventional SRAM-based FPGA, logic cell density would drop to a few percent. This means that almost the entire chip would be occupied by SRAM-based switches. On the other hand, coarse-grain logic cell has the disadvantage of poor logic cell utilization efficiency and wastes area [1]. In order to avoid the need for coarse-grain logic cells presented by conventional SRAM-based FPGAs, we have replaced SRAM-based switches with NanoBridges. The results may be seen in the slash-designated area on the left in Fig. 2. Here, even when fine-grain logic cells such as DFFs, MUXs, or primitive gates are used as logic cells for better logic cell utilization efficiency, logic cell density can still be maintained at 50%. The use of fine-grain logic cells also improves signal delay between logic cells because it reduces the wire length between them. Moreover, using low-resistance interconnection switches with short wires is especially effective in reducing this delay further. Fig. 3 shows estimated delay reduction with the use of the NanoBridge. Although the delay reduction with a 1-mm wire is from 5% to 30%, the reduction with a 100- m wire increases to about 40%. This means that the delay of a local interconnection whose wire length is less than 100 m will be halved by replacing a conventional switch with a NanoBridge. The NanoBridge can also be utilized as a nonvolatile memory. While nonvolatile memories such as flash memories are particularly important building blocks in ASICs, it is difficult for them to operate with low supply voltages. Since the NanoBridge can operate with sub-1-V supply voltages, it is a promising candidate for future nonvolatile memory use. In this paper, to demonstrate the potential of reconfigurable LSIs that employ NanoBridges, we present a crossbar switch and a look-up-table circuit, the basic components of FPGAs, into which NanoBridges have been incorporated. Further, we also present a low-voltage nonvolatile memory chip that utilizes NanoBridges.

Fig. 3.

Delay reduction with NanoBridge.

I. SOLID-ELECTROLYTE NANOMETER SWITCH Scanning tunneling microscope (STM) observations have recently revealed a conductance switching phenomenon resulting the creation or dissolution of nanoscale metallic wire on the surface of Ag S/Ag film, an Ag-ionic/electronic mixed conductor [3], [4]. The Pt tip of the STM was set at a distance of a few nanometers from the Ag S/Ag film. When a negative voltage is applied to the tip, Ag ions on the surface are neutralized, and a nanometer scale metal bridge is formed in the air gap between the Pt tip and the Ag S film. When a positive voltage is applied, the bridge dissolves into the film and conductance decreases. A similar switching effect without the air gap has also been demonstrated [5]. This structure is more suitable for the LSI process because it is difficult to fabricate the air gap. Instead of the air gap, this switch employs Ag/AgGeSe film, where AgGeSe is a solid electrolyte material. Ag is ionized when it emits electrons. Ag ions are mobile inside the solid electrolyte and are neutralized when they are exposed to electrons. When a positive voltage is applied to the Ag film, silver conductive bridges are formed inside the AgGeSe film. Unfortunately, however, silver is unsuitable for the LSI process because it is too easily oxidized. Similar switching of the conductance of the ionic/electronic mixed conductor without an air gap has been demonstrated [6], [7], and here silver has been replaced by copper, which is much more compatible with the current interconnect technology. Fig. 4 shows the NanoBridge in cross-section. It is composed of Cu S sandwiched between two metals (Cu and Ti). Because Cu ions are mobile in Cu S, electric field can be used to move them. When a negative voltage is applied to the top electrode, Cu ions in the Cu S are electrochemically neutralized by the electrons coming from that electrode, and Cu is deposited on it in the following reaction: Cu

Cu

(1)

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Fig. 4. Cross-section of NanoBridge.

The deposited Cu forms a conductive nanometer scale bridge between the two electrodes, changing the conductance to an on-state. Since the bridge is extremely thin immediately after changing to the on-state, its on-resistance will be hundreds of ohms, but with continued application of the negative voltage, the bridge thickens, and on-resistance can be reduced to 50 . Similarly, the bridge can be ionized and dissolved by applying a positive voltage to the top electrode, resulting in an off-state. This reaction can be expressed as Cu

Cu

Fig. 5. Experiment with a liquid electrolyte. (a) SEM micrograph of electrodes in initial condition. (b) On-state. (c) I–V characteristics. (d) Off-state.

(2)

To confirm the operational principle of the NanoBridge, we performed an electroplating experiment with a liquid electrolyte. A platinum electrode and a copper electrode were formed on an SiO /Si substrate, separated by a small gap m), as shown in Fig. 5(a). These electrodes were then ( dipped into a liquid electrolyte consisting of a diluted solution of copper sulfate CuSO and sulfuric acid. When a negative voltage is applied to the platinum electrode, copper is electroplated on that electrode by the following electrochemical reaction: Cu

Cu

(3) Fig. 6.

As a result of the electroplating, a copper bridge forms between two electrodes [see Fig. 5(b)], making possible the current flow shown in Fig. 5(c). Conversely, by biasing a positive voltage, it is possible to dissolve the deposited copper into the electrolyte, resulting in the condition shown in Fig. 5(d), and making current flow impossible. The platinum and copper electrodes here correspond to the top and bottom electrodes of the NanoBridge, and the experiment indicates that the change in current flow through the NanoBridge originates in the deposition or dissolution of a copper bridge formed by an electrochemical reaction. Fig. 6 shows measured current–voltage characteristics for the NanoBridge at room temperature. The switch is turned on by applying a negative voltage to the top electrode, and the onresistance becomes roughly 50 . The switch is turned off by applying a positive voltage to the top electrode. This switching operation is repeatable more than times, as shown in Fig. 7.

Current–voltage characteristics.

After – times, the switching time becomes gradually longer, and then the switch remains in either an on-state or off-state. In these endurance tests, the bottom-electrodewas measured under a biasing to-top-electrode current voltage of V. Fig. 8 shows retention characteristics of a NanoBridge at room temperature. After programming to be on-state by –V and 1-ms pulse, we applied a constant positive a to the top electrode and measured duration in voltage V, the state changes to off-state the on-state. For V, the duration decreases to 2.5 s. after 970 s. For The duration decreases exponentially as increases (shown in the inset of Fig. 8). Extrapolating from these results, the retention time under zero bias conditions is estimated to be three months. In actual measurements, retention of more than one month has been confirmed at room temperature. At higher


Fig. 7.

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Cycling endurance.

Fig. 9.

Crossbar switch.

Fig. 8. Retention characteristics.

temperature, it is theoretically predicted that the retention decreases with temperature. The retention can be improved by replacing the solid-electrolyte material with that having lower ion mobility. The off-state is more stable than the on-state, and retention of the off-state is longer than that of the on-state. The steps seen in the current drops in the figure would appear to exist because the bridge itself consists of a number of bridge elements, strands, which dissolve one by one. II. APPLICATION TO RECONFIGURABLE LSIs The compact and low-resistance switch NanoBridge is ideal for reconfigurable LSIs. Let us consider a 4 4 crossbar switch and a 2-input look-up table, described below. A. Crossbar Switch Fig. 9 shows the schematic of 4 4 crossbar switch composed of NanoBridges. It could be programmed by applying in Fig. 9, voltages to its horizontal and vertical lines. Switch for example, could be programmed to be on-state by applying to , grounding , and applying to the other is a programming voltage for the NanoBridge lines, where and is greater than the threshold voltage of the NanoBridge , and is less than . Since the voltage difference between the two terminals of would become , which would be turned on. With respect to all the exceeds other switches, since the voltage difference for them would be or zero, both of which are less than , their states would not change.

Fig. 10.

Crossbar switch with transistors.

That, at least, is how the crossbar switch is designed to operate. Actual fabrication technology is not yet sufficiently values for all sophisticated to ensure a consistency in values fabricated NanoBridges. That is, variation among for individual devices is too high to ensure proper programming. To prevent inaccurate programming, a pass transistor is connected to each NanoBridge, as shown in Fig. 10. Programming is performed by rows. For example, the first row on and turn , and might be programmed to turn off. To do this: 1) would be applied to , and ; 2) A supply voltage would be applied to WE; , and would be grounded; and 4) 3) would be grounded via its turned-on transistor (used here as a becoming forward biased, resistor). This would result in being an on-state, and an increase in the voltage at . This , and becoming reverse increase would result in biased and being an off-state. During actual operations, WE is

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Fig. 12.

Measured waveforms for crossbar switch.

Fig. 13.

Look-up-table-based configurable logic cell.

Fig. 11. (a) Micrograph of crossbar switch. (b) Cross section of switch. (c) SEM micrograph of NanoBridge.

grounded, and is applied to , and . Although this use of a pass transistor makes the crossbar switch less compact (25 F /switch) and increases its resistance ( k ), the NanoBridge still represents a significant advance over conventional designs in area requirements compared with F /switch). SRAM-based switch ( Fig. 11(a) is a top-view micrograph of the crossbar switch. A NanoBridge is located at each crosspoint of the vertical and horizontal lines. A schematic cross section of a crosspoint is shown in Fig. 11(b). Each crosspoint is composed of a transistor and a NanoBridge. The transistors have been fabricated with 0.18- m standard CMOS technology. Fig. 11(c) is a SEM micrograph of the NanoBridge. Since the maximum process temperature in NanoBridge fabrication is 150 C, the fabrication process does not affect the transistors or the interconnections. Fig. 12 shows measured waveforms for the fabricated crossbar switch. In these experiments, actual operations were limited to 2–8 ms. Here, the switches and shown in Fig. 10 have been programmed to be on-state, and the other switches to be off-state. Results show that the input signals , and are successfully transferred to , and , via , and , respectively. Programming operations were also confirmed for a variety of other configurations. Unfortunately, however, transistor requirements necessitated an operation voltage of 1.8 V higher than the threshold voltage of the NanoBridge. This resulted in unintended changes in switch states during actual operations, and the best solution would seem to be to try to raise the threshold voltage by using a different solid electrolyte material having lower ion mobility. The measurable maximum operating frequency here was limited by the capacity of the I/O circuits and our measurement

systems. The limited frequency bandwidth of our wafer probe had a particularly strong influence, as the ringing waveforms show. B. Configurable Logic Cell We fabricated a 2-input look-up-table-based configurable logic cell circuit. The circuit diagram is shown in Fig. 13. Programming is conducted using a table establishing correspondences between the two input values (A, B) and an output value determinant D. This D is used in programming to ensure that a desired output is obtained for given combinations of A and B. Programming involves setting A, B, and D value and to WE, which will result in a single NanoBridge applying being selected and either forward or reverse biased (i.e., programming to either on-state or off-state). Table I shows an example of the relationship between input values and an output value when the look-up-table is configured as an XOR gate. During actual logic operations, WE is grounded, and input


EXAMPLE

OF

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TABLE I RELATIONSHIP BETWEEN INPUT VALUES AND AN OUTPUT VALUE

Fig. 15.

Illustration of over-programming.

Fig. 16. Switching time distributions.

Fig. 14.

Measured waveforms for look-up-table.

logic values are applied to A and B, and then the corresponding output logic value Y is obtained by sensing an switching state of a NanoBridge. Fig. 14 shows measured waveforms for the two-input look-up-table circuit. The upper two waveforms are for input signals A and B, and the other waveforms are for output signal Y under AND, OR, NAND, NOR, and XOR configurations, respectively. The waveforms show that proper reconfigurations with respect to the look-up table were achieved. III. NONVOLATILE MEMORY A nonvolatile memory fabricated with the NanoBridge technology might be advantageously embedded in NanoBridgebased reconfigurable LSIs. The competitive potential of this memory lies in its low-voltage operations and scalability. NanoBridge-based memory, however, has two disadvantages: long switching time and short cycling endurance, both originating from an over-programming problem, peculiar to

the NanoBridge. Fig. 15 contrasts over-programmed (i.e., over-dissolved and over-created) NanoBridges with properly programmed NanoBridges. This is due to continued voltage biasing even after a bridge has turned on or off, resulting in excessive thickening or excessive dissolution of a bridge. When over-programming has occurred either subsequent programming operations take a longer time, or switching simply fails. Fig. 16 shows the distribution of switching times for when a NanoBridge is repeatedly turned on/off with a fixed biasing time of 10 ms. The broadness of the distribution, ranging from 0.1 to 10 ms, is due to over-programming. Over-programming also decreases cycling endurance because it puts superfluous stress on switches. Specifically, when the switch is programmed to be on-state, neutralization of Cu ions results in copper deposition on the top electrode, while copper in the bottom electrode migrates into the solid electrolyte as copper in the bottom electrode is oxidized and ionized. Over-programming causes superfluous migration of copper in the bottom electrode, causing crumbling and shortening the cycling endurance of the NanoBridge. To alleviate over-programming, biasing times need to be controlled by monitoring either the resistance or the current of the switch. Fig. 17 shows the circuit used in programming operations. By comparing voltage drop on a memory cell with that on a replica cell, the resistance of the NanoBridge can be monitored during programming. To turn the NanoBridge on, a programming voltage is applied to a bit line and a plate line is grounded. When the resistance of a selected NanoBridge becomes lower , the voltage on the bit line than that of the replica resistor falls lower than that on the replica cell, a comparator will output a signal indicating that programming has been completed. To turn the NanoBridge off, a programming voltage is applied to a plate line and a bit line is grounded. When the resistance of a selected NanoBridge becomes higher than that of the replica , the voltage on the bit line falls lower than that resistor on the replica cell, the comparator outputs a signal indicating

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Fig. 17.

Programming circuit for memory.

Fig. 18.

Micrograph of 1 kb memory.

that the programming has been completed. A BUSY signal, such as that as shown in Fig. 17 indicates that a circuit is currently performing the programming operations. Fig. 18 is a chip micrograph. The peripheral circuits, including driver circuit and address decoders, were fabricated with 0.25- m CMOS technology. After the CMOS circuit was fabricated, NanoBridge devices were formed on the top metal layer. Two NanoBridge terminals are connected to, respectively, an access transistor and a plate line. Fig. 19 shows waveforms for programming operations. A selected NanoBridge is repeatedly programmed to be on-state and off-state. The BUSY signal indicates that programming is being conducted. The selected cell is alternately programmed to be on-state and off-state with a programming voltage of 1.1 V. The fall of a BUSY signal indicates that the programming operation has been completed. Its signal width corresponds to the switching time of the solid electrolyte switch, which ranges from 5 to 32 s. This switching time has a narrower distribution than that shown in Fig. 16, which was programmed with a constant pulse width.

Fig. 19.

Measured waveforms for memory cell programming operation.

IV. CONCLUSION We have presented here a solid-electrolyte nanometer switch, called NanoBridge, suitable for reconfigurable LSIs because of its compact size and low on-resistance. It also has a potential capability for use as a low-voltage nonvolatile memory. These characteristics might help to reduce chip costs and raise operating speeds in reconfigurable LSIs, as well as to improve scalability in the operation voltages of nonvolatile memories. To demonstrate its application to a reconfigurable LSI, we have fabricated a crossbar switch and a look-up table, the main components of reconfigurable LSIs, for use with a NanoBridge design, and we have confirmed that they operate properly. We have also demonstrated the use of a NanoBridge as a lowvoltage nonvolatile memory device. Although retention times and switching times still need to be improved, the potential appears good, mainly because of its compact size (4 F ) and low operation voltage (less than 1 V). Since it will be more difficult for current flash memories to lower the operating voltages and


to reduce cell sizes further, NanoBridge appears to have particular potential value.

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Hiroshi Sunamura was born in Kanagawa, Japan. He received M.S. and Ph.D. degrees in applied physics engineering from the University of Tokyo, Tokyo, Japan, in 1994 and 1997, respectively. He joined the Fundamental Research Laboratories, NEC Corporation, in 1997, where he has been engaged in development of nonvolatile memories and solid-electrolyte nanometer switches. He is currently an Assistant Manager at the System Devices Research Laboratories, NEC Corporation. Dr. Sunamura is a member of the Japan Society of

ACKNOWLEDGMENT The authors would like to thank H. Watanabe, M. Fukuma, J. Sone, S. Ohya, T. Baba, M. Yamashina, and N. Nishi for their important advice and support throughout this work. Applied Physics.

REFERENCES [1] J. Rose, A. E. Gamal, and A. Sangiovanni-Vincetelli, “Architecture of field-programmable gate arrays,” Proc. IEEE, vol. 81, no. 7, pp. 1013–1029, Jul. 1993. [2] T. Sakamoto, S. Kaeriyama, H. Sunamura, M. Mizuno, H. Kawaura, T. Hasegawa, K. Terabe, T. Nakayama, and M. Aono, “A nonvolatile programmable solid electrolyte nanometer switch,” in IEEE Int. SolidState Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2004, pp. 290–291. [3] T. Hasegawa, K. Terabe, T. Nakayama, and M. Aono, “Quantum point contact switch using solid electrochemical reaction,” in Ext. Abs. Int. Conf. Solid State Devices and Materials (SSDM 2001), Sep. 2001, p. 564. [4] K. Terabe, T. Nakayama, T. Hasegawa, and M. Aono, “Ionic/electronic mixed conductor tip of a scanning tunneling microscope as a metal atom source for nanostructuring,” Appl. Phys. Lett., vol. 80, pp. 4009–4011, May 2002. [5] M. N. Kozicki, M. Mitkova, and J. Zhu, “Can solid state electrochemistry eliminate the memory scaling quandary?,” in Tech. Dig. IEEE Si Nanoelectronics Workshop, Jun. 2002. [6] T. Sakamoto, H. Sunamura, H. Kawaura, T. Hasegawa, T. Nakayama, and M. Aono, “Reproducible current switching in copper sulfide film,” in Ext. Abs. Int. Conf. Solid State Device and Materials (SSDM2002), Sep. 2002, pp. 264–265. [7] T. Sakamoto, H. Sunamura, H. Kawaura, T. Hasegawa, T. Nakayama, and M. Aono, “Nanometer-scale switches using copper sulfide,” Appl. Phys. Lett., vol. 82, pp. 3032–3034, May 2003.

Shunichi Kaeriyama (M’02) received the B.E. degree in information engineering and M.S. degree in information science from Tohoku University, Sendai, Japan, in 1999 and 2001, respectively. In 2001, he joined the Silicon Systems Research Laboratories, NEC Corporation, Kanagawa, Japan, where he has been engaged in research and development of high-speed serial links.

Toshitsugu Sakamoto was born in Nara, Japan. He received the M.S.E.E. and Ph.D. degrees from Osaka University, Osaka, Japan in 1991 and 1996, respectively. In 1991, he joined the Fundamental Research Laboratories of NEC Corporation. From 1999 to 2000 he was also a visiting researcher in California Institute of Technology, Pasadena, CA. He has been doing research in the areas of such nanometer-scale devices as hot electron transistors, single electron devices, and solid-electrolyte devices. He is currently a Principal Researcher of the Fundamental and Environmental Research Laboratories, NEC Corporation. Dr. Sakamoto is a member of the Japan Society of Applied Physics.

Masayuki Mizuno (M’95) received the B.S., M.S., and Dr.Eng. degrees in electronic engineering from Osaka University, Osaka, Japan, in 1991, 1993, and 2000, respectively. In 1993, he joined the System ULSI Research Laboratory, Microelectronics Research Laboratories, NEC Corporation, Kanagawa, Japan, where he has been engaged in the research and development of low-power single-chip MPEG2 video encoder LSIs, low-power PLLs, and high-speed clock distribution networks. While on leave from 1999 to 2000, he studied interconnection network for chip multiprocessors at Stanford University, Stanford, CA, as a Visiting Scholar. His research interests are low-power techniques for high-speed CMOS LSIs, high-speed serial links, and high-speed clocking. He is currently a Principal Researcher of the System Devices Research Laboratories, NEC Corporation. Dr. Mizuno is a member of the Institute of Electronics, Information, and Communication Engineers of Japan.

Hisao Kawaura was born in Saitama, Japan, on March 8, 1962. He received the M.S. degree in physics from Kyoto University, Kyoto, Japan, in 1987 and also received the Ph.D. degree in engineering from the Tokyo Institute of Technology, Tokyo, Japan, in 2003. He joined NEC Corporation in 1987 and was engaged in the development of charge coupled devices and custom LSIs. In 1993, he moved to the Fundamental Research Laboratories and worked on source-drain tunneling effects in nanometer-scaled MOSFETs. He has been interested in nano-structured biochips and solid electrolyte switching devices. He is currently a Principal Researcher at the Fundamental and Environmental Research Laboratories, NEC Corporation. Dr. Kawaura is a member of the Japan Society of Applied Physics.

Tsuyoshi Hasegawa received the B.S. degree in physics in 1985, the M.S. degree in materials science in 1987, and the Ph.D. degree in 1996 from the Tokyo Institute of Technology, Japan. He worked for Hitachi at the Central Research Laboratory from 1987 to 1999. He developed new types of instruments, such as the nano-prober, which enables a direct measurement of a single transistor in a memory cell. He joined the RIKEN (the Institute of Physical and Chemical Research) in 1999 and the National Institute for Materials Science (NIMS) in 2002 as a Senior Research Scientist. His research has been focused on developing a conceptually new nano-devices based on atomic mechanics. Now he leads the research of the new devices as an associate director of the Atomic Electronics group in NIMS. Dr. Hasegawa received the JSPE Technology Development Award in 1991 from the Japan Society for Precision Engineering (JSPE).

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Kazuya Terabe received the B.S. degree in 1986, the M.S. degree in 1988, and the D.R. degree in 1992 in material science and engineering from Nagoya Institute of Technology. In 1992, he was a research associate with Nagoya University. In 1996, he was with the institute of physical and chemical research (RIKEN) working on creation of nano-ionics devices, such as an atomic switch made of Ag S crystal, based on solid state electrochemistry by using scanning tunneling microscopy. Since 2001, he has been with National Institute for Materials Science (NIMS), working on novel functional nano-devices made of solid electrolyte and ferroelectric materials.

Tomonobu Nakayama received the B.S. degree in physics in 1986 and the M.S. degree in materials science in 1988 from the Tokyo Institute of Technology (TIT), and the Ph.D. in physics in 1999 from the University of Tokyo, Japan. He joined the Mitsui Mining and Smelting Co. Ltd in 1988 and became a member of the Aono Atomcraft Project supported by Japan Science and Technology Agency in 1989. He was a Researcher at the Institute of Physical and Chemical Research (RIKEN) from 1991 to 2002, and a visiting Professor at Taiwan National Chiao Tung University from 2001 to 2002. He has been a visiting Lecturer of TIT since 2002. Since 2002, he has been an Associate Director of the Electro-Nanocharacterization Group in Nanomaterials Laboratories of the National Institute for Materials Science, and also an Associate Professor at the University of Tsukuba from 2004. Dr. Nakayama received the Best Research Prize in Surface Science in 2001 from the Kao Foundation for Arts and Sciences.


Masakazu Aono received the B.S. degree in metallurgy in 1967 from the Waseda University, the M.S. degree in metallurgy in 1969, and the Ph.D. degree in 1972 from the University of Tokyo, Japan. He joined the National Institute for Research in Inorganic Materials in 1972. He was a Chief Scientist of RIKEN from 1986 to 2002. He was a Professor of Osaka University in 1996. He conducted the Aono Atomcraft Project as an Exploratory Research for the Advanced Technology project of the Japan Science and Technology Agency (JST) from 1989 to 1994. Core Research for Evolutional Science and Technology and Solution Oriented Research on Science and Technology projects (JST) were also conducted by him. He started the Nanoscale Quantum Conductor Array Project as an International Cooperative Research Project (JST) in 2003. He is a Director General of the Nanomaterials Laboratories of the National Institute for Materials Science (NIMS) and a Professor of Osaka University, Japan, since 2002. Dr. Aono received the Science and Technology Ministry Prize in 1983, and became a Fellow of the American Vacuum Society (AVS) in 2003.