Abstract-High frequency clock rate is a key issue in today's. VLSI. To improve performance on-chip, clock multipliers are used. But it is a difficult task to design ...
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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 31, NO. 7, JULY 1996
A Portable Clock Multiplier Generator Using Digital CMOS Standard Cells Michel Combes, Karim Dioury, and Alain Greiner
Abstract-High frequency clock rate is a key issue in today’s VLSI. To improve performance on-chip, clock multipliers are used. But it is a difficult task to design such circuits while maintaining low cost. This paper presents a circuit fabricated to test a new method of clock frequency multiplication. This new approach uses a digital CMOS process in order to implement a fully integrated digital delay locked loop. This multiplier does not require external components. Moreover, as it is primarily intended for ASIC design, it is generated by a parameterized generator written in C which relies on a portable digital standard cell library for automatic place and route. The design based on the delay locked loop allows the clock waveform to reach its operating point faster than conventional methods. Special techniques enable high multiplication factors (between 4 and 20) without compromising the timing accuracy. With a clock multiplier of 20, in 1 pm CMOS process and a 5 V supply voltage, a 170 MHz clock signal has been obtained from a 8.5 MHz external clock with a measured jitter lower than 300 ps.
I. INTRODUCTION DVANCES in VLSI fabrication process have led to an increase in the clock frequencies of circuits. Today, frequencies of several hundred megahertz are within reach. Unfortunately, at such high frequencies, problems in the distribution of clock signals throughout an entire system are encountered. An external clock cannot be used, thus creating the need for an on-chip clock multiplier for high speed products. More and more, the overall system performance is determined by the clock network itself and clocking becomes a key issue in VLSI design. Some full custom designs of clock multipliers have already been used for high end microprocessors [l], [ 2 ] . But for ASIC’s, the time to market is critical and, consequently, the full custom approach is not possible. Several methods are possible to realize frequency multiplication: analog phase locked loop (PLL) [1]-[3], digital phase locked loop (DPLL) [4], and delay locked loop (DLL) [5], [6]. The former requires not only a very long time to lock but also external or internal analog components (resistances, capacitances, etc.) whose dependence upon the technology implies very precise adjustment. The substitution of analog components (filter, phase comparator, Manuscript received October 23, 1995; revised February 9, 1996. This work was performed at the MASI Laboratory. M. Combes was with Institut Blaise Pascal, Laboratoire MASI, Couloir 55-65, 2kme Ctage, Universitt Pierre et Marie Curie (P6) CNRS URA 818. 75252 Paris Cedex 05, France, He ia now with Texas Instruments France, 0627 1 Villeneuve Loubet Cedex, France. K. Dioury and A. Greiner are with Institut Blaise Pascal, Laboratoire MASI, Couloir 55-65, 2bme Ctage, Universiti Pierre et Marie Curie (P6) CNRS URA 818, 75252 Paris Cedex 05, France. Publisher Item Identifier S 0018-9200(96)04409-5.
VCO) by digital parts that occur in DPLL suppresses the need for external passive elements [4]. Unfortunately, the use of a digital approach creates quantification errors which decrease the system accuracy. Moreover, addition of phase error on the overall loop reaction delay causes, on the output clock, phase jumps greater than the quantification step. Regarding the clock frequency multiplication, phase tracking is not required since the input signal is not modulated, so that it is impossible to lock onto a false frequency. Consequently, a simpler approach than PLL’s can be used: the delay locked loop (DLL) is more adapted to our problem. DLL is based on the propagation of events along a series of variable delays and a mechanism controls delays to ensure that two events occur simultaneously at both ends of the delay line. In order to minimize area cost of the clock multiplier and to improve the accuracy of the clock signal, we have introduced the factorized DLL inspired from the conditioned oscillator [7].
11. THE OBJECTIVES Our aim is to prove the feasibility of a clock multiplier generator which uses a CMOS process. The approach is a digital design of the delay locked loop based on a standard cells library. The first set of objectives are linked to the intrinsic features of the clock signal. Sharp edges and a precise period are required to decrease the skew and to prevent the malfunctioning of circuits. The maximum jitter should be less than 5% of the cycle time. The duty cycle must be precisely defined, as digital circuits are usually sensitive to both rise and fall transitions. Regarding the clock frequency multiplication, the phase shift between the generated clock and the reference clock must be small and constant to achieve a synchronous data flow exchange. Other requirements are linked to the use of the clock frequency multiplier: the multiplier must provide a sufficiently high value of the maximum frequency (fmax r” 100 MHz for a 1 pm technology and 5 V supply voltage) with a large bandwidth (0 to fir,,,), and the range of adjustment must compensate any variations due to: the temperature, the power supply, and the fabrication process. The time to lock must be as short as possible (less than 100 ps). For ASIC design, it is necessary to have a parameterized generator: the user can choose the multiplication factor (between 4 and 20). Moreover, the area must not exceed l mm2 for a 1 Fm technology.
0018-9200/96$05.00 0 1996 IEEE
COMBES et al.: A PORTABLE CLOCK MULTIPLIER GENERATOR USING DIGITAL CMOS STANDARD CELLS
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111. SYSTEMOVERVIEW The scheme of the clock multiplier is represented in Fig. 1 . It is made up of five blocks: two variable delays with digital control [8], a set-reset flip-flop, a phase comparator, a frequency divider, and a delay controller which is a finite state machine. To reduce even further the output frequency, a frequency divider can be added. The delays are controlled by the phase comparator through the delay controller. The divider counts the clock cycles to realize the frequency multiplication. An independent finite state machine uses successive results of phase comparison to indicate whether or not the loop is locked. A detailed study of the clock frequency multiplier can be found in [9]. The clock frequency multiplier principle is illustrated on the time diagram on Fig. 2 . A rising transition on CKref creates, at the point labeled A, a rising edge which crosses the two delays of value I-. After a delay of 7 , the input reset of the flip-flop is activated, so that the signal A falls to a low level. After a delay of 2 x I-, the rising edge at the point J is used to set the flip-flop. These events recur during m cycles
which are counted by the divider. Then, to be activated again, the DLL needs the external signal CKref (selected by the input multiplexer). The first m - 1 clock cycles are of equal period, whereas the last cycle has a different period fixed by the rising edge of C K r e f . The principle of the delay locked loop is to find the delay necessary to equal the m cycles: at the mth cycle, the phase comparator measures the displacement between the rising edge of C K r e f and J . The delay controller adjusts the value of the delays. To assure a duty cycle of 0.5, the same value must be given to both variable delays: an extra gate must be added to the second one to offset the flip-flop propagation time. The phase shift between CKref and C K x M is due to the propagation time in the flip-flop plus the propagation time in the buffer. A. The Variable Delay The clock multiplier accuracy depends on its delay adjustment capability, independently of the input frequency or of any other factors. Indeed, the clock multiplier tuning range is determined by the delay range itself. Therefore, the delay is a critical component in the design. We need to achieve
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 31, NO. 7, JULY 1996
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a very precise variation step over a very wide range. As we resynchronize the oscillator periodically, the error is not accumulated over time. As a result, delay tuning is compatible with the use of digital control rather than a conventional charge pump. This allows the clock multiplier to operate regardless of the power supply fluctuation and any other “analog” noise sources. However, the accuracy of the clock multiplier is based upon the tunable delay step, resolution required is relatively low, and an 8 b wide command is acceptable in the delay implementation. The variable delay (Fig. 3) is digitally controlled. It is made up of two blocks: 15 fixed delays associated with an iiiterpolator (Fig. 4). The principle of the delay is to select two consecutive edges with the command SelG. and then to perform an interpolation between them. A single interpolation between the two edges A and l? (on Fig. 4) is realized by controlling the relative power of the two sets of drivers on &. For example, if the command is zero, the power of A driver is a maximum and the power of U driver is zero. When the command increases, the power of A decreases and the power of 11 simultaneously increases. The drivers A and B are realized with 16 parallel tristate gates. The SelN command sets the number of activated tristate gates. The t command 1. chooses between SebN and S e l N The digitally controlled delay has a linear characteristic (see Fig. 5 ) with a step Sr (Sr ‘v 50 ps for 1 km technology). The
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B. The Phase Comparator A very accurate delay element is feasible, but to make the best use of the 50 ps step in 1 pm technology, a sufficiently precise phase measure is essential. With a large blind window, any decision can be taken by the phase detector. The required phase comparator must support a large frequency spread. Our phase comparator (see Fig. 6) is a set-reset flip-flop. Just before the measurement, the flip-flop is in the first state on the table of the Fig. 6. If the rising edge of J arrives before the rising edge of C K r e f , Q stays at one, and conversely, if the rising edge of J arrives later than the rising edge of C K r ef , Q goes to zero. The delay controller uses the result
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COMBES et al. A PORTABLE CLOCK MULTIPLIER GENERATOR USING DIGITAL CMOS STANDARD CELLS
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the multiplication factor. This increase in area is entirely due to the controller delay, and the divider by m. Fig. 8 shows that the increase is linear with the multiplication factor. These results have been obtained after the place and route of all the clock multipliers which it is possible to generate. With two consecutive place and route of the same netlist, different areas can be obtained. This explains the fluctuations shown in Fig. 8.
C. The Delay Controller The delay controller iq a finite state machine. It is clocked by the multiplied clock. Thus, to support such high frequency, it was necessary to design a very fast dynamic D-type flipflop (Fig. 7), and the controller delay netlist has been designed with optimization of the critical paths. The divider, which counts the clock pulse, uses the same techniques, but with a T-type flip-flop. The area of' the multiplier increases with
D. The Lock Finite State Machine It is necessary-for the test (and for using the clock multiplier in a circuit-to know at each time if the loop is locked or not. To realize thi, function, we have added a finite state machine to the clock multiplier. It uses the phase comparator result to update an output signall lock which indicates the state of the loop. The lock finite state machine diagram is illustrated
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IV. THE EPSILONTECHNIQUE The variable delay is controlled by two digital signals: SelG selects the range (sig,/sig,L+l) and SelN controls the interpolator. The delay step Sr is the difference between two consecutive control codes (C and C 1).In I pm technology, this is about 50 ps. The cycle time step S t of the output clock equals two delay steps ST. Using the hypothesis that the delays are constant during one cycle of CKref it is obvious that the difference ST between the last cycle of the generated clock and the other cycles can reach m x 6 t (see Fig. 10). This error is unacceptable (2 ns for rn = 20 and a 1 pm process).
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COMBES et ul.: A PORTABLE CLOCK MULTIPLIER GENERATOR USING DIGITAL CMOS STANDARD CELLS
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have developed a generator. The clock frequency multiplier generator, C M G , has been realized with the ALLIANCE CAD system [lo]. C M G is a tool written in C and using the Genlib procedural language [ 1 11. C M G creates a gate netlist, for automatic place and route. C M G uses a classical digital standard cells library including six dedicated cells: two for the variable delay (the fixed delays and the interpolator), the set-reset flip-flop, the phase comparator, a dynamic D-type flip-flop for the finite state and a dynamic T-type flip-flop for the divider. Dynamic flip-flops are required in order to attain a frequency of 100 MHz. The only “analog” cell is the interpolator. All cells are designed in symbolic layout [I21 in order to be portable to any CMOS technology. C M G requires two parameters to generate the appropriate clock multiplier circuit: the multiplication factor m and the division factor d for the output frequency divider. With given input and output frequencies, and knowing that the oscillator can run between 50-100 MHz in 1 pm CMOS technology, d is obtained from the output frequency, and gives a required oscillator frequency fx. This frequency, together with the input frequency, gives the multiplication factor m (see Fig. 12). VI. THE POWERCONSUMPTION Nowadays, problems related to power consumption are becoming more and more important. The demand for lowpower circuits and the increase in integration density has made the power consumption a critical factor in VLSI design. An analysis of power consumption of the clock multiplier was performed with SPICE. The power consumption was calculated for a factor 20 multiplier. The interconnection and transistor capacitances were calculated for worse case. The circuit was simulated with a supply voltage of 5 V and an operating frequency of 100 MHz for an input frequency of 5 MHz. The average power measured over a period of 10 input clock cycles (200 generated clock cycles) was 135 mW, 70 mW for the oscillator and 65 mW for the finite state machines. The power consumption of the oscillator is proportional to the operating frequency. The power consumption of the finite state machines is also proportional to the operating frequency but inversely proportional to the multiplication factor. VII. THE SENSITIVITY TO SUPPLY VOLTAGE PLL’s and DLL’s are highly sensitive to supply voltage fluctuation, which affect their operation and can cause unlock. The variable delay range of our multiplier allows the compensation of all supply voltage fluctuations between 4.5 V and 5.5 V for a 5 V 1 p m CMOS technology. However, a step in the supply voltage can momentarily cause unlock. It is possible to calculate the maximum acceptable steepness in the supply voltage fluctuation. A 1 V variation in the
Fig. 13. The layout of the H i f a c t circuit.
supply voltage corresponds to a variation of 25 delay steps in the output period. To compensate for this variation m x 25 ( m is the multiplication factor) external clock cycles are required. It is therefore possible to compensate for 40 mV of supply voltage variation in m cycles of the extemal clock. We can therefore deduce the maximum acceptable steepness: AV/& = ( f i x 40 mV)/m ( f i is the input frequency). In the worst case ( m = 20 and f e = 5 MHz) AV/At equals 10 mVlfis.
VIII. CIRCUITREALIZATION A test chip H i f a c t [I31 (Fig. 13), using the ES2 1 pm and 5 V supply voltage CMOS technology was fabricated to validate this approach. It performs a multiplication by 20 with an input frequency of 5 MHz. It is divided in three blocks. Multick: The clock frequency multiplier (by 20 with a divider by two) generated by C M G . Its area equals 1.1 mm2. Metrick: Its function is to measure the precision (jitter) of the gencrated clock. Register files 1, 2, 3: Three register files which assure the storage of a “history”’ of 256 cycles: the measures of Metrick, the phase comparison values, and the digital command of the delays. Several test functions were added to the clock multiplier: an “open loop” signal which forcles the clock multiplier to work without feedback, a “bypass” signal which forces the C K r ef to be the only authorized flip-flop set and the lock finite state machine. Those functions enable the realization of a functional test. Moreover, Metrick allows the measurement of the output clock accuracy which would hlave been impossible to realize from outside given its high value.
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IX. EXPERIMENTAL RESULTS The measurements realized on the Tektronic LV500 test computer give the following results: a maximum output frequency of 172.41 MHz with an input frequency of 8.62 MHz and a code delay of zero; a minimum output frequency of 40.46 MHz with an input frequency of 2.03 MHz and a code delay of 237. The target frequency of 100 MHz is obtained with a code delay of 50. The measured delay step Sr is 92 ps, with a maximum oscillation around a locking point of three delay steps. This gives a maximum clock jitter of 276 ps. The diagram of Fig. 14 shows the range of output frequencies possible with an ES2 1 pm CMOS technology. using SPICE simulation in best, typical, and worst cases of the fabrication process. The tested circuit lies between best and typical simulation. In every case, the target range of 50-100 MHz is always completely obtainable.
X. CONCLUSION This work has shown that it is possible to produce a clock frequency multiplier with a delayed locked loop approach, without having to deal with the problem of analog components and without using a full custom approach. We have proven the feasibility of a parameterized frequency multiplier generator, with a large range of multiplication factors (between 4-20), providing a standard cell netlist for automatic place and route. These cells use symbolic layouts, so that circuits can be fabricated for any two metal digital CMOS technology and easily portable to submicron processes. The clock multiplier works at high frequencies over a large bandwidth and generates an output clock of high precision thanks to the epsilon technique. Indeed, with 1 pm 5 V technology, an output clock frequency of 170 MHz was measured with a period fluctuation of no more than 300 ps. For a clock frequency multiplier by 20, the power consumption is less than 135 mW and the maximum
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acceptable steepness in the supply voltage fluctuation is 10 mViDs.
REFERENCES I11 J. Alvarez. H. Sanchez, G. Gerosa, and R. Countryman, “A wide-
bandwidth low-voltage PLL for PowerPdrM Microprocessors,” IEEE J. Solid-State Circuits, vol. 30, no. 4, pp. 383-391, Apr. 1995. [21 I. A. Young, J. K. Greason, and K. L. Wong, “A PLL clock generator with 5-1 10 MHz lock range for microprocessors,” IEEE J. Solid-State Circuits, vol. 27, no. 11, pp. 1599-1607, Nov. 1992. PI D. Mijuskobic, M. Bayer, T. Chomicz, N. Garg, F. James, P. McEntarfer, and J. Portcr, “Cell-based fully integrated CMOS frequency synthesizers,’’ IEEE J. Solid-Stare Circuits, vol. 29, no. 3 , pp. 271-279, Mar. 1994. r41 J. Dunning, G. Garcia, J. Lundberg, and E. Nuckolls, “An all-digital phase-locked loop with 50-cycle lock time suitable for high-performance microprocessors,” IEEE J. Solid-Slate Circuits, vol. 30, no. 4, pp. 412422, Apr. 1995.
COMBES et al.: A PORTABLE CLOCK MULTIPUER GENERATOR USING DIGITAL CMOS STANDARD CELLS
[5] A. Cofler, J. C. Lebihan, R. Nezamzadeh, and R. Marbot, “Integration of multiple bidirectional point-to-point serial links in the gigabits per second range,” presented at Hot Interconnects Symp., Stanford, Aug. 1993. [6] A. Efendovich, Y. Afek, C. Sella, and Z. Bikowsky, “Multifrequency zero-jitter delay-locked LOOP,” ZEEE J. Solid-State Circuits, vol. 29, no. I, pp. 67-70, Jan. 1994. [7] F. J. Mowle, “Introduction to sequential circuit design,” A Systematic Approach to Digital Logic Design. Reading, MA: Addison-Wesley, July 1977, pp. 287-290. 181 A. Cofler, M. Combes, J. C. Lebihan, R. Marbot, and R. Nezamzadeh, “Circuit i retard variable,” Registered Patent no. 92.03527, 1992. [9] M. Combes, “Un gknkrateur paramktrahle de multiplieur de frkquence utilisant des techniques numkriques,” Ph.D. dissertation, Universitk Pierre et Marie Curie, Dec. 1994. [lo] A. Greiner and F. Pgcheux, “Alliance: A complete set of CAD tools for teaching VLSI design,” presented at 3rd EuroChip Workshop, Grenoble, France,-Oct. 1992.1111 . . A. Greiner and F. Pktrot, “Using C to write portable CMOS VLSI module generators,” in European Design Automation Con$, Sept. 1994, pp. 676-681. [I21 A. Greiner and J.-P. Leroy, “A symbolic layout view in Edif for process independent design,” presented at Fourth European Edif Forum Proc., Daresbury, Cheshire, U.K., 1990. [13] M. Combes, K. Dioury, and A. Greiner, “A portable clock multiplier generator using digital CMOS standard cells,” in European Solid-state Circuits Con$, Sept. 1995, pp. 66-69.
Michel Combes was born in L’Isle Adam, France, in 1969. He received the electrical engineering degree from the Institut superieur d’klectronique de Paris in 1991 on microelectronics and VLSI design. He received the Pb.D. degree in informatics and microelectronics from the University Pierre et Marie Curie (Paris 6 ) in 1994. In 1995, he joined Texas Instruments and he is currently in charge of the DSP Electrical team.
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Karim Dioury wds born in Casablanca, Morocco, in 1969. He received the masters from the University Pierre et Marie Curie (Pari7 6) in 1994 on microelectronics and VLSI design. Now, he is working toward the P1i.D. degree at the University Pierre et Marie Curie. As the final part of his masters project he contributed to the design and realization of the clock multiplier generator. His current research interests are timing analysis, interconnection, transistor modehzation, clock, and power supply tree design, VLSI design, and CAD tools
Alain Greiner was born in Paris, France, in 1952. He received the Ph.D. degree from the University Denis Diderot (Paris 7) in 1982. He worked six years at “Commissariat ? 1’Energie i Atomique” as a research engineer prior to earning the Ph.D. In 1986, he joined the BULL company, as a Senior Engineer. He was project leader in the team in charge of designing the Basic Processing Unit for the DPS7000 computer, the most powerful mainframe in this family. Since 1990, he has a permanent position as a Professor at the University Pierre et Marie Curie. He was the pro,ject leader for the ALLIANCE CAD system, a public domain VLSI CAD system distributed, and used in more than 250 universities worldwide. This project won the Seymour Cray prize in 1994. He is presently the head of the MAS1 Laboratory. His main interests are in computer architecture, VLSI design, and CAD tools.
