A STAFAN-like Functional Testability Measure for Register-Level Circuits

A STAFAN-like Functional Testability Measure for Register-Level Circuits C.P. Ravikumar Gurjeet S. Saund Department of Department of Electrical Engg. EECS IIT Delhi Urbana Champaign Illinois, USA 110016, INDIA

Abstract

at the stage of high-level synthesis. Since high-level synthesis programs explore a large design space, it is useful to have a fast and accurate testability measure which works on register-level components; with such a tool, it becomes possible to reject inferior designs at an early stage of design. Designs are characterized by three components - area A, delay D, and testability T which are indicators of the cost, performance, and testability of the design. While many estimators for area and performance are reported in the literature (see [10]), there are not many testability measures reported for this level of abstraction. Presently, the testability measure being employed at the registerlevel is the number of self-loops in the structure graph of the circuit. The structure graph is a directed graph constructed by associating a node with each register in the circuit and associating a directed edge from node i to node j when there exists a combinational path from the output of register i to the input of register j [5]. A self-loop in the structure graph represents a "self adjacent" register [2]; when built-in self-test is employed using BILBO architecture [1], a self adjacent register R must be configured both as a PRPG (Pseudo Random Pattern Generator) and an MISR (Multiple Input Signature Register) - an impossibility when concurrent BILBOs are not available. Therefore, most testability-driven synthesis tools attempt to eliminate the number of self-loops in the structure-graph of the final design [11, 2, 9]. Clearly, there are limitations to this testability measure.

STAFAN (Statistical Fault Analysis) is a well known testability analysis program which predicts the fault coverage of a digital circuit under the stuck-at fault model, without actually performing fault simulation. STAFAN offers speed advantage over other testability analysis programs such as SCOAP; further, it explicitly predicts the fault coverage for a given test set, unlike other testability measures which are harder to interpret. STAFAN works on gate-level digital circuits composed of basic logic gates. In this work, we show how a STAFAN-like testability analysis program can be constructed for circuits built out of register-level modules. With the proliferation of high-level synthesis and testability-driven synthesis, it is becoming more and more important to have fast testability analysis tools which operate on register-level components such as adders, multipliers, multiplexers, busses, and so on. Our testability analysis algorithm, which we call FSTAFAN, fills this void. We have implemented FSTAFAN on a Sun/SPARC workstation and describe its performance on several register-level circuits.

1

Nitin Agrawal * Wipro Infotech Ltd. Global R&D Bangalore 560001, INDIA

Introduction

It is becoming increasingly important to define a testability measure for a circuit composed of register-level components such as parallel adders, multipliers, registers, counters, multiplexers, and busses. With the proliferation of high-level synthesis softwares for digital systems, it is becoming common practice to design circuits using register-level components. Further, stress is now being laid on incorporating testability

• The testability measure is appropriate for specific test methodologies such as BILBO-based built-in self-test. • The testability properties of the combinational logic blocks in the circuit are ignored by the metric.

"The second and third authors were B.Tech students in the Electrical Engineering Department at IIT Delhi when this work was carried out.

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When gate-level circuits are concerned, a number of accurate testability measures are known. Popular among these are SCOAP (Sandia Controllability and Observability Program) proposed by Goldstein [6], STAFAN (Statistical Fault Analysis) proposed by Jain and Agrawal [7], and PREDICT (Probabilistic Estimation of Digital Circuit Testability) proposed by Seth and Agrawal [13]. SCOAP uses the controllability and observability of nodes to measure the testability of a circuit. Primary inputs are fully controllable and primary inputs are fully observable. Three numerical measures are associated with each node in a combinational circuit - the combinational 1-controllability CCi, combinational O-controllability CCQ, and combinational observability CO. In a sequential circuit, three other measures are associated with each node, corresponding to sequential testabilities. Goldstein gave simple rules to compute the controllabilities of internal nodes and primary outputs by traversing the circuit forward from the inputs to the outputs in a breadth-first manner [6]. The sum of the six testability measures of all nodes is the testability metric for the whole circuit; the smaller this value, the more testable the circuit.

signal probabilities in a combinational circuit.

1.1

Statistical Fault Analysis

The O-controllability C0(Z) of a line Z in a circuit is defined as the probability that a random test vector places the logic value 0 on the line I. The 1controllability C1(Z) is similarly defined. B0(Z), the O-observability of a line Z, is the probability that the logic value on I can be observed at one of the primary outputs, given that this logic value is 0. Thus B0(l) is the conditional probability that there is a sensitized path from I to one of the primary outputs, given that the value on Z is 0 when a random test vector is applied. The 1-observability of I, -Bl(Z), is similarly defined. It is possible to compute the detection probability dj of a fault stuck-at / on line Z, given the controllabilities and observabilities at line Z. For instance, the probability of detecting a fault I stuck-at 0 is given by d,_,a_o =

(1)

STAFAN gives us a method of computing the controllabilities and observabilities of each line in a gate-level circuit by simulating the circuit on N test vectors [7]. Thus logic simulation is used to count the number of times a 1 appears on a line Z when each of the N test vectors is applied. The Ones-count at Z can be used to compute C1(Z) as follows.

The advantage of the SCOAP metric is that it measures testability as a topological property of the circuit, without regard to a set of test vectors. In a survey of testability measures, Chandra and Patel [4] found that SCOAP comes closest to measuring the true testability of a circuit i.e. there is strong correlation between the fault coverage of a circuit and its SCOAP value. STAFAN estimates the fault coverage of a circuit under a given test set without actually performing fault simulation.

OnesCount(l) N

(2)

If we compute the detection probabilities for all the stuck-at faults in the circuit, we can compute the fault coverage of the circuit for the test set of N vectors. The probability that none of the N test vectors can detect a fault Z-sa-t; is given by (1 — di-ea-v)N• If F is the set of all relevant stuck-at-faults in the circuit, then the probability that at least one of the N test vectors will detect a fault / = Z s-a-i; is 1 — (1 — df) . Hence the fault coverage using N test vectors is

Signal probabilities have been used in computing the random-pattern testability of a circuit [13, 12]. The signal probability of a line / is the probability that a 1 is placed on line Z when exhaustive testing is employed. Simple algebraic rules can be applied to compute the signal probabilities at the outputs of logic gates, given the signal probabilities at their inputs. For instance, if PA and ps are the signal probabilities at the inputs of an AND gate, then the signal probability at the output C is simply pc = PA-PB- In a circuit without reconvergent fanout, these algebraic rules can be applied starting from the primary inputs and traversing the circuit in a breadth-first manner. For general circuits, however, computing the signal probabilities is an NP-complete problem [13]. The signal probability at a line / is related to the probability of detecting a stuck-at fault at line Z [13, 12]. Both [13] and [12] gave efficient algorithms for computing the

(3)

STAFAN was applied with success to several benchmark circuits. STAFAN is much less expensive in terms of CPU-time in determining the fault coverage than performing a complete fault simulation.

1.2

Organization

The testability measures discussed above are all intended for gate-level circuits. In this paper, we are

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interested in developing a testability analysis tool for data paths described at the register-transfer (RT) level. In the next section, we shall discuss the need for testability measures at the RT level. A fault model relevant for RT circuits is then described. A STAFANlike testability analysis tool (called FSTAFAN ) for RT level circuits is developed. Section 3 describes the implementation of FSTAFAN and reports results obtained on several example circuits. Conclusions and directions for further research are presented in Section 4.

2

Here G\ is the BDD corresponding to the subcircuit which forms the entry point to Gf. Jamoussi et al [8] have also presented techniques to compute the Variable Testability Measure (VTM) of signal lines in a register-level circuit. Again, VTM of a signal line x is defined as the minimum number of test vectors required to test the function represented by line x. For example, the VTM of each primary input is 2. Given a structural description of a circuit, the authors of [8] have described a method to compute the VTM of each module-external line using the BDDs of the modules. The sum of the VTMs at the primary outputs is then used as a measure of testability of the entire circuit. The drawbacks of this approach are as follows.

Functional Testability

In reality, most digital systems are designed using register-level modules rather than gates. If gate-level testing and testability-analysis tools are to be used with practical systems, it would call for an flattening procedure which is expensive both in terms of memory and CPU-time. Frequently, the results of applying testing and testability analysis procedures to building blocks of circuits are available; for instance, the test patterns and SCOAP measures for a 4-bit ripple carry adder may be available. This information, albeit useful, is ignored when the system is expanded into its gate-level description. There is thus a need for space and time-efficient testing algorithms that work on RT level circuits. Of particular importance are efficient testability analysis tools for RT level circuits. These can be employed by testability-driven high-level synthesis algorithms such as the genetic algorithm for testability-driven pipeline synthesis reported in [11]. There is limited work available today on testability analysis tools for RT level circuits. Jamoussi et al have reported a cyclomatic test measure (CTM) for deciding the testability of combinational function / from its Binary Decision Diagram [8]. The testability is measured as the lower bound on the number of test vectors required to test any realization of /. If Gj is the BDD representation of the function /, then the minimum number of test vectors required to test any implementation of / is given by

V(Gf)

-n-

• It is difficult to interpret the VTMs of the signal lines of the circuit collectively as a testability measure. Let I(X) be the set of all primary inputs on which a primary output X depends; it is rarely the case that for two primary outputs Xi and Xj, I(Xi) f] I(Xj) = . Thus VTM(Xi) + VTM{Xj) is not a true measure of the number of test vectors required to test the functions represented by X{ and Xj. In FSTAFAN , we will provide the fault coverage of the circuit achieved by a specified test set. Fault coverage is much easier to interpret as a measure of circuit testability. • There is no direct way of computing VTMs in a circuit with feedback. The authors of [8] suggest the use of dummy multiplexers to counter this problem. FSTAFAN , like STAFAN, can handle circuits with feedback by breaking the feedback loop(s) and iteratively computing the controllability and observability of the feedback line(s) until convergence is obtained. • When a circuit structure is such that VTMs cannot be determined, [8] will infer that the circuit is untestable. For example, consider the circuit of Figure l(a), where the VTMs of the adder outputs cannot be determined. In this case, the conclusion about the untestability of the circuit is valid; e.g. the register Rl is self-adjacent and cannot be configured both as a pattern generator and as a signature register during self-test mode. On the other hand, the same conclusion will not be true for the circuit of Figure l(b), where the adder can be tested by configuring Rl and R2 as pattern generators and R3 as a signature register.

(4)

where n is the number of nodes in Gj. If a function can be decomposed into p subfunctions / i , /a, • • •, / P , and the corresponding BDDs are Gj., (?2, • • •, Gp, then [8] gives (5)

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Rl

R2

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procedure Sensitization (T, M) { Updating the sensitization count for the inputs of module M after simulating the input vector T for M } begin for each bit i in T do begin Invert the value of bit i; Repeat the functional simulation of M; if an output j of M changes then SCOUNT{i,j):= SCOUNT{i,j) +1; end end

R2

R R3

Figure 1: An Untestable Circuit and Its Testable Variant

Figure 2: Updating the sensitization count

2.1

A Fault Model for Register-Level Circuits

modules fed by the primary inputs are simulated and the values generated are in turn used in the simulation of the next level of logic, and so on. The values at the output of each module are then unpacked into bit streams to evaluate the one count, zero count, and sensitization count of each module-external line. While it is straightforward to update the one count and zero count at the end of each simulation, some explanation is required for updation of the sensitization count. Figure 2 explains the algorithm for updating the sensitization count. Note that we maintain sensitization count for every input-output pair of bits (i, j) for the module under consideration. Some optimization is possible by identifying a priori the subset of outputs that are sensitive to an input line i.

A register-level circuit consists of an interconnection of functional modules such as n-bit adders, multipliers, multiplexers, and registers. We define moduleinternal lines as signal lines that are internal to the functional modules; these lines do not appear explicitly in a register-level description. On the other hand, module-external lines appear explicitly in an RTL description of a circuit. Using conventional testability analysis tools such as STAFAN or SCOAP may not even be possible on RTL circuits since the internals of the modules are unknown and thus the faults on the module-internal lines cannot be defined. Even when the structural descriptions of modules are available, the effort involved in flattening the module to its gatelevel description is non-trivial and memory-intensive. In the experiments conducted by Brglez et al [3], the authors found that test vectors generated for stuckat faults on module-external lines covered most of the stuck-at faults on module-internal lines as well. Based on the above considerations, it makes sense to consider only the stuck-at-faults on the module-external lines in the testability analysis of an RTL circuit. This is the approach followed in FSTAFAN.

2.2

Testability Lines

of

Module-External

FSTAFAN computes the controllability and observability of each module-external line after the completion of the simulation phase. The one-controllability of a module-external line I is defined as Cl(l) = OnesCount(l)/N, where N is the number of test vectors; zero-controllability is similarly defined. The observability O(l) of a module-external line is defined recursively as follows. If I is a primary output, its observability is defined as unity; otherwise, the line I may be observable implicitly through one or more module-external lines j, where j is an output of the module M which is fed by I. Let O(l, j) denote the observability of line I through line j.

FSTAFAN estimates the fault coverage obtained using a specified test set on a given circuit, without actually performing fault simulation. Instead, it performs functional simulation of the good circuit on every test vector. Thus, a A:-input module M is interpreted as a function g -.TZxTZx- • -Tl i->72. FSTAFAN can handle a number of library modules such as n-bit adders and multipliers, registers, multiplexers, busses, and so on. It is also possible to handle simpler cells such as complex gates which are used in logic synthesis. Beginning with the primary inputs, we interpret the binary test vector as a set of one or more real values, based on the functionality of the circuit. The

SCOUNTjlJ) xO(j) N

(6)

To compute the observability of line I, we follow the approach used in [7] to evaluate the observability of a fanout stem using the observabilities of the fanout

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branches. Assuming that the lines j are independently observable at the primary outputs, we compute the upper bound on the observability of line I as

Similarly, a lower bound on the observability O(l) is found as O(l)>maxj O(l,j) (8) We compute O(l) as a weighted average of the two bounds found above

(a)

Figure 3: Circuit for Example jkex. (a) Original Circuit, (b) Circuit modified for improved testability.

(9) where the constant a, 0 < a < 1 is found heuristically.

2.3

a=input_2 b=input_2 c=input_2 d=input_2 e=input_2 f=in.put_2 cini=input_i cin2=input_l ctrll=input_l g,coutl=adder_2(a,b,cinl)

Estimation of Fault Coverage

After computing the observability and controllabilities of module-external lines, we compute the detection probabilities of each stuck-at fault. Fault coverage is then estimated using Equation 3. For further details, we refer to Section 1.1 and to [7].

3

Implementation and Results

h,cout2=adder_2(d,e,cin2) c out1=output _I c out 2=output _1 i=mul_2(c,±) j=mul_2(li,g) ik=mux_4:(i> j , c t r l l ) k=outpiLt_4

FSTAFAN has been implemented on a Sun-SPARC workstation in C programming language. The complete software requires about 3500 lines of code. The input to FSTAFAN is read from a text file containing the description of the circuit composed of modules such as n-bit adders, multipliers, registers, multiplexers, and basic gates. The description of the example circuit used in [8] (see Figure 3) is shown in Figure 4. The user has the option to estimate either the random-pattern testability of the circuit or the fault coverage achieved by a specified test set. The output of FSTAFAN is an estimate of the percentage fault coverage achievable through the specified test set. We ran FSTAFAN on a number of small as well as large example circuits to study its performance. Figure 5 shows the results obtained using FSTAFAN on the example jkex drawn from [8]. The original circuit (shown in Figure 3(a) above) is declared as a less testable circuit in [8] using the VTM testability measure. This observation is confirmed by the results obtained using FSTAFAN , which predicts higher fault coverage for the modified circuit for the same number of test vectors. Figure 7 shows the plot of the estimated fault coverage when FSTAFAN is used on a circuit described at four different levels of abstraction. The circuit considered in this experiment was an 8-input adder which

Figure 4: Textual Description of Example jkex(b)

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0

computes the sum of 8 4-bit unsigned numbers. Level1 refers to a description of this circuit using simple gates and Exclusive OR gates. Level-2 corresponds to a description using full adders, and Level-3 corresponds to a description using 4-bit adders. The number of faults at Level-1, Level-2, and Level-3 were 798, 192, and 142 respectively. The gate-level description had 1276 faults. It is clear from Figure 7 that the error in estimation of fault coverage decreases with an increase in the number of test vectors. However, the estimated fault coverage becomes more and more optimistic with higher levels of abstraction; this is mainly due to the diminishing size of the fault set. The proposition that module-external faults are "equivalent" to a number of module-internal faults becomes less true at higher levels of abstraction. Figure 8 shows the plot of the execution time of FSTAFAN for the 8-input adder circuit when the number of test vectors is increased. Gate-level STAFAN is about 5 times more expensive than FSTAFAN (Level-3), about 3.5 times more expensive than FSTAFAN (Level-2), and about 1.72 times more expensive than FSTAFAN (Level-1) for 100 test vectors. The savings in execution time will be even more significant for larger circuits and larger number of test vectors.

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Figure 7: Fault Coverages Estimated by FSTAFAN for 8-input Adder Circuit for different levels of abstraction.

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We have presented a Statistical Fault Analysis tool called FSTAFAN which borrows ideas from STAFAN [7] and extends them to circuits composed of macro blocks. FSTAFAN is applicable to technology-mapped circuits and data paths. It is also applicable to mixed-level circuits. FSTAFAN can provide signifi-

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cant speedups in the estimation of fault coverage without too much loss of accuracy when the number of test vectors is large. We have described an implementation of FSTAFAN and results obtained using FSTAFAN on some examples. We are currently extending FSTAFAN to handle circuits with feedback loops; the essential modification required in this case will be to identify loops in the structure of the circuit and break the loops by removing some of the directed edges. FSTAFAN can then be applied iteratively, very much in the line of SCOAP [6] or STAFAN [7].

[8] M. Jamoussi et al. A new variable testability measure : a concept for data-flow testability evaluation. In Proceedings of the International Conference on VLSI Design, India, pages 239-244, 1991. [9] A. Mujumdar, K. Saluja, and R. Jain. Incorporating testability considerations in high-level synthesis. In Proceedings of the Fault-Tolerant Computing Symposium, pages 272-279, 1992. [10] A.C. Parker, M. McFarland, and R. Camposano. The high level synthesis of digital systems. Proceedings of the IEEE, 78, February 1990.

Acknowledgements We acknowledge initial discussions with Vikram Saxena, presently with Department of Electrical and Computer Engineering, University of Illinois, UrbanaChampaign.

[11] C.P. Ravikumar and V. Saxena. TOGAPS - a testability oriented genetic algorithm for pipeline synthesis. Technical report, Department of Electrical Engineering, Indian Institute of Technology, Delhi, 1994. Submitted for Publication.

References

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[2] L. Avra. Allocation and assignment in high-level synthesis for self-testable data paths. In Proceedings of International Test Conference, pages 463472, 1991. [3] J.D. Calhoun and F. Brglez. A framework and method for hierarchical test generation. IEEE Transactions on Computer-Aided Design, 2(l):45-67, January 1992. [4] S.J. Chandra and J.H. Patel. Experimental evaluation of testability measures for test generation. IEEE Transactions on CAD, 8(l):93-97, January 1989. [5] K.-T. Cheng and V.D. Agrawal. A partial scan method for sequential circuits with feedback. IEEE Transactions on Computers, 39(4):544548, April 1990. [6] L. H. Goldstein. Controllability/observability analysis of digital circuits. IEEE Transactions on Circuits and Systems, 26:685-693, 1979. [7] S.K. Jain and V.D. Agarwal. Statistical fault analysis. IEEE Design & Test of Computers, pages 38-44, February 1985.

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