AC-JTAG: Empowering JTAG beyond Testing DC ... - Semantic Scholar

AC-JTAG: Empowering JTAG beyond Testing DC Nets Sung S.Chung and Sang H. Baeg Cisco Systems, Inc. 170 W. Tasman Drive San Jose, CA 95134

ABSTRACT This paper presents the new technology that extends today’s JTAG’s capability from DC domain to both AC and DC domains. New concept, AC_EXTEST is introduced to support AC interconnection test and to have backward compatibility with EXTEST. It leverages existing application software available within boundaryscan test industry to promote this technology to manufacturing floor with minimal impact.

1

Introduction

Bandwidth requirements for internet devices (e.g. switch, router) have increased over multiple Tera-bits per seconds in today’s network equipments. This type of industry trend promotes use of high-speed serial interconnections instead of parallel bus based communications in relatively lower speed. The typical serial interconnections can be found in devices such as SERDES (SERializer DESerializer) and VCSEL (Vertical Cavity Surface Emitting LASER) device. SERDES takes parallel data and transforms to serial bit stream or vice versa. It is often interconnected with VCSEL devices to transmit or receive optical signals or with SERDES for high-speed serial connection. Transmission speed in the connection starts from 1 GBPS (Giga-Bits Per Second) in optical interface. In many cases, such serial interconnections are AC coupled nets. For performance reasons, only high frequency signals are delivered to other party and amplified. To increase noise immunity, the interconnections are often connected differentially. Since receivers only see the differences of the signals, the noise appearing both differential lines is canceled out by so called common-mode rejection. The traditional interconnection test schemes based on IEEE 1149.1 are no longer valid under such conditions [1, 2, 5-8]. Devices utilizing AC coupled connection in parallel optics

Paper 2.1

transceiver modules are under development by optical vendors for Cisco Systems Inc. Figure 1 shows two types of interconnections between devices in terms of interconnect testability. The first type is a net testable by standard IEEE 1149.1, where DC value is driven and captured. The second type of nets is AC coupled net, which goes beyond the IEEE 1149.1’s capability. Capacitance can be coupled on board or embedded inside devices, which look like DC nets by outward appearance. IEEE 1149.4 [5] addresses analog pins, however current IEEE 1149.1 defines them as “linkage” so that the signals are no longer test resources [1, 2, 9]. IEEE 1149.1 based approach was considered as a better candidate for the AC coupled line test than with IEEE 1149.4 since AC coupled signal lines carry high speed digital signals rather than analog signals. Additional issues listed below prevented further utilization of IEEE 1149.4 as primary means of testing AC coupled nets. • •

•

•

• •

IEEE 1149.4 is harder to implement and has higher area, delay and power overhead than IEEE 1149.1. High-speed differential signaling technology requires very tight timing constraint so that fully compliant ABM implementation is difficult with today’s technology. Wide variations of termination methods used in differential lines add longer test time with IEEE 1149.4 when there are 100s of such nets within the device. Power budget needed for Parallel Optics modules is not suited for the 1149.4 implementation because it adds substantial area overhead, in turn it adds more power dissipation. Device must work with the DC coupled and AC coupled application with existing IEEE 1149.1 environment. The solution must support interoperability with the existing legacy device within IEEE 1149.1.

ITC INTERNATIONAL TEST CONFERENCE

30

Proceedings of the International Test Conference 2001 (ITC’01) 0-7803-7171-2/01 $17.00 © 2001 IEEE

0-7803-7169-0/01 $10.00 © 2001 IEEE

In this paper, new boundary scan method is proposed to solve testing of AC coupled interconnection nets under IEEE 1149.1 environment. Section 3 discusses objectives of this project. The system view of AC-JTAG is explained in Section 4. The new concept, AC_EXTEST is defined in section 5. Design examples for boundary scan cells are shown in section 6. The philosophical aspect of fault coverage is discussed and coverage result is shown for LVDS (Low Voltage Differential Signal) in section 7 [3]. Device 1

Device 2 or Connector

STD 1149.1 capable

We call this technology as DC-JTAG for convenience. Under DC-JTAG, DC patterns are applied by drivers and DC patterns are captured by the counter-part receivers. If there is an AC coupling element on the DC line, the AC signals need to be transmitted and received for proper communication. When such AC signals are used for interconnect test under boundary-scan environment, we call it ACJTAG. AC-JTAG and DC-JTAG should be selectively executable. •

Self-Contained Technology: AC-JTAG should be developed, deployed, and executed independently and should not depend on or be driven from the mission logic function. It should be portable to migrate designs easily from one design to different designs and process technologies. It should also be as transparent as possible to existing boundary-scan ATE equipments.

•

Minimal Impact to JTAG Application Software: The current boundary scan softwares should be available with minimal additive enhancement without invalidating existing functions. This is critical aspect of the new technology development due to time pressure on the manufacturing floor.

•

Interoperable with Broader Supply Base: ACJTAG should use simple and clear protocol so that many different devices from different vendors can support AC-JTAG. At the same time, legacy devices should work with devices equipped with AC-JTAG.

STD 1149.1 incapable

STD 1149.1 incapable

Figure 1: DC and AC Coupled Nets

2

Definitions

AC: Alternating Current AC Coupling: if steady state value at the receiving end of the net is no longer the same value as in driving end, then the net is so call AC coupled. The net has serial coupling with a capacitive component. A DC de-coupled net is an AC coupled net. AC Boundary-Scan: general term to describe AC coupled net test capable boundary-scan structure. It consists of a pattern generator and pattern capture with optional synchronizing pulse, and a pattern mapping mechanism if necessary to map captured AC signals back to the expected DC value. AC pattern: consist of serial bit stream with certain clock speed. The pattern has fixed length and repeats itself continually. As a simplest form, it can be a LFSR with single feedback, which has polynomial form of f(x) = 1+Xn. Other known coding sequences also can be used. AC pattern clock: clock used to generate AC pattern. DC pattern: test pattern with the constant driving value during the entire duration of given test cycle.

3

Objectives

This section discusses the major considerations taken during the development. •

Dual Mode Support for both AC and DC: The conventional JTAG is used to test only the DC lines.

4

System Overview

Figure 2 shows the logical view of the AC-JTAG system. This layer model is introduced to explain and discuss AC-JTAG in IEEE 1149.1 domain. There are three layers in the system model, application link layer, logical link layer, and physical link layer. When two AC boundary-scan cells are communicating each other, they are communicating through the three layers. The bold lines in the figure show the data flow through layers. Application link defines communication protocols between devices, and runs boundary-scan test algorithms. It works over the logical link layer. The protocol is named as AC_EXTEST and discussed in the next section. Logical link layer provides the foundation under which interconnection is checked. The link is logically connected when the driven value is same as the received value. The logical values are either high or low.

Paper 2.1 31


Driving AC Boundary Scan Cell

Application Link

1149.1

Receiving AC Boundary Scan Cell Protocol under AC_EXTEST and RTI

0

Logical Link

1

Physical Link

1149.1

0

0

1

1

101010...

101010...

010101...

010101...

Figure 2: System Layer Model for AC-JTAG Since we assume the application layer works on the logical layer, the application software in boundary-scan industry doesn’t need redevelopment. Physical link layer represents physical connection between two devices. When DC-JTAG is selected, a driver takes a logical value from logical link and puts it on the physical link. The receiver does the same but in reverse order. Note that the values in the physical link are same as in the logical link. When AC-JTAG is selected, it takes a logical value from the logical link layer, translates it to an AC signal, and drives the actual physical link. The receiver monitors the AC signal and translates it back to a logical value, which will be passed to the logical link layer. Two major components in the AC-JTAG system are discussed further in detail: AC pattern generation, and AC pattern sample.

4.1

AC Pattern Generation

AC patterns generation belongs to the physical link layer. The patterns are generated and driven from the driving side of the AC boundary scan cells and received by the receiving side of AC boundary scan cells. Three different pattern generation schemes are discussed here. •

•

Built-in AC pattern generation (BAPG): this scheme is a distributed test generation system, in which each AC boundary scan cell in a chip has a built-in AC test pattern generator. Parallel AC pattern generation (PAPG): this is a centralized test generation scheme, in which one centralized test pattern generator drives a group of AC boundary scan cells in a certain sequence. In this

Paper 2.1 32 Proceedings of the International Test Conference 2001 (ITC’01) 0-7803-7171-2/01 $17.00 © 2001 IEEE

•

scheme, all AC boundary scan cells receive the same pattern from the central test generator. Serial AC test generation (SATG): this is also a centralized test generation system like the parallel scheme. It is different from the parallel scheme in how patterns are delivered to boundary scan cells. In this scheme, test pattern is fed to boundary scan cells serially through a shift register chain instead of a single wire common to all boundary-scan cells as in the parallel scheme.

PAPG saves hardware overhead paid for each boundary-scan cell, but in turn needs global wiring from the central pattern generation logic to every AC boundary scan cells. SATG saves such global routing overhead by shifting the AC patterns serially but it may need additional shifting chain for the AC pattern. If BAPG implements a simple AC pattern generation mechanism, the expected overall hardware overhead penalty is not significantly different among the three approaches. The major advantage of PAPG and SATG is to provide rather complex AC patterns such as 8B/10B encoding [4] without adding too much of additional hardware overhead when other AC pattern is implemented. A design example is shown using BAPG in section 6.

4.2

AC Pattern Sample

The receiving device with help of the driving device should determine the time to sample a constantly varying AC signal. The receiving AC boundary-scan cell is responsible for decoding a DC value from the AC pattern. In order to achieve this goal, the cell must sample the AC signal at pre-determined sample intervals. The sampled value(s) are decoded, and then used by traditional test

software for comparison. The decoded value should be the same logical value as on the driving side as a result of the decoding process. This step corresponds to the procedure from the physical link to the logical link in figure 2. The time interval to sample AC signal can be determined explicitly or implicitly.

4.2.1

Explicit AC Sample Scheme

Driving device reports the sampling time for a AC signal to its counter-part receiving device by the explicit signal, called AC capture signal. The receiving device purely relies on the signal to sample the AC pattern. While explicit signaling enables clear communication among devices, it has disadvantage of having multiple extra AC capture signals connected over multiple devices, especially when a device is receiving AC capture signals from multiple driving devices. Board designers may elect one for a master driver to avoid multiple AC capture signals from going to a device. Since the data and clock signals are transmitted together, this scheme requires a careful timing adjustment during board design as in source synchronous designs.

4.2.2

AC EXTEST1

5

AC_EXTEST defines an application layer protocol to enable testing AC coupled nets when AC boundary-scan cells are used.

5.1

The AC_EXTEST Instruction

The AC_EXTEST is a public instruction in IEEE 1149.1 and is a super set of the mandated EXTEST instruction. AC_EXTEST works with the AC boundaryscan cell, which is backward compatible with the mandated EXTEST instruction when the cell is under the EXTEST instruction. When the AC_EXTEST instruction is selected, the boundary-scan register cells determine the state of all system output pins. As in the mandatory EXTEST instruction defined in the IEEE 1149.1 Standard, AC_EXTEST would load data into the latched parallel outputs of boundary-scan shift-register stages using the PRELOAD instruction. The AC_EXTEST capable AC boundary-scan register cells located at system output pins (2-state, 3-state, or bi-directional) can generate AC patterns during the Run-Test/Idle controller state.

Implicit AC Sample Scheme

In this scheme, no explicit AC capture signal is transmitted as in the previous case. The receiving device recognizes the sample time by processing the protocol defined in the application link layer. AC boundary scan cells are timed to sample the AC signals based on such protocol. The details are discussed in the next section. Start

Preload Test Stimulus

Initiate AC_EXTEST Instructio n

Execute AC_EXTEST Instructio n

Reload Net Test Data

The snapshot of AC pattern signal is sampled at the system input pins during the Run-Test/Idle controller state at every 16th AC pattern cycles and the falling edge of the AC pattern clock as shown in Figure 5. The 16th cycle is a part of implicit synchronization scheme discussed in section 4 and selected as an interoperability reason. Explicit synchronization can be used when a device-todevice interconnection is well defined. The decoded DC value from sampled value(s) shall be the same value as the data held in the driving AC boundary-scan register cell at the system output pins. Then the sampled value in the AC Boundary-scan cell is loaded onto the boundary-scan Capture register cell on the rising edge of TCK in the Capture-DR controller state. Figure 3 shows the expected execution for AC_EXTEST. Execution effects after Capture-DR

Transfer AC_EXTEST Instructio n Results

Instruction

Evaluate AC_EXTEST Results

AC Scan Cell

DC Scan Cell

Passing through RTI

Bypassing RTI

AC_EXTEST

AC_EXTEST

EXTEST

EXTEST

EXTEST

EXTEST

EXTEST

EXTEST

End

Table 1: Comparisons of AC_EXTEST and EXTEST

Figure 3: Expected AC_EXTEST Execution 1

AC_EXTEST is a Cisco’s invention Paper 2.1 33


5.2

a)

Both the system output pins and the system input pins are interconnected and are under the AC_EXTEST instruction. The test shall work properly regardless of AC coupling between the interconnections. b) If there is no AC coupling between two devices, the system output pin under the EXTEST instruction shall operate with the system the input pin under the AC_EXTEST instruction. c) The system output pins under the AC_EXTEST instruction shall operate as the EXTEST instruction if the TAP controller is not in the Run-Test/Idle controller state.

Link to EXTEST

When the AC_EXTEST instruction is selected, the system output pins follow rules set by the EXTEST instruction, except for the system output pins with the AC boundary-scan cells. The pins equipped with an AC boundary-scan cell apply AC patterns in the Run-Test/Idle controller state, instead of steady state logic levels as in the EXTEST instruction. Table 1 shows the effects of AC_EXTEST compared to EXTEST. The devices under AC_EXTEST operate as an AC_EXTEST only when the TAP controller goes through Run-Test/Idle controller state. AC_EXTEST works the same way as EXTEST if the TAP controller goes to the Capture-DR controller state without passing through the Run-Test/Idle controller state after each Update_DR or Update_IR.

The system input pins under the EXTEST instruction may not perform the test properly with the system output pins under the AC_EXTEST instruction and should be avoided. The input pins capture unpredictable AC values, which are unknown to the DC world.

AC_EXTEST instruction should provide interoperability with the following test combination of the conditions: To next cell Data from system logic From last cell ShiftDR AC_Test AC_Pattern_Clock or ClockDR

To system pin

0 1

0 1

D

Q

ck Q

D

Q

To next cell 0 1

0 1

ck

0 1

D AC_Sync

ck

Q

0 1

0 1

D ck

Q

D

Data to system logic

Q

ck

AC_Test_Ran From last cell ShiftDR ClockDR UpdateDR DC_Mode

AC_Test_Marker UpdateDR AC_Test DC_Mode

TCK

From system pin

0 1

Figure 4: Example AC boundary-scan cell BC_1 value. Figures 4 shows the examples of AC capable boundary-scan cells and various signals used in the examples. The major signals are explained as follows:

Run-Test / Idle AC Pattern A =1 AC Pattern A = 0 AC_Sync A

Figure 5: Example timing diagram of critical signals

6

•

•

Boundary-scan cell Design examples

The AC boundary-scan cell can have predefined function of BC_0 to BC_10, which carry all the semantics of 1149.1 with additional AC related portions. The AC test pattern generation and capture capabilities are added to the existing boundary scan scheme. The AC boundaryscan cells together with the AC capable TAP controller have pattern generator, and pattern capture functions, as well as pattern mapping circuitry if necessary to convert preloaded DC (logic) value into AC patterns and the sampled AC signals back to the expected DC (logic)


•

AC_Test: a function of the AC_EXTEST instruction and the Run-Test/Idle controller state. It becomes true when the TAP controller is in the Run-Test/Idle controller state under the AC_EXTEST instruction. AC_Pattern_Clock: the AC pattern generation and pattern sample logic use the same clock known as “AC pattern clock”, shown here as “AC_Pattern_Clock” to synchronize pattern generation and sample operations. The signal “AC_Pattern_Clock” is a shared clock for AC pattern generation and the ClockDR for capturing and shifting of boundary-scan test signals. AC_Test_Marker: a single event that is one and a half pattern clock cycle long, and positive going pulse to mark the beginning of the AC pattern generation sequences. It is used to set the pattern generation flipflop with a known value.

6.1

AC_Test_Ran: used to control the input AC boundary-scan register cells to capture from the system pin input buffer instead of capturing from AC pattern sample flip-flop. In special cases where the AC_EXTEST instruction is executed without going to the Run-Test/Idle controller state, this mode of operation is enabled and the signal forces the AC boundary-scan register cell to act like a DC scan cell.

AC Boundary Scan Cell Design Example

The examples in Figures 4 are boundary-scan register cell type BC_1 and maintain compatibility with existing EXTEST. AC boundary-scan cells can be mixed into the design with any of the IEEE 1149.1 Standard compatible devices. The left portion of Figure 4 shows an AC scan cell with a built-in AC pattern generator, it generates AC patterns using “AC_Pattern_Clock” and boundary-scan Capture register cell. First, the EXTEST value from the Update scan cell is copied into the boundary-scan Capture and register cell with “AC_Test_Marker” Subsequent “AC_Pattern_Clock”. “AC_Pattern_Clock” starts to generate a AC pattern and the pattern is fed into the system pin. The right portion of Figure 4 shows an example of input scan cell with the AC_EXTEST capability. There is an extra AC pattern sample flip-flop with an “AC_Sync” signal, which can be generated either explicitly or implicitly as discussed in Section 4.

translated to the logical value used by the application layer. Since there are so many types of drivers and receivers combined with different technologies, we believe that it is an entirely new area of research to define both the sampling and encoding methods. In this section, we have shown fault coverage for LVDS (Low Voltage Differential Signal) without adding any special receiving features for fault detection purposes on normal LVDS receiver to demonstrate the coverage that plain AC-JTAG without special buffer technology can achieve.

7.1

LVDS Connection

The differential line with point-to-point connection using LVDS is typically configured as in Figure 6. The driver is both sourcing and sinking current. The termination registers at the receiving side will provide differential voltage of 350mV. Please see [3] for LVDS specification. LVDS Line Driver Q D

SET

CLR

DATA Transmit

Q

SET

QB

CLR

3.5mA

Q

Q

Figure 6: A Typical Point-to-Point LVDS Application gnd vdd

D

S ET

gnd vdd

Q

D

Q

SE T

CLR

Q

Q

fault injections

Figure 7: Faults inject points in LVDS pair

Signal before CAP

Fault Coverage

Signal after CAP

The application link layer (see section 4) determines the physical link quality based on the translated logical value. The DC connection in IEEE 1149.1 is checked pretty well in this environment because logical representation is identical as in the physical signal value system (i.e. high and low values). However, AC connection is not easily mapped to the existing JTAG system due to time variant nature of AC signals. While time factor is removed during transforming AC signal to a logic value, it is likely to mask out some failures. Therefore, test quality purely depends on how AC signals are sampled and decoded before they are

D

DATA Receive

gnd vdd

7

Rt 100Ohm 350mV

Q

CLR

When “AC_Test_Ran” signal becomes active, signifying the AC_EXTEST has been executed under the Run-Test/Idle controller state, the Capture scan cell captures value from the AC pattern sample flip-flop; otherwise, it captures a value from the system pin. This selection of capture source is controlled by the signal the “AC_Test_Ran”.

LVDS Line Receiver

3.5mA

gnd vdd

•

Recovered Signal

Figure 8: AC signal transitions

7.2

AC Coupled Capacitance

To create AC coupled lines to the differential lines, a capacitance is added to the receiving end of a LVDS

Paper 2.1 35


receiver. 100nf coupling capacitances are used in this experiment; however, the coupling capacitance can be a much smaller or higher value. As the coupling capacitance is getting smaller, the signal after coupling capacitance is no longer same as the signal before the coupling capacitance. Since only the high frequency components of the incoming signals passes through the capacitance, the signals in the receiving side will be both positive and negative going pulses at the rising and falling edges of the incoming square waveform signal respectively. Signal Number

Fault Type

1 2 3 4 5

Open Open Open Open Short

6

Short

7

Short

8

Short

9 10 11 12 13 14 15 16

Stuck-0 Stuck-1 Stuck-0 Stuck-1 Stuck-0 Stuck-1 Stuck-0 Stuck-1

and

AC Yes Yes Yes Yes Yes

Coverage AC + DC Yes Yes Yes Yes Yes

and

Yes

Yes

and

No

Yes

and

No

Yes

Yes/No Yes/No Yes Yes/No Yes/No Yes/No Yes Yes/No

Yes/No Yes/No Yes Yes/No Yes/No Yes/No Yes Yes/No

Signal Positive before CAP Positive after CAP Negative before CAP Negative after CAP Positive before CAP Negative after CAP Positive after CAP Negative before CAP Positive before CAP Positive after CAP Negative before CAP Negative after CAP Positive before CAP Positive before CAP Positive after CAP Positive after CAP Negative before CAP Negative before CAP Negative after CAP Negative after CAP

recovery logic can be added to handle such cases in the receiving side before the AC signal is captured by AC boundary scan cell. Such recovery logic belongs to the physical layer. So the AC_EXTET protocol is not affected by such signals behavior. Figure 8 shows the signal transitions through a small coupling capacitance and effects of the signal recovery logic. The signal transitions are for one leg of the differential pair seen in Figure 7.

Comments

Combining with DC test might detect this fault Combining with DC test might detect this fault May require longer simulation time Depends on Stuck voltage level Depends on Stuck voltage level May require longer simulation time Depends on Stuck voltage level Depends on Stuck voltage level

Table 2: Fault injection and coverage for LVDS AC coupled differential lines

7.3

Fault Coverage

Faults are injected using resistors as shown in Figure 7. Certain resistors are initially set to infinite (zero) number and changed to zero (infinite) value to create short (open) faults. Table 2 summarizes coverage report based on the Spice simulation for the LVDS pair connection through capacitance. The first column represents the fault number. Fault type is shown in the second column. In the third column, fault location is specified. “Positive” and “negative” describe the polarity of differential signals in a connection. The forth column in Table 2 shows the coverage when only AC_EXTEST result is considered and the fifth one shows the coverage when both AC and DC test results are


combined. The coverage analysis is purely based the previously defined AC_EXTEST without assuming any special circuitry in the receiver side. To demonstrate the detection mechanism used in this experiment, two spice simulation results are shown in Figures 9 and 10. Figure 9 shows the normal behavior and Figure 10 is the behavior with fault number 1 in Table 2 . The first two signals in the figures show the input and output pulses. The next four signals represent the differential signal pairs before and after the coupling capacitance. The output of circuit with a fault is different from the normal behavior.

build and execute the instruction. AC pattern generation and sample methods have been illustrated with design examples. Fault coverage result is presented using LVDS I/O technology.

Acknowledgements

Figure 9: Normal LVDS behavior

This technology has been presented and reviewed by many MSA (Multi Source Agreement) partners for Cisco Parallel Optics module vendors. Authors wish to thank the those who provided advice and feedback, especially Pandu Sharma at Cisco Systems Inc., and Robert Schuelke at AMCC.

References

Figure 10: Behavior with fault number 1 All the open faults are detected. For the short faults, there are two faults (i.e. 7 and 8) that are not detected in AC test. However the faults can be identified when test results in DC domain are combined. If a DC test is run, the short faults will not be detected since the short line creates a DC link instead of an AC link. The AC link is not broken in this LVDS case since original LVDS is working properly without the coupling capacitance. However initial assumption is that the DC test should fail because of the coupling cap, so the fault is detected by an inductive analysis. Faults are “conditionally” detected when “Yes/No” appears in the coverage column. Since the LVDS is a differential signaling method, the stuck voltage level at one leg will affect the differential voltage across the differential receiver, which makes coverage conditional.

8

Conclusion

[1] IEEE Standard 1149.1a-1993, “IEEE Standard Test Access Port and Boundary-Scan Architecture”, IEEE Standards Board, New York, October 1993. [2] Supplement to IEEE Standard 1149.1-1990, “IEEE Standard Test Access Port and Boundary-Scan Architecture”, IEEE Standards Board, New York, March 1995 [3] TIA/EIA-644-1996: “Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface Circuits”. [4] A. F. Benner “Fibre Channel: Gigabit communications and I/O for computer networks”, McGraw-Hill,1996. [5] IEEE Standard 1149.4-1999, “IEEE Standard for a Mixed Signal Test Bus”, IEEE Standards Board, New York, March 1999 [6] L. Whetsel, “Improved Boundary Scan Design”, Proc. International Test Conference, 1995, pp 851860 [7] H. Singh, G. Patankar and J. Beausang, “A Symbolic Simulation-based ANSI/IEEE Std 1149.1 Compliance Checker and BSDL Generator”, Proc. International Test Conference, 1997, pp 256-264 [8] B. Nadeau-Dostie, J.F. Cote, H. Hulvershorn and S. Pateras, “An Embedded Technique for At-Speed Interconnect Testing”, Proc. International Test Conference, 1999, pp 431-438 [9] K. P. Parker “The Boundary-Scan Handbook, second edition, Analog and Digital”, Kluwer Academic Publishers, 1998, , pp 251-253

We have introduced a new AC-JTAG technology. It allows testing of AC coupled nets in the boundary-scan environment. In addition, adopting this technology into a manufacturing board test process can significantly reduce board test cost. AC_EXTEST is a public instruction, which enables this technology. All the elements and protocols between devices have been described to help Paper 2.1 37
