an introduction to microprocessor 8085

AN INTRODUCTION TO MICROPROCESSOR 8085 By

Dr. D. K. Kaushik Principal, Manohar Memorial (P.G.) College, Fatehabad (Haryana) India

Dhanpat Rai Publishing co., New Delhi

AN INTRODUCTION TO MICROPROCESSOR 8085 Chapter 1

Evolution and History of Microprocessors

1.1 Introduction 1.2 Evolution/History of Microprocessors 1.3 Basic Microprocessor System 1.3.1 Address Bus 1.3.2 Data Bus 1.3.3 Control Bus 1.4 Brief Description of 8-Bit Microprocessor 8080A 1.5 Computer Programming Languages 1.5.1 Low-Level Programming Language 1.5.2 High-Level Programming Language

Chapter 2

SAP – I

2.1 2.2 2.3 2.4

Architecture of SAP – I Instruction Set of SAP-I Computer Programming of SAP-I Computer Working of SAP-I Computer 2.4.1 Fetch Cycle 2.4.2 Execution Cycle 2.5 Hardware Design of SAP-I Computer 2.5.1 Design of Program Counter 2.5.2 Memory Unit 2.5.3 Instruction Register 2.5.4 Controller-Sequencer 2.5.5 Accumulator 2.5.6 Adder-Subtractor 2.5.7 B-Register 2.5.8 Output Register

Chapter 3 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8

SAP – II

Architecture of SAP-II Computer Instruction Set of SAP-II Computers Machine Cycle and Instruction Cycle Addressing Modes Instruction Types Flags Assembly Language Programming Delay Calculations

Chapter 4

SAP – III

4.1 Programming Model of SAP-III Computer 4.2 Instruction Set of SAP-III Computer 4.2.1 Data Transfer Group 4.2.2 Arithmetic Group of Instructions 4.2.3 Logic Transfer Group 4.2.4 Branch Group

4.2.5 Stack and Input / Output Instructions 4.3 Time Delay Introduced by a Register Pair

Chapter 5

The 8085 Microprocessor

5.1 Architecture of 8085 Microprocessor 5.1.1 Register Section 5.1.2 Address Buffer and Address-Data Buffer 5.1.3 Arithmetic and Logical Unit (ALU) 5.1.4 Timing and Control Unit 5.1.5 Interrupt Control 5.2 Pin Description of 8085 5.3 Instruction Set of 8085 Microprocessor 5.4 Timing Diagram for 8085 Instructions 5.4.1 Timing Diagram of MOV reg, M 5.4.2 Timing Diagram of MOV M, reg 5.4.3 Timing Diagram of MVI reg, data 5.4.4 Timing Diagram of MOV reg2, reg1 5.4.5 Timing Diagram of MVI M, data 5.4.6 Timing Diagram of XCHG 5.4.7 Timing Diagram of LXI rp, dbyte 5.4.8 Timing Diagram of IN byte

Chapter 6

Programming of 8085

6.1 Simple Progams 6.2 Progams on code conversion 6.2.1 BCD to Binary Conversion 6.2.2 Binary to BCD (Unpacked) Conversion 6.2.3 Binary to ASCII Conversion 6.2.4 ASCII to Binary Conversion 6.3 Progams on addition and subtraction 6.4 Progams to find largest or smallest number 6.5 Progams to arrange a given series in ascending or descending order 6.6 Program on Multiplication 6.7 Program on 8-Bit Division 6.8 Miscellaneous Programs

Chapter 7

Interrupt Instructions of 8085

7.1 Methods of I/O Operations 7.1.1 Memory Mapped I/O 7.1.2 I/O Mapped I/O or Isolated I/O 7.2 Data Transfer Schemes 7.2.1 Programmed I/O Data Transfer 7.2.2 Interrupt Driven I/O Data Transfer 7.2.3 Direct Memory Access (DMA) Data Transfer 7.3 The 8085 Interrupts 7.4 Software Interrupts 7.5 Hardware Interrupts 7.6 Interrupt Control Circuit 7.7 Interrupt Instructions

7.8 Serial Input and Output Data Transfer

Chapter 8

Programmable Peripheral Interface (PPI) 8255A

8.1 8.2 8.3 8.4 8.5

Details of PPI IC 8255A Operational Modes of 8255A Control Word Format for 8255A Programming in Mode 0 Programming in Mode 1 (strobed Input/Output) 8.5.1 Input Control Signals in Mode 1 8.5.2 Output Control Signals in Mode 1 8.6 Programming in Mode 2 (Strobed Bidrectional Bus I/O) 8.7 Bit Set/Reset (BSR) Mode

Chapter 9

Programmable Interval Timer/Counter: 8253

9.1 INTEL Programmable Interval Timer 8253 9.2 Block Diagram of 8253 9.3 Logics for Counters 9.4 Control Word Format of 8253 9.5 Interfacing and programming of 8253 9.6 Programming of 8253 in Mode 0: Interrupt on Terminal Count 9.7 Programming of 8253 in Mode 1: Programmable One Shot 9.8 Programming of 8253 in Mode 2: Rate Generator 9.9 Programming of 8253 in mode 3: Square Wave Generator 9.10 Programming of 8253 in mode 4: Software Triggered Strobe

Chapter 10 Programmable Keyboard and Display Interface: 8279 10.1 10.2 10.3 10.4 10.5

INTEL Programmable Keyboard/Display Interface 8279 Block Diagram of 8279 Functional Description of 8279 Key Board San Scanned Keyboard 10.5.1 Two-key Lockout 10.5.2 N-key Rollover 10.6 Scanned Sensor Matrix 10.7 Strobed Input 10.8 Display Interface 10.9 Display Modes 10.9.1 Left Entry Mode (Type Writer Mode) 10.9.2 Right Entry Mode (Calculator Mode) 10.10 Programming of 8279 10.10.1 Keybaord/Display Mode Set 10.10.2 Program Clock 10.10.3 Read FIFO/Sensor RAM 10.10.4 Read Display RAM 10.10.5 Write Display RAM 10.10.6 Display Write Inhibit/Blanking 10.10.7 Clear 10.10.8 End Interrupt/Error Mode Set 10.11 Status Register (IN Operation)

10.12 Interfacing of 8279 with 8085

Chapter 11 Programmable Interrupt Controller: 8259 11.1 11.2 11.3 11.4 11.5 11.6 11.7 11.8

Programmable Interrupt Controller 8259 Block Diagram of 8259 Interfacing of 8259A with 8085A Vectoring Data Formats for 8259 Initialization of 8259 Initialization Command Words (ICWs) Operation Command Words (OCWs) Interrupt Modes of 8259A 11.8.1 Fully Nested Mode (FNM) 11.8.2 Rotating Priority Mode 11.8.3 Special Mask Mode 11.8.4 Polled Mode 11.9 Status Read Operation of 8259

Chapter 12 Direct Memory Access Controller: 8257 12.1 Block Diagram of 8257 12.1.1 DMA Channels 12.1.2 Data Bus Buffer 12.1.3 Read/ Write Logic 12.1.4 Control Logic 12.1.5 Mode Set Register 12.1.6 Status Word Register 12.2 Programming of 8257 12.3 DMA Interfacing Circuit

Chapter 13 Interfacing Data converters: A/D and D/A Converters 13.1

Digital to Analog Converter 13.1.1 Resistive Divider D/A converter 13.1.2 Binary Ladder D/A Converter 13.2 Performance Criteria for D/A Converter 13.3 D/A Converter IC 0808 13.4 Interfacing of D/A Converter 13.5 Microprocessor Compatible D/A Converter 13.6 Analog to Digital Converter 13.7 Simultaneous A/D Converter 13.8 Successive Approximation A/D Converter 13.9 Counter or Digital Ramp Type A/D Converter 13.10 Single Slope A/D Converter 13.11 Dual Slope A/D Converter 13.12 ADC 0808/0809 13.13 A/D Converter Using D/A Converter and Software

Chapter 14 Serial Communication and Programmable Communication Interface

14.1 14.2 14.3 14.4 14.5 14.6

Serial Data Communication Modem Serial Communication Standard Asynchronous Software Approach Programmable Communication Interface Block Diagram of 8251A 14.6.1 Read/Write Control Logic 14.6.2 Transmitter Section 14.6.3 Receiver Section 14.6.4 Modem Control 14.7 Interfacing of 8251A 14.8 Programming of 8251A 14.8.1 Initialization of 8251A in Asynchronous Mode 14.8.2 Initialization of 8251A in Synchronous Mode

Chapter 15 Applications of Microprocessor 15.1 15.2 15.3 15.4 15.5 15.6 15.7 15.8 15.9

Real Time Clock with On/Off Timer Microprocessor Based LED Dial Clock Design of Microprocessor Based Running light Microprocessor Based Automatic School bell system Microprocessor Based Traffic Light 15.5.1 Another Design of Microprocessor Based Traffic Light Microprocessor Based Stepper Motor Control Microprocessor Based Washing Machine Controller Microprocessor Based Water Level Controller Microprocessor Based Temperature Controller

Appendices

1 Evolution and History of Microprocessors To understand the working and programming of microprocessors, it is very necessary to know the details of evolution and history of microprocessors which will be discussed in this chapter. In the succeeding chapters of this book, the detailed discussion on the basics of microprocessors will be made. For the beginners it is very difficult to understand the operation of a digital computer as it contains large details, so efforts have been made to envisage the operation of a digital computer in step by step manner. 1.1 INTRODUCTION Microprocessor is a digital device on a chip which can fetch instructions from a memory, decode and execute them i.e. performs certain arithmetic and logical operations, accept data from input device, and send results to output devices. Therefore, a microprocessor interfaced with memory and Input/ Output devices forms a Microcomputer. Basically, there are five building blocks of a digital computer namely: Input Unit

Through this unit data and instructions are fed to the memory of the computer. The basic purpose of this unit is to read the data into the machine. The program from the memory is read into the machine along with the input data which are required to solve or compute the problem by the machine. The typical devices which are used for this purpose are keyboards, paper tape reader and toggle switches etc.

Memory Unit

The memory unit of a digital computer consists of devices which are capable of storing information. The memory of a computer is used for storing two distinct type of information such as data to be processed by the computer and program through which the result of the desired problem is obtained. Computer program and data are stored in the Memory Unit. This usually consists of chips of both ROMs (Read Only Memories) and RAMs (Random Access Memories) either bipolar or MOS.

Arithmetic and Logical Unit (ALU)

This unit is used for performing arithmetic operations such as Addition, Subtraction, Multiplications, division and other logical operations on the data. The control unit guides ALU which of the operations are to be performed. The sequence of the instructions is controlled by the control unit.

Control Unit

The control unit performs the most important function in a computer. It controls all other units and also controls the flow of data from one unit to another for performing computations. It also sequences the operations. It instructs all the units to perform the task in a particular sequence with the help of clock pulses.

Output Unit

After processing of the data in the Arithmetic and Logical Unit, the results are displayed to the output world through this unit. The CRTs (Cathode Ray Tubes), LEDs (Light Emitting Diodes) and Printer etc. form the output unit.

In a computer system ALU and Control Unit are combined in one unit called Central Processing Unit (CPU). The block diagram of a computer is shown in figure 1.1.

Fig. 1.1 2

The Central Processing Unit is analogous to the human brain as all the decisions as per the instructions are made by CPU. All other parts are also controlled by this unit. A microprocessor is an integrated circuit designed for use as Central Processing Unit of a computer. The CPU is the primary and central player in communicating with devices such as memory, input and output. However, the timing of communication process is controlled by the group of circuits called control unit. The term ‘Microprocessor’ came into existence, in 1971, when the Intel Corporation of America, developed the first microprocessor (INTEL-4004) which is a 4bit microprocessor ( µ p). A microprocessor is a programmable digital electronic component that incorporates the functions of a Central Processing Unit (CPU) on single semi-conducting Integrated Circuits (ICs). As such, a system with microprocessor as an integral part is termed as a microprocessor based system. When a computer is microprocessor based, it is called a microcomputer ( µ c). A microprocessor is specified by its ‘Word Size’, e.g. 4-bit, 8-bit, 16-bit etc. By the term ‘word size” means the number of bits of data that is processed by the microprocessor as a unit. For example, an 8-bit microprocessor performs various operations on 8-bit data. It also specifies the width of the data bus. As discussed above, a microcomputer consists of input/ output devices, and memory, in addition to microprocessor which acts its CPU. In fact CPU is commonly referred to microprocessor ( µ p). Microprocessors made possible the advent of the microcomputer in the mid-1970s. Before this period, electronic CPUs were typically made from bulky discrete switching devices. Later on small-scale integrated circuits were used to design the CPUs. By integrating the processor onto one or very few large-scale integrated circuit package (containing the equivalent of thousands or millions of discrete transistors), the cost of processor was greatly reduced. The evolution of microprocessors has been known to follow Moore’s law when it comes to steadily increasing performance over the years. This law suggests that the complexity of an integrated circuit, with respect to minimum component cost, doubles in every 18 months. This dictum has generally proven true since the early 1970’s. This lead to the dominance of microprocessors over every other form of computer; every system from the largest mainframes to the smallest hand held computers now uses a microprocessor as its core. The microprocessor based systems play significant role in the every functioning of industrialized societies. The microprocessor can be viewed as a programmable logic device that can be used to control processes or to turn on/off devices. So the microprocessor can be viewed as a data processing unit or a computing unit of a computer. The microprocessor is a programmable integrated device that has computing and decision making capability similar to that of the central processing unit (CPU) of a computer. Nowadays, the microprocessor is being used in a wide range of products called microprocessor based products or systems. The microprocessor communicates and operates in the binary numbers 0 and 1, called bits. Each microprocessor has a fixed set 3

of instructions in the form of binary pattern called a machine language. However, it is difficult for human beings to communicate in the language of 0s and 1s. Therefore, the binary instructions are given abbreviated names, called mnemonics, which form the assembly language for a given microprocessor. 1.2 EVOLUTION/HISTORY OF MICROPROCESSORS An English Mathematician Charles Babbage was the first man to propose the basic principle of modern computers from 1792-1871. He gave the concept of a programmable machine having computer similar to modern digital computers. He is, therefore, known Father of Modern Computers. In 1930s successful general purpose mechanical computer was developed. Before this, mechanical calculators were built to perform simple mathematical operations such as addition, subtraction, multiplication and division. Improvement continued and in 1944 Prof. H. Aiken developed a first practical electro-mechanical digital computer in collaboration with IBM. This computer was known as HAWARD MARK-I. It was in large size (51’ long and 8’high) and weighing about 2 tons. The punch cards ware used to input the data in the computer. During the development of the HAWARD MARK-I Computer, Konard Joos of Germany was busy in developing another computer based on 0’s and 1’s rather than decimal numbers. So he developed a computer making use of relays (on-off for 1’s and 0’s) during 1936-44. Joos also developed a language for the computer. The giant machines during 1940-50 were thus designed using relays and vacuum tubes. In 1945, John J. Mauchy and J. Presper Eckert of University of Pennsylvania developed first electronic computer ENIAC (Electronic Numerical Integrator and Calculator). It was too huge weighing 30 tons and occupied an area 30' X 50' and made use of 18000 vacuum tubes, more than 30000 resistors, 10000 capacitors and 6000 switches. It took 200 µ S for addition, and 3mS for 10-digit multiplication. It had separate memory for program and data. It used 20 electronic accumulators for memory. Each accumulator stored signed 10-digit decimal number. A number of computers using vacuum tubes were developed during 1940-55. The main drawback with the ENIAC was the life of the vacuum tube components, which required the frequent maintenance. The invention of semiconductor transistors in 1948 at Bell Laboratories leads further development of computers. The use of semiconductor transistors could not only reduced the size of computers but also increased its capability to a great extent. This leads reduction in cost. Further, the invention of Integrated circuits in 1958 by Jack Kilby of Texas Instrument made a revolution in electronic circuitry. The use of ICs made the size of computers very small and became more versatile in functions. Finally, the advent of IC technology leads to the development of first microprocessor (INTEL 4004) in 1971 at Intel Corporation by an engineer Marcian E. Hoff. It was a 4-bit microprocessor – a programmable controller on a chip. This was called the first generation microprocessor. It was fabricated using P-channel MOSFET technology and had an instruction set of 45 different instructions. It addressed 4096 four-bit wide memory locations. The P-channel MOSFET technology gave low cost but low speed not compatible with TTL (Transistor-

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Transistor Logic) technology. It has to use at least 30 ICs to form a system. As INTEL 4004 had very small number of instructions, it could be used in limited applications such as early video games and small microprocessor-based controllers. Seeing microprocessor as a viable product, Intel Corporation released the 8008 microprocessor – an extended 8 bit version of the 4004 microprocessor in 1972. Soon a variety of microprocessors was released by different manufactures. A few first generation microprocessors are listed in table 1.1. Table 1.1

4-bit Microprocessors

8-bit Microprocessors

INTEL 4004 INTEL 4040 FAIRCHILD PPS-25 ROCKWELL PPS-4 NATIONAL IMP-4

INTEL 8008 NATIONAL IMP-8 ROCKWELL PPS-8 AMI 7200 MOSTEK 5065

Second generation microprocessors appeared in 1973 and used NMOStechnology which offered faster speed, higher density and still better reliability. In the year 1974, an 8-bit microprocessor INTEL 8080 was developed using NMOS technology. It requires only two additional devices to design a functional CPU. It is much faster than 8008 and has more instructions than 8008 that facilitates the programming. The 8080 was compatible with TTL, whereas the 8008 was not directly compatible. The 8080 microprocessor could also address four times more memory (64K bytes) than the 8008 microprocessor (16K bytes). INTEL Corporation in 1977 developed another 8-bit microprocessor 8085 which was proved to be a better version than 8080. The execution time of two 8-bit numbers is 2.0 µ S for 8085 whereas it is 1.3 µ S for 8080. The main advantages of the 8085 were its internal clock generator, internal system controller, and higher clock frequency. Some of the important second generation microprocessors are given in table 1.2. Table 1.2

8-bit Microprocessors

12-bit Microprocessors

INTEL 8080 INTEL 8085 FAIRCHILD F8 MOTOROLA M6800 ZILOG Z-80 SIGNETICS 2650

INTERSIL 6100 TOSHIBA TLCS-12

The advantages of second generation microprocessor are given below:

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(i) (ii) (iii) (iv) (v) (vi) (vii) (viii)

Larger chip size (170 X 200 mils), 40 pins, More number of on-chip decoded timing signals, Ability to address larger memory space, Ability to address more I/O Ports, More powerful instruction set, Faster operation, Better Interrupt handling capabilities.

Third generation microprocessors were introduced in 1978. These were 16-bit microprocessors, designed using HMOS (High Density MOS) technology. These microprocessors offered better speed and higher packing density than NMOS. Some important third generation microprocessors are given in table 1.3. Table 1.3

16-bit Microprocessors INTEL 8086 INTEL 8088 INTEL 80186 INTEL 80286

MOTOROLA-68000 MOTOROLA-68010 NATIONAL NS-16016 TEXAS INSTRUMENTTMS-99000

INTERSIL 6100 TOSHIBA TLCS-12 ZILOG Z-8000

In 1978, 16-bit INTEL 8086 microprocessor of 64 pins was introduced and in 1979 other 16-bit microprocessor 8088 was developed. In addition to the other performances, these µP s contain multiply/divide/arithmetic hardware. The memory addressing capabilities has been increased to very large i.e., 1MB to 16MB through a variety of flexible and powerful addressing mode. The other characteristics of third generation are given below:

(i) (ii) (iii) (iv) (v) (vi) (vii) (viii) (ix) (x)

These microprocessors were 40/48/64 pins, High speed and very strong processing capability, Easier to program, Allow for dynamically re-locatable programs, Size of internal registers were 8/16/32 bits, These µP s had the multiply/divide/arithmetic hardware, Physical memory space was from 1 to 16 Mega-bytes (MB), Flexible 10 port addresses, More powerful interrupt and hardware capabilities, Segmented address and virtual memory features.

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Fourth generation microprocessors of 32 bits were introduced in the form of 80386 in 1985 and 80486 in 1989. The instruction set of the 80386 microprocessor was upward compatible with the earlier 8086, 8088 and 80286 microprocessors. However, the 80486 is an improved version of the 80386 microprocessor. The 80386 executes many instructions in 2 clock cycles while the 80486 executes in one clock cycle. These microprocessors are of low power version of HMOS technology. Some important fourth generation microprocessors are given in table 1.4. Table 1.4

32-bit Microprocessors INTEL 80386 INTEL 80486 NATIONAL NS16022 MOTOROLA MC 88100

MOTOROLA M-68020 MOTOROLA M-68030 BELLMAC-32

Fifth generation microprocessor was introduced by INTEL Corporation in 1993 in the form of PENTIUM with 64 data bus. The Pentium was similar to the 80386 and 80486 microprocessor. The two introductory versions of the Pentium operated with a clock frequency of 60 MHz and 66 MHz and a speed of 110 MIPS (Million Instructions Per Second). With better and more advanced technologies, the speed of µPs has increased tremendously. The old 8085 of 1977 executed 0.5 million instruction/sec. (0.5 MIPS), while the 80486 executes 54 million instruction per sec. The Pentium Pro Processor is the Sixth generation microprocessor introduced in 1995 having better architecture but more in size. The Pentium Pro Microprocessor contains 21 million transistors, 3 integer units as well as a floating unit to increase the performance of most software. The basic clock frequency is 150 MHz and 166 MHz. 1.3

BASIC MICROPROCESSOR SYSTEM

The Microprocessor alone does not serve any useful purpose unless it is supported by memory and I/O ports. The combination of memory and I/O ports with microprocessor is known as microprocessor based system. As discussed above the microprocessor which is the central processing unit executes the program stored in the memory and transfer data to and from the outside world through I/O ports. The microprocessor is interconnected with memory and I/O ports by the data bus, the Address bus and the control bus. A bus is basically a communication link between the processing unit and the peripheral devices as shown in figure 1.2. 1.3.1 Address Bus

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The address bus is unidirectional and is to be used by the CPU to send out address of the memory location to be accessed. It is also used by the CPU to select a particular input or output port. It may consist of 8, 12, 16, 20 or even more number of parallel lines. Number of bits in the address bus determines the minimum number of bytes of data in the memory that can be accessed. A 16-bit address bus for instance can access 216 bytes of data. It is labeled as A0…………An-1, where n is the width of bits of the address bus.

Fig. 1.2 1.3.2 Data Bus Data bus is bidirectional, that is, data flow occurs both to and from CPU and peripherals. There is an internal data bus which may not be of the same width as the external data bus by that connects the I/O and memory. A microprocessor is characterized by the width of its data bus. All those microprocessors having internal and external data buses of different widths are characterized either by their internal or external data buses. The size of the internal data bus determines the largest number that can be processed by a microprocessor, for instance, having a 16-bit internal data bus is 65536 (64K). The bus is labeled as: D0 ………………Dn-1, where n is the data bus width in bits 1.3.3 Control Bus Control bus contains a number of individual lines carrying synchronizing signals. The control bus sends out control signal to memory, I/O ports and other peripheral devices to ensure proper operation. It carries control signals like MEMORY READ, MEMORY WRITE, READ INPUT PORT, WRITE OUTPUT PORT, HOLD, INTERRUPT etc. For instance, if it is desired to read the contents of a particular memory location, the CPU first sends out address of that very location on the address bus and a ‘Memory Read’ control signal on the control bus. The memory responds by outputting data stored in the addressed memory location on the data bus.

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This book will confine the detailed study of 8085 microprocessor because it is most commonly used microprocessor. However, evolution of microprocessors has been discussed in this chapter, in order to have the knowledge microprocessors introduced so far. Before discussing the details of the 8085, brief discussion of 8-bit microprocessor 8080 is given here. 1.4 BRIEF DESCRIPTION OF 8-BIT MICROPROCESSOR 8080A Intel 8080 microprocessor is a successor to the Intel 8008 CPU. The Intel 8080/8080A was not object-code compatible with the 8008, but it was source-code compatible with it. The 8080 CPU had the same interrupt processing logic as the 8008, which made porting of old applications easier. Maximum memory size on the Intel 8080 was increased from 16 KB to 64 KB. The number of I/O ports was increased to 256. In addition to all 8008 instructions and addressing modes the 8080 processor included many new instructions and direct addressing mode. The 8080 also included new Stack Pointer (SP) register. The SP was used to specify position of external stack in CPU memory, and the stack could grow as large as the size of memory. Thus, the CPU was no longer limited to 7-level internal stack, like the 8008 did. The Intel 8080, an 8-bit microprocessor was very popular. Fig. 1.2 shows the shape of the microprocessor and Fig. 1.3 shows the pin out configuration of the 8080A microprocessor. Its salient features include: a) b) c) d) e)

A two-phase clock input Q1 and Q2 16-bit address bus 8-bit data bus Power supply input of +5V, -5V and +12V required. The 8080A places the status of the operation on the data bus during the earlier part of the cycle and places data on the bus during later part of cycle.

Fig. 1.2

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Fig. 1.3 Program memory

Pprogram can be located anywhere in memory. Jump, branch and call instructions use 16-bit addresses, i.e. they can be used to jump/branch anywhere within 64 KB. All jump/branch instructions use absolute addressing.

Data memory

The processor always uses 16-bit addresses so that data can be placed anywhere.

Stack memory

It is limited only by the size of memory. Stack grows downward.

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Interrupts

The processor supports maskable interrupts. When an interrupt occurs the processor fetches from the bus one instruction, usually one of these instructions:

•

One of the 8 RST instructions (RST0 - RST7). The processor saves current program counter into stack and branches to memory location N * 8 (where N is a 3-bit number from 0 to 7 supplied with the RST instruction).

•

CALL instruction (3 byte instruction). The processor calls the subroutine, address of which is specified in the second and third bytes of the instruction.

The interrupt can be enabled or disabled using EI (Enable Interrupts) and DI (Disable Interrupts) instructions. I/O ports 256 Input ports 256 Output ports Registers Accumulator or A register is an 8-bit register used for arithmetic, logic, I/O and load/store operations. Flag is an 8-bit register contains the following five, 1-bit flags: •

Sign flag - set if the most significant bit of the result is set.

•

Zero - set if the result is zero. Auxiliary carry flag - set if there was a carry out from bit 3 to bit 4 of the result.

• • •

Parity flag - set if the parity (the number of set bits in the result) is even. Carry flag - set if there was a carry during addition, or borrow during subtraction/ comparison.

General registers: •

8-bit B and 8-bit C registers can be used as one 16-bit BC register pair. When

•

used as a pair the C register contains low-order byte. Some instructions may use BC register as a data pointer. 8-bit D and 8-bit E registers can be used as one 16-bit DE register pair. When used as a pair the E register contains low-order byte. Some instructions may use DE register as a data pointer.

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•

8-bit H and 8-bit L registers can be used as one 16-bit HL register pair. When used as a pair the L register contains low-order byte. HL register usually contains a data pointer used to reference memory addresses.

Stack pointer

It is a 16 bit register. This register is always incremented/ decremented by 2.

Program counter

It is also a 16-bit register. Instruction Set

8080 instruction set consists of the following instructions: • • •

Data moving instructions. Arithmetic - add, subtract, increment and decrement. Logic - AND, OR, XOR and rotate.

•

Control transfer – conditional, unconditional, call subroutine, return from subroutine and restarts.

•

Input/Output instructions. Other – setting/clearing flag bits, enabling/disabling interrupts, stack operations,

•

etc. 1.5

COMPUTER PROGRAMMING LANGUAGES

In order for computers to accept commands from human and perform tasks vital to productivity, a means of communication must exist. Programming languages provide this necessary link between man and machine. Because they are quite simple compared to human language, rarely containing more than few hundred distinct words, programming languages must contain very specific instructions. There are more than 2,000 different programming languages in existence, although most programs are written in one of several popular languages, like BASIC, COBOL, C++, or Java. Programming languages have different strengths and weaknesses. Depending on the kind of program being written, the computer will run on the experience of the programmer, and the way in which the program will be used, the suitability of one programming language over another will vary. One can categorize computer language as low Level and high level programming languages which are being discussed in the subsequent subsections. 1.5.1

Low-Level Programming Language

A low-level programming language is a language that provides little or no abstraction from a computer's instruction set architecture. The word "low" refers to the small or nonexistent amount of abstraction between the language and machine language; because of this, low-level languages are sometimes described as being "close to the

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hardware." A low-level language does not need a compiler or interpreter to run; the processor for which the language was written is able to run the code without using either of these. By comparison, a high-level programming language isolates the execution semantics of computer architecture from the specification of the program, making the process of developing a program simpler and more understandable. Low-level programming languages are sometimes divided into two categories: first generation, and second generation programming languages. First Generation Programming Language The First-Generation Programming Language (1GL) is machine code or machine language. Machine language is a language which is directly understood by a computer. It is also called binary language as it is based on 0s or 1s. Any instruction in machine language is represented in terms of 0’s and 1’s, even the memory addresses are given in binary mode. Programs in machine language are very difficult to read and understand as binary codes of each command can not easily be remembered. So it is very difficult and complicated to write the computer program in machine language. The experienced programmer can only work in machine language that too after having the good knowledge of machine hardware. Programs written in machine language cannot easily be understood by other programmers. Currently, programmers almost never write programs directly in machine code, because as discussed above it not only require attention to numerous details which a high-level language would handle automatically, but it also requires memorizing or looking up numerical codes for every instruction that is used. Second Generation Programming Language The Second-Generation Programming Language (2GL) is assembly language. Assembly language was first developed in the 1950s and it is different for different microprocessors. It was the first step to improve the computer programming. For writing the programs in assembly language it is necessary that the programmers should have the knowledge of machine hardware. The assembly language eliminated much of the errorprone and time-consuming first-generation programming needed with the earliest computers, freeing the programmer from tedious or boring jobs such as remembering numeric codes and calculating memory addresses. The assembly language was once widely used for all sorts of programming. However, by the 1980s (1990s on small computers), the use of assembly languages had largely been supplanted by high-level languages, in the search for improved programming productivity. Assembly languages are basically a family of low-level languages for programming computers, microprocessors, microcontrollers etc. They implement a symbolic representation of the numeric machine codes and other constants needed to program a particular CPU architecture. This representation is usually defined by the hardware manufacturer, and is based on abbreviations (called mnemonics) that help the

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programmer remember individual instructions, registers, etc. An assembly language is thus specific to certain physical or virtual computer architecture. Instructions (statements) in assembly language are generally very simple, unlike those in high-level languages. Generally, an opcode is a symbolic name for a single executable machine language instruction, and there is at least one opcode mnemonic defined for each machine language instruction. Each instruction typically consists of an operation or opcode plus zero or more operands. Most instructions refer to a single value, or a pair of values. Operands can either be immediate (typically one byte values, coded in the instruction itself) or the addresses of data located elsewhere in storage. A typical assembly language statement of 8080A or 8085 microprocessor written by the programmer is given below, which is divided in to four fields namely, Label, Mnemonics or Operation code (Opcode), Operand and comments. Label

Mnemonics

Operand

START:

LXI H,

2500 H

Commnets ; Initialize H-L register pair

A label for an instruction is optional, but it is very essential for specifying jump locations. Similarly, comments are also optional but it is required for good documentation. The four fields of assembly language statements shown above are separated by the following delimiters: Delimiters

Placement

Colon (:)

A colon is placed after the Label. Label is optional.

Space ( )

Space is left between an opcode and operand.

Comma (,)

A comma is placed between two operands.

Semicolon (;)

Semicolon is placed between the comments.

The program written in assembly language is converted to machine language manually. For writing the program in machine language, the starting address, where the program is to be stored should be known. Now the op code of the instruction is to be written in first location (starting address) and in the consecutive memory locations data /address of the operand is written. While storing the address in the memory locations, lower byte of he address is stored first then the upper byte. A utility program called an assembler is used to translate assembly language statements into the target computer's machine code. The assembler performs a more or less isomorphic translation (a one-to-one mapping) from mnemonic statements into machine instructions and data. The reverse process that is conversion of machine language to the assembly language is done by deassembler.

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For software development for a microprocessor/ microcomputer (written in assembly language in large number of instructions), it is absolutely essential to use an assembler. In fact assembler translates mnemonics into binary code with speed and accuracy; thus eliminating human error in looking for the opcodes. Other advantages of using the assembler for the software development are as follows: • • •

1.5.2

It assigns appropriate values to the symbols used in a program. This facilitates specifying jump locations. The assembler checks syntax errors, such as wrong labels and expressions, and provides error messages. However it cannot check logic errors in a program. It is easy to insert or delete instructions in a program; the assembler can reassemble the entire program quickly with new memory locations and modified addresses fro jump locations. This avoids rewriting the program manually.

High-Level Programming Language

The machine language and assembly languages discussed above are the first and second generation programming languages which fall in the category of low level languages. These languages require deep knowledge of computer hardware. The high level computer languages developed around 1960s are machine independent i.e. computer hardware is not necessary to know for the programmers. In high level languages one has to know only the instructions in English word and logic of the problem irrespective of the types of computer being used. For the computer programming prepared in high level language, only the use of English alphabets and mathematical systems like +, -, /, * etc. are made. In fact high level language is more close to user and is easy to read and understand. The high level languages are called procedural language and are designed to solve general and specific problems. The term "high-level language" does not imply that the language is superior to low-level programming languages - in fact high level refers to the higher level of abstraction from machine language. They have no opcodes that can directly compile the language into machine code, unlike low-level assembly language. In high level languages the words in English are converted into binary language of different microprocessors with the help of a program called Interpreter or Complier. The compiler or interpreter accepts English like statements as the input called Source code. The source codes are translated into machine language compatible with the microprocessor being used in the machine. The translation in the machine language from the source code is called the object code. Figure 1.4 shows the block diagram for translation of high level language program into machine code. Each microprocessor needs its own compiler or an interpreter for each high level language.

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Fig. 1.4 The difference between a compiler and an interpreter is that the compiler reads the entire program first and then generates the object code; where as the interpreter reads one instruction at a time and produces its object code which is executed at the same time before reading the next instruction. The high level programming language developed so far may be categorized into third, fourth and fifth generation programming languages whose brief discussion is given below. Third Generation Programming Language A third-generation programming language (3GL) is a refinement of a secondgeneration programming language. Whereas a second generation language is more aimed to fix logical structure to the language, a third generation language aims to refine the usability of the language in such a way to make it more user friendly. A third generation language improves over a second generation language by having more refinement on the usability of the language itself from the perspective of the user. Languages like ALGOL, COBOL, FORTRAN IV etc. are examples of this generation and were considered as high level languages. Most of these languages had compilers and the advantage of this was speed. Independence was another factor as these languages were machine independent and could run on different machines. FORTRAN (FORmula TRANslating) and COBOL (COmputer Business Oriented Language) were the first high-level programming languages to make an impact on the field of computer science. Along with assembly language, these two high-level languages have influenced the development of many modern programming languages, including Java, C++, and BASIC. FORTRAN is well suited for math, science, and engineering programs because of its ability to perform numeric computations. The language was developed in New York by IBM's John Backus. FORTRAN was known as user’s friendly, because it was easy to learn in a short period of time and required no previous computer knowledge. It eliminated the need for engineers, scientists, and other users to rely on assembly programmers in order to communicate with computers. Although FORTRAN is often referred to as a language of the past, computer science students were still taught the language in the early 2000s for historical reasons, and because FORTRAN code still exists in some applications.

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COBOL was another high level and third generation programming language well suited for creating business applications. COBOL's strength is in processing data, and in its simplicity. Other languages like BASIC, C, C++, C#, Pascal, and Java are also thirdgeneration languages. Fourth-Generation Programming Language A fourth-generation programming languages (4GL) (1970s-1990) are the programming language designed with a specific purpose in mind, such as the development of commercial business software. In the evolution of computing, the fourth generation language followed the third generation language in an upward trend toward higher abstraction and statement power. The fourth generation language was followed by efforts to define and use a fifth generation language (5GL). Basically the fourth generation languages are languages that consist of statements similar to statements in a human language. Fourth generation languages are commonly used in database programming and scripts. The commonly used fourth generation languages are FoxPro , SQL , MATLAB etc. Fifth-Generation Programming Language A fifth-generation programming language (5GL) is a programming language based around solving problems using constraints given to the program, rather than using an algorithm written by a programmer. Most constraint-based and logic programming languages and some declarative languages are fifth-generation languages. While fourth-generation programming languages are designed to build specific programs, fifth-generation languages are designed to make the computer solve a given problem without the programmer. This way, the programmer only needs to worry about what problems need to be solved and what conditions need to be met, without worrying about how to implement a routine or algorithm to solve them. Fifth-generation languages are used mainly in artificial intelligence research. Prolog, OPS5, Visual Basic, and Mercury etc. are examples of fifth-generation languages. Problems 1.1 1.2 1.3 1.4 1.5

Draw the block diagram of a general computer and discuss in detail the five blocks of a digital computer. Discuss History and Evolution of Microprocessor. What is microprocessor? What is the difference between a microprocessor and a microcomputer? What is the difference between the 4-bit microprocessor and 8-bit microprocessor? Name the main 8-bit microprocessors. Give the brief description of 8-bit microprocessor 8080A.

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1.6 1.7 1.8 1.9 1.10 1.11 1.12

Discuss basic microprocessor system with the help of block diagram. What are low level computer programming languages? Discuss them. Discuss first generation computer programming languages. Discuss second generation computer programming languages. Write short note on high level computer programming languages. What is the difference between assembly language and machine language? Mention the brief description of Assembly Language. What are the advantages of assembler?

________

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2 SAP – I For the beginners it is very difficult to understand the operation of a digital computer as it contains large details. To understand the step by step operation of a digital computer, the concept of Simple as Possible (SAP) computer has been introduced. Simple as possible computer, a conceptual computer will be discussed in three stages namely SAP – I, SAP – II and SAP – III computers. All the necessary details for the operation of digital computers will be discussed in three stages. After the study of these three stages of SAP computers, we will be in a position to understand clearly the fundamentals of microprocessor 8085 including the architecture, programming and interfacing devices. In this chapter the organization, programming and circuits of SAP – I computer will be discussed; the succeeding chapters will have the details of other stages of SAP computers. 2.1 ARCHITECTURE OF SAP - I SAP – I, a conceptual computer is an 8-bit computer, as it can process the data of 8-bits. Further it is a simple computer and is considered for the basic understanding of the operation of digital computers, so it is assumed that it can store only 16 words (each word being 8 bit long). The length of the memory address register will of 4 bits since 2 4 = 16 (16 is the total capacity of the memory unit). The address of 16 memory locations of memory address register (MAR) will be 0000 to 1111 i.e.

Memory locations (in Hexadecimal) 0H 1H 2H 3H 4H 5H 6H 7H

Address

Memory locations (in Hexadecimal)

Address

0000 8H 1000 0001 9H 1001 0010 AH 1010 0011 BH 1011 0100 CH 1100 0101 DH 1101 0110 EH 1110 0111 FH 1111 The basic architecture of this computer is shown in figure 2.1. It contains an 8-bit W-Bus (Wire Bus), which is used for data transfer to various 8-bit registers. A Bus is a group of conducting wires. In this figure, all register outputs connected to W-Bus are three-state which allows ordinary transfer of data. Remaining other register outputs continuously drive the boxes they are connected to. A brief discussion of each block is given below:

Program Counter First block of the SAP –I computers is the Program Counter (PC). It is basically the part of the control unit, its function is to send to the memory the address of the next instruction to be fetched and executed. Program counter is also called as the pointer as it is like someone pointing a finger at a list of instructions, saying do this first and do this next and so on. In the beginning, program and data is stored in the memory through the input unit. A 4-bit binary address (0000 to 1111) is sufficient to address a word in the memory. The first instruction of the program is stored in the memory location 0000, second instruction at 0001 location, and the third instruction at 0010 location and so on. When the computer starts executing the program, the program counter is reset. The program counter is then incremented by one to get the next address of the memory location. After the first instruction is fetched and executed, the PC sends address 0001 to memory. Again the PC is incremented by one. After execution of second instruction, PC sends the next address to memory and so on.

Fig. 2.1 Input and MAR The second block of SAP –I computer is Input and Memory Address Register (MAR). It includes 4 bit address register and 8 bit data register. These registers are basically the parts of input unit. The input and MAR sends 4 bit address and 8 bit data to memory unit, this unit helps in storing the instructions and data to the memory, before the computer run starts. This unit includes a matrix of switches (micro-switches) for address 20

and data. In this SAP-I computer, the switch matrix allows to send 4 address bits and 8 data bits to memory. The relevant switch is opened or closed to program the memory. This can be done by providing switches on the front panel of the computer. The memory address register is also the part of SAP-I memory. When SAP-I computer starts executing the program, the address in the PC is latched into the MAR. The MAR will then send this address to RAM for the read operation. Memory Unit It is 16x8 static TTL RAM (Random Access Memory) i.e. it is capable of storing 16 words (total capacity is only of 16 words) and each word is of 8 bit long. It stores the program and data before the execution of program; and during the execution it sends the stored instruction and data to the W-bus for further transfer to other registers as soon as address is received by it from MAR. Instruction Register The instruction register of SAP-I computer is the part of control unit. As already discussed during the execution of program, the content of addressed memory location is placed on the W-Bus. At the same time, during the next positive edge of the clock pulse this instruction (content of memory location) is loaded into the Instruction Register. The instruction register now splits the content of the instruction (8-bit) into two nibbles (one nibble is of 4-bit long). Instruction register sends the upper nibble directly to Controller/Sequencer, the lower nibble is, however, placed by the Instruction register to W-Bus for the read operation whenever needed. Controller Sequencer The block controller sequencer is basically control unit. This is a key unit for the automatic operation of this SAP-I computer. It generates a control word of 12 bits as given below: CON = C P E P L M C E L1 E1 L A E A SU E U L B LO The symbolic notations of the control signal (CON) used in the computer are given in table 2.1. Table 2.1 Notation

Interpretation

CP

PC is incremented, when CP is high.

EP

Enable PC, when E P is high.

LM

Loads MAR from W-Bus, when L M is low.

CE

Loads RAM, when C E is low.

L1

Loads instruction register, when it is low.

E1

Enable instruction register, when it is low.

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LA

Loads the accumulator, when it is low.

EA

Enable the accumulator, when it is high.

SU

Enables subtraction, when if is high and enables addition when it is low.

EU

Enable Adder/Subtrator to send the answer to W-Bus, when it is high.

LB

Loads the register B, when it is low.

LO

Loads the output register, when it is low.

Accumulator The accumulator or register A is an 8-bit register and it is also called the buffer register. When L A is low, the data from the W-Bus is loaded to the accumulator at the positive edge of the clock pulse. This data also directly goes to the Adder/Subtractor. The answer of Adder/Subtractor may also be loaded to the accumulator via W-Bus. The answer or the data stored in Accumulator will go to W-Bus when E A is high. Adder-Subtractor The adder-Subtractor is the part of Arithmetic and Logical Unit (ALU) of the computer. This block can add the content of B-register to accumulator content when SU is low. Similarly, this block can subtract the content of B-register from the accumulator content when SU is high. The answer of addition or subtraction may be loaded to W-Bus

when E U is high. The subtraction in the block adder/subtrator is done using 2’s complement method. Register B The register B is the part of Arithmetic and Logical Unit (ALU) of the computer. It is another buffer register of 8 bit long. The content to be added to the accumulator or subtracted from the accumulator, is loaded to B-register from W-Bus when LB is low. Output Register O The output register O is the part of the output unit of the SAP-I computer. At the end of the execution of program the answer available at the accumulator may be transferred to output register O, at the positive edge of the clock pulse and when LO is low, this register is also called the output port. Binary Display (BD) The last block of SAP-I computer is Binary Display (BD), which is the part of output unit. This display unit contains 8 LEDs (Light Emitting Diodes) connected to 8 bit output port through 8 flip-flops. When the data or answer is available at the output port, the same is transferred to LEDs indicating the answer is in binary form. 2.2 INSTRUCTION SET OF SAP-I COMPUTER

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The instruction set is a set of instructions that can be executed by the computer. The computer programming is done using these instructions. Any problem to be solved on the computer is to be written in the form of a program. The SAP-I computer has got only five instructions as it is a very simple computer. These instructions are given in table 2.2. The instructions are written in abbreviated form or short form. These short forms of the instructions are known as Mnemonics (Memory aids). In fact the instructions in short form can easily be remembered by the programmers or users. Further, every instruction is stored in computer in coded form known as Op Code (Operation Code). The Op codes for the instructions of SAP-I computer given in table 2.2 are shown in binary form. From the above discussion it is clear that mnemonics is the short form of instruction for the user’s remembrance and op code is the coded form of the instruction in machine language. Table 2.2 Mnemonic LDA

Op Code (Binary) 0000

ADD

0001

SUB

0010

OUT

1110

Operation It loads the accumulator the content from addressed location. It adds the content of the memory location to the accumulator content. It subtracts the content of the memory location from the accumulator content. It transfers the accumulator content to the output port. It stops the computer for further execution.

HLT 1111 LDA Instruction The LDA instruction loads the content from the specified memory location to the accumulator. There is always an operand with this instruction. The operand with the LDA instruction is the address of the memory location whose content is to be transferred to the accumulator. For example LDA 9 H will load the accumulator, the content from the memory location 9 H. The alphabet H denotes hexadecimal number, as the op code for LDA is 0000 and binary equivalent of 9H is 1001. The machine language for this instruction is 0000 1001. It must be remembered that LDA 9 H is known as the assembly language of the instruction and 0000 1001 (09H) is known as machine language of the instruction. If the memory location 9H has the content 0001 0010 (12 H), then after execution of the instruction in SAP-I computer, it will load the content 0001 0010 to the accumulator, i.e. or A ← 00010010 A ← 12 H ADD Instruction ADD instruction adds the content of memory location to the accumulator content. The address of the memory location is the operand of this instruction. For example ADD E H adds the content of memory location E H (1110) to the accumulator content.

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If before the execution of this instruction accumulator A is having data say 00010101, and 0000 0001 is already stored in memory location E H, then after execution of he instruction ADD E H the accumulator is loaded with the data 0001 0110, as 0000 10101 + 0000 0001 = 0001 0110. i.e. or A ← 00010110 A ← 16 H SUB Instruction SUB instruction subtracts the content of the memory location from the accumulator content. The operand for this instruction is the address of the memory location. For example SUB C H subtracts the content of memory location C H (1100) from the accumulator content. If before the execution of this instruction accumulator A is having the content say 0000 0011 and the content in memory location C H is 0000 0010, then after the execution of this instruction, the accumulator A will have the answer as: 0000 0011 – 0000 0010 = 0000 0001 or So A ← 00000001 A ← 01 H OUT Instruction The SAP-I instructions LDA, ADD and SUB discussed above are the memory reference instructions since the address of the memory location is the operand for these instructions. OUT instruction is not the memory reference instruction, as this instruction is itself complete and operand is not needed. The OUT instruction is used to transfer the accumulator content (answer after processing) to the output port. HLT Instruction HLT instruction is also not memory reference instruction, as it is complete itself and no operand is used with this instruction. HLT instruction stops further processing of the computer. This instruction must be used as the last instruction of every program otherwise meaningless answer will be obtained. The complete assembly and machine code (Binary and Hexadecimal) of all the operations are shown in table 2.3. Table 2.3 Assembly Code Machine Code Operations Binary Hex LDA 5H 0000 0101 05 H Loads the Acc., the content of memory location 5 H. ADD CH 0001 1100 1C H Adds the content of memory location CH to Acc. content. SUB BH 0010 1011 2B H Subtracts the content of memory location BH from the Acc. content. OUT 1110 xxxx Ex H Sends Acc. content to the output port. HLT 1111 xxxx Fx H Stops the processing. 2.3 PROGRAMMING OF SAP-I COMPUTER Programming means set of instructions written by the user or programmer for performing a particular task. These instructions are then fed to the computer to get the

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desired result. The program for the particular task is written by the programmer in assembly language (in mnemonic form) and then fed to the computer in the consecutive memory locations in the form of op codes (machine language) along with data. The program written in mnemonics form or assembly language is also called Source Program and the program written in machine language is known as Object Program. It will now be illustrated in more detail by taking an example. Suppose we wish to get the addition of three numbers (decimal) 2, 3 and 5. Let these numbers are stored in three different memory locations 6, 7 and 8 respectively. Following steps will be taken for its execution: Step-I Step-II

Step-III

Step-IV Step-V

First number from the memory location 6 should be transferred to the accumulator (LDA 6 H). Second number from memory location 7 should be added to the accumulator and sum of these two numbers should remain in the accumulator (ADD 7 H). Third number from memory location 8 should now be added to the accumulator content and final sum should also remain in the accumulator (ADD 8 H). Final answer (accumulator content) should be sent to the output port for the display in binary form (OUT). Stop the processing of the computer (HLT).

The program is now fed in the memory locations starting at 0 H and data in the memory locations starting at 6 H, as: Memory location Mnemonic (in Hex) 0H LDA 6 H 1H ADD 7 H 2H ADD 8 H 3H OUT 4H HLT 5H xx H 6H 02 H 7H 03 H 8H 05 H This program in machine language is given as: Memory location Op code 0000 0001 0010 0011 0100 0101 0110

0000 0110 0001 0111 0001 1000 1110 xxxx 1111 xxxx xxxx xxxx 0000 0010

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0111 0000 0011 1000 0000 0101 Note: x – sign represents any binary digit 0 or 1. Example 2.1 Write an assembly language program that performs the following operation in SAP-I computer. 7+6−4+5−3 Use memory locations 7H to BH for the data. Further convert this program in machine language.

Solution. below:

SAP-I assembly language program of the given problem is as given Memory location (in Hex)

Mnemonic

0H LDA 7 H 1H ADD 8 H 2H SUB 9 H 3H ADD A H 4H SUB B H 5H OUT 6H HLT 7H 07 H 8H 06 H 9H 04 H AH 05 H BH 03 H This program in machine language is given by: Memory location Op code 0000 0000 0111 0001 0001 1000 0010 0010 1001 0011 0001 1010 0100 0010 1011 0101 1110 xxxx 0110 1111 xxxx 0111 0000 0111 1000 0000 0110 1001 0000 0100 1010 0000 0101 1011 0000 0011 Example 2.2 Write an assembly language program to calculate the following expression on SAP-I computer: Y + 2 Z − 3W The data Y, Z and W (as 6, 7 and 2) are stored in memory locations 8H to AH. Solution.

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SAP-I assembly language program of the given problem is as given below: Memory location Mnemonic (in Hex) 0H LDA 8 H 1H ADD 9 H 2H ADD 9 H 3H SUB A H 4H SUB A H 5H SUB A H 6H OUT 7H HLT 8H 06 H 9H 05 H AH 02 H Example 2.3 Write assembly program for SAP-I computer to solve the following problem: 17 + 22 + 20 − 33 . The numbers are given in decimal. Also give the machine language program. Solution. First the decimal numbers are converted to Hexadecimal numbers. The Hexadecimal equivalents of these numbers are given as: 17 = 11 H 22 = 16 H 20 = 14 H 33 = 21 H Let us assume that these numbers are stored in memory locations 7H to AH. Memory location Mnemonic (in Hex) 0H LDA 7 H 1H ADD 8 H 2H ADD 9 H 3H SUB A H 4H OUT 5H HLT 6H xxH 7H 11 H 8H 16 H 9H 14 H AH 21 H The machine language program is given as follows: Memory location Op code 0000 0000 0111 0001 0001 1000 0010 0001 1001 0011 0010 1010 0100 1110 xxxx

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0101 1111 xxxx 0110 xxxx xxxx 0111 0001 0001 1000 0001 0110 1001 0001 0100 1010 0010 0001 2.4 WORKING OF SAP-I COMPUTER For the working of SAP-I computer, instructions are fetched from RAM and then executed one by one in a sequence till a Halt instruction is executed. The SAP-I computer executes program starting from 0 H memory location. For this controller / sequencer unit generates a CLK signal for all the register and CLR signal for the Program counter. As soon as the computer starts executing the program, program counter receives a CLR signal which resets the program counter. The program counter will send the address of 0 H memory location. In SAP-I computer the loading of a register takes place only when setup and hold times of the clock pulse are satisfied. For this 50% duty cycle clock pulse is used and positive edge occurs half way through each state. Waiting half a cycle before loading the register satisfies setup time; waiting half a cycle after loading satisfies the hold time. Secondly, the reason for waiting half a cycle before loading a register is that when enable input of the sending register goes active, the content of the register suddenly dumped on to register. Stray capacitance and lead inductance may, however, prevent the voltage level immediately. In other words the transients on the W-Bus will be eliminated if the clock has the wait time to die out the transients and valid data is transferred. The control word generated by the controller sequencer unit does the automatic operation of the computer. The execution of a program is carried out by fetching and execution operations of the instructions. The instruction cycle for the execution of an instruction consists of the following two cycles: (i) Fetch cycle fetches a word from memory (ii) Execution cycle executes the fetched instruction We will now discuss these cycles in detail. 2.4.1 Fetch Cycle The operation of fetch cycle is performed in three states namely: (a) Address State (b) Increment State (c) Memory State During the address state, the content of PC is transferred to MAR via W-Bus: MAR ← PC During the increment state, the PC gets incremented. The incremented content will be sent to MAR when next fetch cycle occurs. PC ← PC + 1 During the memory state, memory read operation is performed. W − Bus ← M PC The control word generated by the controller sequencer for these three states is given below:

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T1

CPE P LM CE 0 1 0 1

L1 E 1 L A E A 1 1 1 0

SU E U L B L O 0 0 1 1

T2

1 0 1 1

1 1 1 0

0 0 1 1

T3

0 0 1 0

0 1 1 0

0 0 1 1

Fig. 2.2

Address State Only E P and L M are active. Figure 2.2 shows shaded boxes as active. Increment State Only CP is active. Figure 2.3 shows shaded boxes as active. Memory State Only C E and L1 are active. Figure 2.4 shows shaded boxes as active.

Fig. 2.3

Fig. 2.4

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Fig. 2.5(a)

Fig. 2.5(b) The Controller-sequencer keeps a track of three different states of Fetch cycle and generates control signals accordingly. A ring counter is used for this purpose. Consider a 6-bit synchronous ring counter as shown in figure 2.5(a). The output T of the ring counter is given by: T = T6 T5 T4 T3 T2 T1 At the start of the computer run, 6-bit output of the ring counter at the successive clock pulse is shown in figure 2.5(b). The details of the same are given below: T6 T5 T4 T3 T2 T1 st 1 clock pulse = 0 0 0 0 0 1 2nd clock pulse = 0 0 0 0 1 0 3rd clock pulse = 0 0 0 1 0 0 4th clock pulse = 0 0 1 0 0 0 30

5th clock pulse = 0 1 0 0 0 0 6th clock pulse = 1 0 0 0 0 0 7th clock pulse = 0 0 0 0 0 1 and so on. The different outputs are also called T-states or timing states. During first three clock pulses the operation of fetch cycle occurs which are explained below: During T1 state of the timing signal, Controller-sequencer generates a signal so that E P is high and L M is low which sends the content of PC (address of the instruction stored in RAM) to W-Bus and at the positive edge of the clock pulse (midway of the clock pulse) the content of the W-Bus are latched into MAR due to low L M – This state is called Address State of the fetch cycle. During T2 state of the timing signal, controller sequencer generates a signal giving high to C P . At the positive edge of the clock pulse (midway of the clock pulse), PC advances the count by 1 – This state is called Increment State of the fetch cycle. During T3 stat, control signal generated by Controller-sequencer makes C E and L1 low. The addressed RAM word is transferred to W-Bus and at positive edge of CLK (midway of clock) the data is transferred to W-Bus and then loaded to Instruction register – This state is called Memory State of the fetch cycle. The next three states of clock pulse are called the execution cycle of SAP-I instructions. 2.4.2 Execution Cycle After the instruction is fetched and transferred to the Instruction Register (IR) during the fetch cycle, the IR splits the instruction word (8-bit) into two nibbles. The upper nibble goes directly to the controller-sequencer, where it is decoded and accordingly the control word is generated to act as per the direction of the instruction. The decoded output will be different for different instructions (LDA, ADD, SUB, OUT, and HLT). So during the execution cycle (T4 to T6 of the clock pulse), the operation of control signal will be different for different instructions. Now we will discuss these operations for each cycle. Execution Cycle of LDA Instruction: For the discussion of the operation LDA instruction, let us assume the instruction is LDA 6 H = 0 0 0 0 0 1 1 0 In this instruction 0 0 0 0 is the op code of LDA and 6 H (0 1 1 0) is the address of the location where the data is stored. During T3 state of CLK, 0000 0110 is loaded to Instruction Register (IR). The upper nibble 0000 directly goes to controller-sequencer, where it is decoded. During T4, T5 and T6 states for the execution of LDA instruction, the controller-sequencer will generate the following control words in sequence: C P E P L M C E L1 E 1 L A E A S U E U L B L O T4 0 0 0 1 1 0 1 0 0 0 1 1 MAR ← IRLNIBBLE T5 0 0 1 0 1 1 0 0 0 0 1 1 A ← M (MAR ) T6 0 0 1 1 1 1 1 0 0 0 1 1 NO OPERATION During T4 state of CLK, lower nibble already available at the W-Bus is loaded into MAR since E1 and L M are active.

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During T5 state of CLK, C E and L A are active which loads the addressed content from RAM to Accumulator. This was the function of LDA instruction. During T6 state of CLK, no operation is performed as nothing was left for this instruction to do. T4 to T6 states of LDA instruction are shown in figure 2.6 (a to c) with active parts as shaded boxes and figure 2.7 shows timing diagram for Fetch and execution cycle of LDA instruction. The control word generated for each T-state is called as Microinstruction. One of the instructions in instruction set is known as Macroinstruction. The microinstruction for T4, T5 and T6 states of LDA instruction is given below: States T4 T5 T6

Microinstruction 1A3 H 2C3 H 3E3 H

(a)

(12 Bit Control Word) 0001 1010 0011 0010 1100 0011 0011 1110 0011

(b)

(c) Fig. 2.6

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Fig. 2.7 Execution Cycle of ADD Instruction: For the execution of ADD instruction following control signals in sequence during T4, T5 and T6 states will be observed: SU E U L B L O CP E P LM CE L1 E1 L A E A T4 0 0 0 1 1 0 1 0 0 0 1 1 MAR ← IR LNIBBLE T5 0 0 1 0 1 1 1 0 0 0 0 1 B ← M(MAR) T6 0 0 1 1 1 1 0 0 0 1 1 1 A ← SUM During T4 state, the address part of ADD instruction moves to MAR as L M and E1 are active. The data from MAR is fetched and loaded into register B during T5 state as C E and L B are active. The adder-subtractor adds the content of Accumulator and register B as SU is inactive. During T6 state the answer (Sum) is loaded to accumulator, as EU and L A are active. T states of ADD instruction are shown in figures 2.8 (a to c) with active parts as shaded boxes. The timing diagram of Fetch and ADD instruction is shown in figure 2.9. The microinstruction for T4, T5 and T6 states of ADD instruction is given below:

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States T4 T5 T6

Microinstruction 1A3 H 2E1 H 3C7 H

(a)

(12 Bit Control Word) 0001 1010 0011 0010 1110 0001 0011 1100 0111

(b)

(c) Fig. 2.8

34

Fig. 2.9 Execution Cycle of SUB Instruction: The third instruction of SAP-I instruction set is SUB-instruction. For the execution of SUB instruction, following control signals in sequence will be observed during T4, T5 and T6 states. SU E U L B L O CP E P LM CE L1 E1 L A E A T4 0 0 0 1 1 0 1 0 0 0 1 1 MAR ← IR LNIBBLE T5 0 0 1 0 1 1 1 0 0 0 0 1 B ← M(MAR) T6 0 0 1 1 1 1 0 0 1 1 1 1 A ← DIFF . From the above sequence it is clear that SUB instruction follow the same sequence as ADD instruction except that during T5 state SU is high. T states (T4 to T6) of SUB instruction are shown in figures 2.10 (a to c) with active parts as shaded boxes. The timing diagram of Fetch and SUB instruction is shown in figure 2.11. The microinstruction for T4, T5 and T6 states of SUB instruction is given below:

35

States T4 T5 T6

Microinstruction 1A3 H 2E1 H 3CF H

(a)

(12 Bit Control Word) 0001 1010 0011 0010 1110 0001 0011 1100 1111

(b)

(c) Fig. 2.10

36

Fig. 2.11 Execution Cycle of OUT Instruction: For the execution of this instruction, following control signals in sequence will be observed during T4, T5 and T6 states of execution cycle. SU E U L B L O CP E P LM CE L1 E1 L A E A T4 0 0 1 1 1 1 1 1 0 0 1 0 T5 0 0 1 1 1 1 1 0 0 0 1 1 T6 0 0 1 1 1 1 1 0 0 0 1 1 During T4 state, EA and L O are active due to which at the positive edge of clock pulse accumulator content is loaded to the output register. High EA send the accumulator data to W-Bus and low L O loads the data from W-Bus to output register. The work of out instruction is complete. So no-operation is performed during T5 and T6 state i.e. all the signals of the control word are inactive. T states of OUT instruction are shown in figures 2.12 (a to c) with active parts as shaded boxes. The timing diagram of Fetch and OUT instruction is shown in figure 2.13.

37

The microinstruction for T4, T5 and T6 states of OUT instruction is given below: States T4 T5 T6

Microinstruction 3F2 H 3E3 H 3E3 H

(a)

(12 Bit Control) 0011 1111 0010 0011 1110 0011 0011 1110 0011

(b)

(c) Fig. 2.12

38

Fig. 2.13 Execution Cycle of HLT Instruction: HLT instruction does not require any T-cycle for its execution. Thus during T4, T5 and T6 state all the signals of the control word are inactive i.e. no-operation is performed during these states. SU E U L B L O CPE P LM CE L1 E 1 L A E A T4 0 0 1 1 1 1 1 0 0 0 1 1 T5 0 0 1 1 1 1 1 0 0 0 1 1 T6 0 0 1 1 1 1 1 0 0 0 1 1 The microinstruction for T4, T5 and T6 states of HLT instruction is given below: States Microinstruction (12 Bit Control Word) T4 3E3 H 0011 1110 0011 T5 3E3 H 0011 1110 0011 T6 3E3 H 0011 1110 0011 Example 2.4 What are Microinstructions for: (i) LDA instruction (ii) ADD instruction Solution. (i) During T4 state of LDA instruction L M and E 1 are active. During T5 state of LDA instruction C E and L A are active and During T6 state of LDA instruction None is active. So Microinstructions for LDA are 39

For T4 1A3 H T5 2C3 H T6 3E3 H (ii) Similarly, Microinstruction for ADD instruction are For T4 1A3 H 2C3 H T5 3E7 H T6 2.5 HARDWARE DESIGN OF SAP-I COMPUTER In this section we shall discuss the hardware details of the following blocks of SAP-I computer: Program Counter Memory Unit Instruction Register Controller-Sequencer Accumulator Adder-Sutractor B-Register Output Register and Binary Display 2.5.1 Design of Program Counter The program counter (PC) is designed using four J-K flip-flops. The circuit diagram of program counter is shown in figure 2.14. From this diagram it can well be understood that during the start of computer run a low CLR signal resets the program counter to 0 0 0 0. During T1 state of fetch cycle, a high EP sends the address to the WBus. During T2 state, high CP increments the Program counter, at the midway through T2. the program counter is, however, inactive during T3 through T6 states.

Fig. 2.14 2.5.2 Memory Unit

40

Figure 2.15 shows the circuit diagram of memory unit, which consists of Input & MAR and RAM. In this figure IC1 and IC2 form Input & MAR; IC3 and IC4 form read/write memory. IC1 is a 4-bit buffer register. It is a three state output register which is configured here in a two state output, as it is not to be connected to W-Bus. IC2 is basically 2 to 1 nibble multiplexer. When the switch S1 is connected to Run position, the address bits are directly available at the output of IC2. If on the contrary S1 is at the Run position, the address bit from the W-Bus will be available at the output of this IC2. IC3 and IC4 are two 16X4 static RAM, which form the RAM of SAP-I. These two IC’s are configured to form, 16X8 read/write memory. When switch S1 is at PROG position, S2 is at write position, the data from D0 to D7 will be written into static RAM. If S1 is at Run position, the data already stored in the memory will be available at the WBus.

Fig. 2.15 2.5.3

Instruction Register

41

IC1 and IC2 forms the Instruction Register. These are two four-bit buffer registers. These buffer registers are three state registers. IC1 is configured as two state output. The outputs of this IC are upper nibble I7 I6 I5 I4 which directly goes to controllersequencer where these are decoded. The outputs of IC2 are the lower nibble (operand of the fetched instruction), which are directly connected to W-Bus. The logic circuit diagram of the Instruction register is shown in figure 2.16.

Fig. 2.16 2.5.4

Controller-Sequencer

The schematic block diagram of controller-sequencer is shown in figure 2.17. It consists of a ring counter, instruction decoder and control matrix for the generation of 12bit control word. The instruction decoder is a simple decoder, which provides the outputs LDA, ADD, Sub, OUT and HLT. In fact it is a 4-to-5 decoder.

42

Fig. 2.17 The required logic is shown in table 2.4.

I7 0 0 0 1 1

I6 0 0 0 1 1

I5 0 0 1 1 1

Table 2.4 I4 OUTPUT 0 LDA 1 ADD 0 SUB 0 OUT 1 HLT

The logic diagram for the Instruction decoder of SAP-I computer is shown in figure 2.18, which is as per the table 2.4.

43

Fig. 2.18 The synchronous counter has already been discussed. This ring counter gives 6-bit output (T1 to T6) at the successive clock pulse. For the generation of 12-bit control signal, the twelve outputs may be obtained from the logic expressions given below: C P = T2 E P = T1 L M = T1 + T4 . LDA + T4 . ADD+ T4 .SUB

C E = T3 + T5 . LDA + T5 . ADD+ T5 .SUB L1 = T3 E1 = T4 . LDA + T4 . ADD+ T4 .SUB L A = T5 . LDA+ T6 . ADD+ T6 .SUB E A = T4 . OUT SU = T6 .SUB E U = T6 . ADD+ T6 .SUB L B = T5 . ADD+ T5 .SUB LO = T4 . OUT The logic circuit diagram of the above expressions is shown in figure 2.19.

44

Fig. 2.19 2.5.5 Accumulator Figure 2.20 shows the logic diagram of 8-bit buffer register known as accumulator which is designed using two ICs’ IC1 and IC2 (both 74LS173). These ICs are configured as two-state output. The outputs of both the two ICs directly go to AdderSubtractor. Three state switches send the content of accumulator to W-Bus when the signal EA is high.

45

Fig. 2.20 2.5.6

Adder-Subtractor

Figure 2.21 shows the logic circuit used for Adder-subtractor of SAP-I computer. It basically consists of two 2’s complement adder/subtractor ICs (7483). The data from the accumulator directly goes to the Adder-subtractor as shown in figure 2. . The outputs of B-register are also connected to these two ICs through eight exclusive-OR gates. The one terminal each of the eight exclusive-OR gates is being used as control Input (SU). When SU is low the content of B-register is directly loaded to Adder/Subtractor i.e. it will act as simple adder. If on the other hand SU is high, 1’s complement of B-register is being added to adder/subtractor ICs. Logic 1 is also added to LSB to form its as 2’s complement (it therefore works as 2’s complement subtractor). These two

46

adder/subtractor ICs give the 8-bit addition or subtraction. The 8-bit three state switches load the answer (sum or difference) to W-bus.

Fig. 2.21 2.5.7 B-Register Similar to Accumulator, B-register is also designed using the Buffer register ICs 74LS173. The logic circuit diagram of this register is shown in figure 2.22. These two ICs are configured as two state register. When L B is low, the data from the W-Bus is loaded to B-register and then transferred to Adder/Subtractor.

47

Fig. 2.22 2.5.8

Output Register Output register is also formed by two state Buffer register using 74LS173 ICs. The output register with Binary display unit of SAP-I computer is shown in figure 2.23. When L O is low, the data from the W-Bus will be loaded to output register. The output terminals of output register are connected to 8 LEDs, which will glow as per the data available at the output register.

48

Fig.2.23 Problems 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8

2.9

Draw the block diagram of SAP-I computer. Discuss the function of each block. What is the function of Controller/Sequencer in SAP-I computer? How a control word is generate in SAP-I computer? Draw the logic circuit diagram of Program counter and discuss its function. Explain with the help of timing diagram the fetch and execution cycle of LDAinstruction. Explain with the help of timing diagram the fetch and execution cycle of ADDinstruction. Explain with the help of timing diagram the fetch and execution cycle of SUBinstruction. Explain with the help of timing diagram the fetch and execution cycle of OUTinstruction. Explain with the help of timing diagram the fetch and execution cycle of HLTinstruction. Further explain what will happen if HLT instruction is not given at the end of the program? Differentiate between: (i) Micro-instruction and Macro-instruction

49

2.10 2.11 2.12 2.13

2.14 2.15

2.16

2.17 2.18

(ii) Assembly language and machine language (iii) Source program and object program Explain the instruction set of SAP-I computer. What is the size of MAR of the SAP-computer? Why the positive clock edge occurs half way through each T-state in SAP-I computer? What is the role of instruction register in SAP-I computer? Draw the logic diagram for Instruction register of SAP-I computer? Write an assembly language program that perform the following operation in SAP-I computer. 8−3+5+ 2−4 Use memory locations 7H to BH for the data. Write also its program in machine language. Write an assembly language program for SAP-I computer that will display the result of 9 + 3 − 2 . Write an assembly language program for SAP-I computer that will display the result of 7 + 3 − 2 + 4 − 1 + 6 . Use AH to FH memory locations for starting the data. Write an assembly language program for calculating the following expression A + 3 B− 2 C on SAP-I computer. The data A, B and C are stored in memory locations 9 H to B H. Write also its machine language. What are microinstructions for SUB and OUT instructions of SAP-I computer. Express the answer in binary also. The timing diagram for Fetch and Execution cycle of ADD instruction is shown in figure 2.24. What are the microinstructions for Fetch and Execution cycle of ADD instruction?

50

Fig. 2.24 ____

51

3 SAP – II In the preceding chapter of this book, the architecture, Instruction set and Programming of a conceptual computer named SAP-I computer was discussed. In order to understand the basic knowledge of a computer, it was the first step in the evolution towards the modern computers. The further step in this direction is SAP-II computer. The details of SAP-II computers will now be discussed. 3.1 ARCHITECTURE OF SAP-II COMPUTER The architecture of another conceptual computer named as SAP-II computer is shown in figure 3.1. The SAP-II computer has more registers and other blocks, for giving more flexibility in programming. The architectural details of the Simple as Possible computer SAP-II are basically same as that of SAP-I, but SAP-II has more additional features which are given below: (1) It is an eight bit computer, as 8-bit data can be processed in this computer. The SAP-I computer was also 8-bit computer. (2) It has bidirectional BUS shown by double headed arrows, which indicate that the data can move either way after having the proper control signal. In SAP-I computer separate BUS is used for each way. (3) The memory size of SAP-II computers is 64K (65536) words and each word is of 8-bit long. The data may be loaded or retrieved from the memory, through a buffer register known as Memory Data Register (MDR) or Memory Buffer Register (MBR). The address for the location is 16 bits as 64 K = 65536 = 216 . The address will start from: 0000 0000 0000 0000 to 1111 1111 1111 1111 The hexadecimal equivalent of the address is 0 0 0 0 H to F F F F H. However, memory size of SAP-I computers was only 16. As 24 = 16, so 4 address lines were used. (4) The width of the W-BUS is 16, since it has to carry a 16 bit address. The width of W-bus for SAP-I computer was only of 8-bits. (5) The program counter of SAP-II computer is 16-bit wide as it has to send the address of 16 bits to W-BUS. (6) Memory Address Register (MAR) of SAP-II computer is of 16 bits as it receives the address of 16-bits from the W-BUS.

(7)

(8)

The controller sequencer of SAP-II computer generates a control word of bigger size than that of SAP-I computer; since it has to control more registers and blocks of the computer. The control word of SAP-I computers was of 12 bits.

Fig. 3.1 There are three registers in SAP-II computers namely Accumulator (Register A), Register B and Register C. All these registers are 8-bit registers. The registers B and C are general purpose registers. These registers give more flexibility in moving the data from one register to other register during the computer run. In SAP-I computer B-register was available for holding the data being added to or subtracted from the

53

(9)

accumulator. In SAP-II computers, there is a temporary register (Tregister) for this purpose. SAP-II computer has Arithmetic and Logical unit (ALU) which can perform the arithmetic and logical operations on 8 bit data. Two flags (Sign flag S and Zero flag Z) are available with ALU. The accumulator content goes negative or zero during execution of some instructions. This affects the sign and zero flags. Figure 3.2 shows the circuit used for setting of flags of SAP-II computers. It is clear from this figure that when accumulator content is zero all the bits (A0 to A7) are zero and the output of NOR gate is one. This NOR gate derives the AND gate (numbered 2), if the gating signal LF is high and the flag will be updated. Similarly, if the accumulator content is negative, most significant bit (A7) of the accumulator will be one which drives the lower AND gate (numbered 3) and sign flag will be updated when LF is high. The sign flag will be set if accumulator content is negative and reset if positive. The zero flag will be set if accumulator content is zero and reset if it is non zero.

Fig. 3.2 (10) There are two input ports (Input Port-1 and Input Port-2) in SAP-II computers as shown in figure 3.1. A hexadecimal keyboard encoder is connected to Port 1. The instruction and data fed to the computer through this input port 1. The encoder sends a READY signal to bit 0 of Input Port-2. The data may also be accepted in serial form through the Input Port-2. (11) SAP-II computer has two Output Ports namely output port-1 and output port-2. Through the output port-1, the processed data (answer from accumulator) can be visualized on the hexadecimal display. The accumulator content can also be sent to output port serially. (12) Because of the availability of more registers and large size of memory, SAP-II computer has an instruction set with 42 instructions. SAP-I computer has only 5 instruction in its instruction set. 3.2 INSTRUCTION SET OF SAP-II COMPUTERS

54

As already discussed SAP-II computer has 42 instructions in its instruction set which are listed in table 3.1. These instructions are divided into 5 different categories as: Memory Reference Instructions Register Instructions Jump and Call instructions Logical Instructions Miscellaneous Instructions Table 3.1 Category Instruction Op. Operation Code Memory LDA address 3A [A] ← [M address ] Reference STA address 32 [M address ] ← [A] instructions

Register Instructions

Jump and Call instructions

MVI A, data MVI B, data MVI C, data MOV A, B MOV A, C MOV B, A MOV B, C MOV C, A MOV C, B ADD B ADD C SUB B SUB C INR A INR B INR C DCR A DCR B DCR C JMP address JM address

3E 06 0E 78 79 47 41 4F 48 80 81 90 91 3C 04 0C 3D 05 0D C3 FA

JZ address

CA

JNZ address

C2

CALL address

CD

[A] ← Data [B] ← Data [C ] ← Data [A] ← [B] [A] ← [C ] [B] ← [A] [B] ← [C ] [C ] ← [A] [C ] ← [B] [A] ← [A] + [B] [A] ← [A] + [C ] [A] ← [A] − [B] [A] ← [A] − [C ] [A] ← [A] + 1 [B] ← [B] + 1 [C ] ← [C ] + 1 [A] ← [A] − 1 [B] ← [B] − 1 [C ] ← [C ] − 1 [PC ] ← Address [PC ] ← Address ; if acc. content is negative. [PC ] ← Address ; if acc. content is zero. [PC ] ← Address ; if acc. content is not zero. Stack ← [PC ] and

55

[PC ] ← Address [PC ] ← Stack

RET C9 Logical CMA 2F A← A instructions ANA B A0 A ← A. AND . B ANA C A1 A ← A. AND .C ORA B B0 A ← A.OR . B ORA C B1 A ← A.OR .C XRA B A8 A← A⊕ B XRA C A9 A ← A⊕C ANI, data E6 A ← A. AND .data ORI, data F6 A ← A.OR .data XRI, data FE A ← A ⊕ data Miscellane NOP 00 No operation ous IN Port DB [A] ← [Portadress ] instruction OUT Port D3 [Outport ] ← [A] RAL 17 Rotate acc. left RAR 1F Rotate acc. right HLT 76 Stops Processing The operation to be performed by each instruction has been explained in table 3.1. After going through these instructions, it will be possible to write complicated programs in solving the different problems. The SAP-II computer has memory reference instruction like ‘STA address” which allows to store the content of accumulator to the memory location whose address is given with the instruction. For example if accumulator has the content A = 1 0 1 0 1 0 1 0 before execution of an instruction. Let the instruction is STA 2050 H After execution of this instruction the memory location 2050 H will have the data 1 0 1 0 1 0 1 0. i.e. M 2050 H = 10101010 In register instructions, MOV C, B copies the content of B-register into C-register (C ← B) . In Call instructions, the instruction ‘CALL address’ copies the present address of program counter to Stack and the given address with the instruction is copied into program counter. So whenever the next instruction is fetched, the program counter will send this new address. This instruction helps in jumping from the normal routine of the program to subroutine program. The instruction RET stands for return. This statement is used at the end of subroutine program and its sends back to the original program as the content of the stack is copied back to the program counter. In SAP-II computer there is, however, no register for Stack. The last two memory locations FFFE H and FFFF H are used for this purpose as shown in figure 3.3 i.e. these two locations are exclusively used for saving the return address of the subroutine program. The SAP-II computer has the logical instructions such as ‘ANA reg’, ‘ORA reg’, ‘XRA reg’, ‘ANI data’, ‘ORI data’, ‘XRI data’ and ‘CMA’. The ‘ANA B’ instruction

56

AND the contents of A register with the contents of B register bit by bit and the answer is loaded into accumulator. In miscellaneous instructions, ‘IN port’ loads the data word from an input port to the accumulator.

Fig. 3.3 The RAL instruction rotates the accumulator left. This instruction will shift all bits of accumulator content to the left and move the MSB into LSB position as illustrated in figure 3.4.

Fig.3.4 Similarly, the RAR instruction rotates the accumulator right. This instruction will shift all bits of accumulator content to the right and move the LSB into MSB position as illustrated in figure 3.5.

Fig. 3.5 3.3 MACHINE CYCLE AND INSTRUCTION CYCLE It has been discussed in the last chapter that the SAP-I computer takes 6-T states to fetch and execute an instruction. These six states form a machine cycle. The number of T-states needed to fetch and execute an instruction is called Instruction cycle. So in SAPI computer instruction cycle is machine cycle as shown in figure 3.6. The SAP-II computer has, however, more than one machine cycle to fetch and execute an instruction. As shown in figure 3.7, first three T-states are used to fetch an 57

instruction and other 9 T-states are used for the execution of an instruction. So in SAP-II or other computers the instruction cycle may have two or more machine cycles. Table 3.2 shows the number of T-states used for the instruction cycle of each instruction.

Fig. 3.6

Fig. 3.7 The instruction ‘STA address’ takes 13 T-states to fetch and execute this instruction. If the system clock frequency is 3 MHz, then ‘STA address’ will take 1 13 x µ sec = 4.33µ sec 3 time to fetch and execute this instruction i.e. it is the time of instruction cycle of the instruction ‘STA address’. Table 3.2 Instruction Addressing No of Flags No of T-states affected bytes of instr. LDA address Direct 13 None 3 STA address Direct 13 None 3 MVI A, data Immediate 7 None 2 MVI B, data Immediate 7 None 2 MVI C, data Immediate 7 None 2

58

MOV A, B Register 4 None 1 MOV A, C Register 4 None 1 MOV B, A Register 4 None 1 MOV B, C Register 4 None 1 MOV C, A Register 4 None 1 MOV C, B Register 4 None 1 ADD B Register 4 S, Z 1 ADD C Register 4 S, Z 1 SUB B Register 4 S, Z 1 SUB C Register 4 S, Z 1 INR A Register 4 S, Z 1 INR B Register 4 S, Z 1 INR C Register 4 S, Z 1 DCR A Register 4 S, Z 1 DCR B Register 4 S, Z 1 DCR C Register 4 S, Z 1 JMP address Immediate 10 None 3 JM address Immediate 10/7 None 3 JZ address Immediate 10/7 None 3 JNZ address Immediate 10/7 None 3 CALL address Immediate 18 None 3 RET Implied 10 None 1 CMA Implied 4 None 1 ANA B Register 4 S, Z 1 ANA C Register 4 S, Z 1 ORA B Register 4 S, Z 1 ORA C Register 4 S, Z 1 XRA B Register 4 S, Z 1 XRA C Register 4 S, Z 1 ANI, data Immediate 7 S, Z 2 ORI, data Immediate 7 S, Z 2 XRI, data Immediate 7 S, Z 2 NOP 4 -1 IN Port Direct 10 None 2 OUT Port Direct 10 None 2 RAL Implied 4 None 1 RAR Implied 4 None 1 HLT 5 -1 3.4 ADDRESSING MODES There are various techniques to specify the data for instruction. These techniques are called addressing modes. SAP-II computer has the following addressing modes: 1. Direct Addressing 2. Register Addressing 3. Immediate Addressing 4. Implied Addressing

59

Direct Addressing In this mode of addressing, the address of the operand is given in the instruction itself. For example LDA 2100 H OUT 03 H etc. Register Addressing In this mode of addressing, the operands are in registers. For example MOV A , B ADD C etc. Immediate Addressing In immediate addressing mode, the operand in specified in the instruction itself. For example MVI B, 08 H ANI 07 H etc. Implied Addressing There are certain instructions which operate on the contents of the accumulator. Such instructions do not require the address of the operand, since the operand is implied in the instruction itself. So this type of addressing mode is called as Implied Addressing. For example CMA RAL RAR etc. The addressing modes of all the instructions of SAP-II computers are given in table 3.2. 3.5 INSTRUCTION TYPES The instruction set of SAP-II computer may be divided into three types. As already seen, there are different ways for specifying the data for instructions, so the machine codes of all instructions are not of same length. Following are the types of instructions: (i) One Byte Instruction (ii) Two Byte Instruction (iii) Three Byte Instruction One Byte Instruction This type of instruction has only op code part of one byte and no operand is given. The instruction length is only of one byte. It can be stored only in one memory location. For example MOV A, C ADD C CMA RAL RAR etc. If ‘MOV A, C’ instruction is to be stored in some location say 2000 H, then its op code of one byte is to be fed in this memory location. i.e. 2000 H 79 H where 79 H is the op code of the instruction ‘MOV A, C’. Two Byte Instruction In a two byte instruction, first byte of the instruction is its op code and second byte is the given data. Such instruction is stored in two consecutive memory locations.

60

For example

MVI A, 06 H OUT 03 H ANI 76 H etc. In order to store the instruction say ‘MVI A, 06 H’ in the memory locations of the computer, we have to use two consecutive memory locations. In one memory location the op code of MVI A is to be stored and in the second location the data 06H is to be stored. This type of instruction to be stored in two locations say in 2101 H and 2102 H is given below: 2101H 3E H (op code of MVI A) 2102H 06 H (given data) Three Byte Instruction In a three byte instruction, first byte is used for its op code and second and third bytes are used for 16 bit address. Such an instruction is stored in three consecutive memory locations. For example LDA 2100 H STA 3000 H JMP 2500 H etc. In order to store the instruction say ‘LDA 2100 H’ three consecutive memory locations are to be used. In the first memory location op code of the instruction is stored, in second location lower byte of the address is to be stored and in the third byte upper byte of the address is to be stored. This instruction loaded in three consecutive memory location 2000H, 2001H and 2002H is given below: 2000H 3A H (op code of LDA) 2001H 00 H (Lower byte of address 2100 H) 2002H 21 H (Upper byte of address 2100 H) The type of instructions of all the 42 instructions of SAP-II computer is also given in table 3.2. 3.6 FLAGS As already discussed, there are two flags associated with the accumulator of SAPII computer, sign flag (S) and Zero flag (Z). These flags may be set or reset during certain instructions. If the accumulator content is negative after execution of certain instruction the sign flag is set otherwise it is reset. Similarly, if the accumulator content is zero after the operation of certain instruction the zero flag is set otherwise reset. These instructions which affect the flags are listed in table 3.3. Table 3.3 Instruction ADD SUB INR DCR ANA ORA ANI ORI XRI

Flags affected S, Z S, Z S, Z S, Z S, Z S, Z S, Z S, Z S, Z 61

For example in ADD instruction say ADD B, the contents of B register gets added with the accumulator content and after addition the result is stored in accumulator. If the result is zero then zero flag is set otherwise reset. Similarly, if the result is negative the sign flag is set otherwise reset. In INR or DCR instructions both sign and zero flags are affected. For example if there is an instruction INR B, the content of B register is incremented by sending the contents to accumulator and adds 1 to it. The result is then sent back to B register. If the accumulator goes negative while INR instruction is executed, the sign flag is set; and if the accumulator content is zero then the zero flag is set. 3.7 ASSEMBLY LANGUAGE PROGRAMMING The programming of the problem is generally written in assembly language. The assembly language is written in mnemonics. The mnemonics are the initials or short form of the English word of the operation to be performed by the instruction. Assembly language statements are written in standard format as given below: Label Mnemonic Operand Comment Label

A label is a symbol or group of symbols used to represent an address of the location which is not specifically known at the time of program is written. The label can be one to six characters, the first character of which must be a letter. Following are the acceptable labels. NEXT, BACK, DELAY, A2 etc.

Mnemonic

Short form of the operation to be performed.

Operand

Operand is the data on which the operation is performed. It can be a data, memory address, register or port address.

Comment

The comment statement is started with the semicolon. It gives the idea of the program to the user. The comments are not the part of the machine language program. The program written in assembly language can be converted to machine language by hand. For writing the program in machine language, the starting address, where the program is to be stored should be known. Now the op code of the instruction is to be written in first location (starting address) and in the consecutive memory locations data /address of the operand is written. While storing the address in the memory locations, lower byte of he address is stored first then the upper byte as discussed above. Example 3.1 Write assembly language program using the instructions of SAP-II computer of the following statement. Also write the program in machine language. Load the contents of memory locations 2100 H and 2101 H in B-register and Cregister respectively. The content of memory locations 2100 H and 2101H are 16 H and 19 H respectively. Solution. Label Mnemonic Operand Comment

62

LDA

2100H

; Loads the content of 2100H into accumulator. MOV B, A ; moves the content of accumulator to B-register ( B ← A ). LDA 2101H ; Loads the content of 2100H into accumulator. MOV C, A ; moves the content of accumulator to C-register ( C ← A ). HLT ; Stop processing. The assembly language program may be converted to machine language by writing the op codes of the instructions as given below. Let the starting address of the program is 2000H. Memory Content Address 2000 H 3A H LDA 2100 H 2001 H 00 H 2002 H 21 H 2003 H 47 H MOV B, A 2004 H 3A H LDA 2101 H 2005 H 01 H 2006 H 21 H 2007 H 4F H MOV C, A 2008 H 76 H HLT 2101 H 16 H Data 2102 H 19 H Data Example 3.2 Write an assembly language program to find the 2’s complement of a hexadecimal number. The hexadecimal number 6A H is stored in memory location 2100H and the answer is to be stored in 2101 H. Use SAP-II instructions to program it. Solution. Label Mnemonic Operand Comment LDA 2100 H ; Loads the content of 2100 H into accumulator. CMA ; Complements the accumulator content (1’s complement). INR A ; 1 is added to the accumulator content to get the 2’s complement. STA 2101 H ; Loads the accumulator contents into memory location 2101 H. HLT ; Stop processing. Example 3.3 Write an assembly language program using SAP-II instructions to add two numbers (decimal) 38 and 64, then subtract decimal number 3 from the sum. The final answer is to be stored in memory location 2100 H. Solution. First of all decimal numbers 38 and 64 should be converted to hexadecimal numbers, as it works in hexadecimal. Decimal number 38 = 26 H

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Label

Decimal number 64 = 40 H Mnemonic Operand MVI A, 26 H

Comment ; Loads the first number to accumulator. MVI B, 40 H ; Loads the second number to Bregister. MVI C, 03 H ; Loads the third number to Cregister. ADD B ; Adds the contents of B-register with the contents of accumulator and the answer is stored in A. SUB C ; Content of C gets subtracted from accumulator and difference is stored in A. STA 2100 H ; Answer is stored in 2100 H location. HLT ; Stop processing. Example 3.4 Write a program in assembly language for SAP-II computer to mask off the least significant 4 bits of a given hexadecimal number. The answer should be stored in memory location 2200 H. Let the given number is B3 H. Solution. The binary equivalent of B3 H is 1011 0011. The masking of the 4 least significant bits 0011 means to make 0011 to 0000. However, the four most significant bits should not be changed. This can be done if the given number is ANDed with F0 H (1111 0000). In doing so when 4 most significant bits are ANDed with 1111 no change will be there, but 4 least significant bits will be 0000 as required. The assembly language program for this will be as follows: Label Mnemonic Operand Comment MVI A, B3 H ; Loads the number B3H to accumulator. ANI F0 H ; ANDs the accumulator with F0H and answer is loaded to accumulator. STA 2200 H ; Answer is stored in 2200 H location. HLT ; Stop processing. Example 3.5 Write a program in assembly language for SAP-II computer to load a number 79 H in B-register and mask off all bits except A2 bit. The result is to be transferred to C-register. Solution. To mask off the third LSB ( A2 bit) the ANDing of the given content will be with FBH (11111011). The program will be as given below: Label Mnemonic Operand Comment MVI B, 79 H ; Loads the number 79 H to accumulator. MOV A, B ; Moves the content of B-register to accumulator.

64

ANI

FB H

; ANDs the accumulator with FB H and answer is loaded to accumulator. MOV C, A ; Answer is loaded to C-register. . HLT ; Stop processing. Example 3.6 Write a program in assembly language for SAP-II computer to interchange (swap) the contents of two memory locations 2100 H and 2101 H. Solution. The program is given below which is self explanatory. Label Mnemonic Operand Comment LDA 2100H ; Loads the content of 2100H into accumulator. MOV B, A ; Moves the content of Acc to Bregister. LDA 2101 H ; Loads the content of 2101H into accumulator. STA 2100 H ; Loads the acc. content to 2100 H location. MOV A, B ; Moves the content of B-register to Acc. STA 2101 H ; Loads the acc. content to 2101 H location. HLT ; Stop processing. Example 3.7 Write a program in assembly language for SAP-II computer to multiply two decimal numbers 23 and 9 and store the answer in some memory location. Also write this program in machine language. Solution. Hexadecimal equivalent of decimal number 23 is 17 H. The multiplication of these two numbers may be obtained by adding 23 (17 H) by 9 times in the accumulator which should be 00 H at the beginning. So the program of this problem may be as given below: Label Mnemonic Operand Comment MVI A, 00 H ; Loads the acc. 00 H. [ A] ← 00 H . MVI B, 17 H ; Loads B-register with 17H [B] ← 17 H . MVI C, 09 H ; Loads C-register with 09H [C ] ← 09 H . AGAIN ADD B ; Adds the content of B-register to acc. DCR C ; Decrements C-register. JZ END ; Checks for zero; if zero jump to END. JMP AGAIN ; Repeats the addition. END STA 2100 ; Stores the answer to memory location 2100 H. HLT ; Stop processing. The program can be written in machine language stating at address 2000 H as given below: 65

Memory Content Address 2000 H 3E H MVI A, 00 H 2001 H 00 H 2002 H 06 H MVI B, 17 H 2003 H 17 H 2004 H 0E H MVI C, 09 H 2005 H 09 H 2006 H 80 H ADD B 2007 H 0D H DCR C 2008 H CA H JZ 200E H 2009 H 0E H 200A H 20 H 200B H C3 H JMP 2006 H 200C H 06 H 200D H 20 H 200E H 32 H STA 2100 H 200F H 00 H 2010 H 21 H 2011 H 76 H Alternative method of writing this program using JNZ is as given below: Label Mnemonic Operand Comment MVI A, 00 H ; Loads the acc. 00 H. [ A] ← 00 H . MVI B, 17 H ; Loads B-register with 17 H [B] ← 17 H . MVI C, 09 H ; Loads C-register with 09 H [C ] ← 09 H . AGAIN ADD B ; Adds the content of B-register to acc. DCR C ; Decrements C-register. JNZ AGAIN ; Repeats the addition if the content of C-register is not zero. STA 2100 H ; Stores the answer to memory location 2100 H. HLT ; Stop processing. This program can also be written by using subroutine program as follows: Main Program Label Mnemonic Operand Comment MVI A, 00 H ; Loads the acc. 00 H. [ A] ← 00 H . MVI B, 17 H ; Loads B-register with 17 H [B] ← 17 H . MVI C, 09 H ; Loads C-register with 09H [C ] ← 09H . CALL MUL ; Calls subroutine program for multiplication.

66

STA

2100 H

; Stores the answer to memory location 2100 H. ; Stop processing.

Operand

Comment ; Adds the content of B-register to acc. ;Decrements C-register. ; Repeats the addition if the content of C-register is not zero. ; Returns to main program.

HLT Subroutine Program Label Mnemonic MUL ADD B DCR C JNZ

MUL

RET 3.8 DELAY CALCULATIONS Through programming time delay can be introduced, which is very useful in various applications such as digital clocks, traffic controls, digital process control and other data transfer controls. Time delay can be introduced by loading the registers with some desired number and then decremented through the loops to zero value. The delay introduced in the system will depend on the clock period of the system and the number of times the instructions are executed inside the loop. To generate very small delay only one register can be used. Consider a subroutine program given below in which C-register is loaded with 10 H (decimal number 16). It is decremented in a loop to make it zero. Figure 3.8 shows the flow chart for the same. Label Mnemonic Operand No. of T-states MVI C, 10 H 7 LOOP DCR C 4 JNZ LOOP 10/7 RET 10 In this program the instruction MVI C, 10 H is executed only once and it takes 7 T-states to execute. The instruction DCR C is executed 16 times and thus takes 16 x 4 = 64 T-states, since DCR instruction takes 4 T-states for its execution. For the execution of JNZ instruction, it will go to loop 15 times, as the content of C-register will not be zero. So 15 x 10 = 150 T-states will be used in its calculation (till the content of C-register is not zero). When the contents of C-register becomes zero, it will jump to loop and it will take 7 T-states. For the execution of RET statement it will take 10 T-states. Thus total number of T-states taken for the execution of this program will be given by: Mnemonic T-states MVI C, 10 H 7 x1 = 7 DCR C 4 x 16 = 64 JNZ 10 x 15 + 1 x 7 = 157 RET 1 x 10 = 10 Total 238 T-states

67

Fig. 3.8 Total 238 T-states are used for the execution of this program. If the system 1 frequency is 2 MHz, the time taken by one T-state is sec = 0.5 µ sec . 2 x106 The total time delay introduced in the execution of this program is: Time delay = 238x 0.5 µ sec = 119 µ sec = 0.119 msec Maximum delay with this register C may be obtained by loading the number FF H (decimal number 255) in C-register. The maximum delay thus is: MVI C, FF H 7 x1 = 7 DCR C 4 x 255 = 1020 JNZ 10 x 254 + 1 x 7 = 2547 RET 1 x 10 = 10 Total 3584 T-states Time delay = 3584 x 0.5 µ sec = 1.792 msec Total delay introduced by the computer using only one register may be given in the following general form as: TDelay = [1x7 + 4 N + ( N − 1) x10 + 1x7 + 10]x time of one T-state. where N is the decimal number given with the register. = [14 N + 14]x time of one T-state. = 14[N + 1]x time of one T-state. 68

As discussed earlier the total time delay introduced by a register is 1.79 millisec if system clock frequency is 2 MHz. To introduce more time delay two registers may be used as shown in the flow chart shown in figure 3. 9, in which register B is used for the outer loop and register C is used for the inner loop.

Fig. 3.9

Label LOOP1 LOOP

Mnemonic MVI B, MVI C, DCR C

Operand MH NH

69

No. of T-states 7 7 4

JNZ LOOP 10/7 DCR B 4 JNZ LOOP1 10/7 RET 10 Total T-states used in this program will be given by: = 1x7 + M [1x7 + Nx 4 + ( N − 1) X 10 + 1x7] + ( Mx 4) + ( M − 1) x10 + 1x7 + 1x10 MVI

DCR

JNZ

JNZ

DCR

JNZ

JNZ

RET

= 1x7 + M [7 + 4 N + 10 N − 10 + 7] + 4 M + 10M − 10 + 7 + 10 = 14 + M [14 N + 4] + 14 M = 14MN + 18M + 14 This is the general form for calculating the number of T-states of the program given above, in which M is the counts in register-B (in decimal number) in outer loop and N is the counts in register-C (in decimal number) in inner loop. Total time delay is therefore given by: TDelay = (14 MN + 18M + 14 ) x Time of one T-state Example 3.8 Write a delay subroutine program for SAP-II computer to introduce a time delay of 1 millisec using only one register. Let the system frequency is 2 MHz. System frequency = 2 MHz Solution. Time delay of T-state = 0.5 µsec. We shall now find the value of N to be stored to the register. TDelay = 14[N + 1]x 0.5 µsec 1000 µsec = 14[N + 1]x0.5 µ sec 1000 N= −1 7 993 = ≅ 142 decimal number 7 142 = 8E H So the program for the delay of 1 millisec is as given below: Label Mnemonic Operand MVI C, 8E H LOOP DCR C JNZ LOOP RET

Example 3.9 Write a delay subroutine program for SAP-II computer to introduce a time delay of 10 millisec using two registers. Decimal number 10 may be stored in register B (for outer loop). Let the system frequency is 2 MHz. Solution. System frequency = 2 MHz In this case M = 1010 = 0A H N is to be calculated as: TDelay = (14 MN + 18M + 14 ) x Time of one T-state Time of T-state = 0.5 µsec 10ms = (14 x10 xN + 18 x10 + 14 )x0.5µS

70

10000µs = (140 N + 194)x0.5µS 20000 = (140 N + 194 ) 140 N = (20000 − 194) 19806 N= = 142 = 8E H 140 The Subroutine program for the required time delay is therefore given as: Label Mnemonic Operand MVI B, 0A H LOOP1 MVI C, 8E H LOOP DCR C JNZ LOOP DCR B JNZ LOOP1 RET Example 3.10 (a) What will be the time delay introduced in the computer, if the following subroutine program is executed. Assume the system frequency is 2 MHz. MVI B, 64 H LOOP1 MVI C, 8E H LOOP DCR C JNZ LOOP DCR B JNZ LOOP1 RET (b) How much maximum delay can be introduced by this subroutine program? (c) Modify this program to introduce a time delay of 1 sec. (d) Modify this program to introduce a time delay of 10 sec. Solution. In this subroutine program M = 64 H = 10010 N = 8E H = 14210 Time of one T-state = 0.5 µsec TDelay = (14 MN + 18M + 14 ) x Time of one T-state = (14MN + 18M + 14) x 0.5µsec = (14 x100 x142 + 18 x100 + 14) x 0.5µsec = (198800 + 1800 + 14) x 0.5µsec = 200614 x 0.5µsec = 100307 µsec = 100.3 msec ≅ 0.1 sec Approx. 0.1 sec delay is introduced by this subroutine program. (b) The maximum time delay that can be introduced by this subroutine program is calculated if we consider the maximum value of M and N as FF H. i.e. M = FF H = 25510 N = FF H = 25510 TDelay = (14 MN + 18M + 14 ) x Time of one T-state

= (14MN + 18M + 14) x 0.5µsec 71

(c)

= (14 x 255 x 255 + 18 x 255 + 14 ) x 0.5µsec = 914954 x 0.5µsec = 457477 µsec ≅ 0.46 sec To introduce a time delay of 1 sec, the given program can be run 10 times using one more register say A-register. The modified program is given below: Label

Mnemonic Operand MVI A, 0A H LOPP3 MVI B, 64 H LOOP2 MVI C, 8E H LOOP1 DCR C JNZ LOOP1 DCR B JNZ LOOP2 DCR A JNZ LOOP3 RET (d) To introduce a time delay of 10 sec, in the above program 64 H (10010) can be taken in place of 0A H (1010). The subroutine program will be as given below: Label Mnemonic Operand MVI A, 64 H LOPP3 MVI B, 64 H LOOP2 MVI C, 8E H LOOP1 DCR C JNZ LOOP1 DCR B JNZ LOOP2 DCR A JNZ LOOP3 RET Example 3.11 Write a program in assembly language of SAP-II computer to count continuously in hexadecimal from FF H to 00 H. Use subroutine program also to set up a one millisecond delay between each count and display the number at one of the output port. Assume the system frequency is 2 MHz. Solution. For its programming load a count 00 H in one register say B-register. Decrement the content of B-register, so that in B-register the counts are FF H. Display this count on one of the output port say 04 H. Then introduce a delay of 1 millisec in a subroutine program. After the delay, decrement the counts in B-register and proceed continuously as discussed above. The program is given below: Main Program Label Mnemonic Operand Comment MVI B, 00 H ; Loads the count 00 H in B-register. [B] ← 00H .

72

START

DCR B CALL

DELAY

MOV A, B OUT PORT 04 H JMP START Subroutine Program (Delay program of 1msec)

; Decrements the counts of Bregister. ; Calls the delay subroutine program. ; Moves the content of B to A. ; Displays the data at the output port.

Label DELAY LOOP

Mnemonic Operand MVI C 8E H DCR C JNZ LOOP RET Subroutine program is the same as discussed in example 3.7. Example 3.12 Suppose SAP-II computer can input a data (one byte) from port 2. Write an assembly language program to find if the bit 1 (A1) is zero or one. If the bit 1 is one, it should load the accumulator with ASCII Y otherwise ASCII N. The accumulator data should be available at output port 4. The hexadecimal number for ASCII Y is 59 H and for ASCII N is 4E H. Solution. Label Mnemonic Operand Comment IN 02 H ; Input a byte (data) from input port 02H. ANI 02 H ; Isolate bit A1. JZ NO ; Jump if A1 is zero. MVI A, 59 H ; Loads Y to Acc. JMP END ; Jump to END. NO MVI A, 4E H ; Loads N to Acc. END OUT 04 H ; Output is available at port 04 H. HLT ; Stop processing. Example 3.13 Write a program in assembly language of SAP-II computer to subtract a number stored in memory location 2100 H from the number in memory location 2101 H using addition method. The result should be stored in memory location 2102 H. If the result is negative, memory location should be loaded with 00 H. Solution. In this problem subtraction is to be carried out using addition method. So we have to add 2’s complement of the number in memory location 2101 H. Label Mnemonic Operand Comment LDA 2100 H ; Loads the Acc. the content stored in 2100 H. CMA ; Takes 1’s complement of the number in Acc. INR A : Acc. content is added with to get 2’s complement in Acc.

73

MOV B,

A

; Moves the Acc. content to Bregister. LDA 2101 H ; Loads the Acc. the content stored in 2101 H (second number). ADD B ; Adds 2’s complement of the number with Acc. JM END ; Jump if the sum is negative. STA 2102 H ; Stores the answer if positive. HLT ; Stop processing. END MVI A, 00 H ; Moves 00 H to Acc. STA 2102 H ; If answer is negative store 00 H to 2102 H. HLT ; Stop processing. Example 3.14 Write a program in assembly language using SAP-II instructions that inputs a byte from port 2 and determine if decimal number is even or odd. If the input byte is even load FF H otherwise 00 H to memory location 2500 H. Solution. Label Mnemonic Operand Comment IN 02 H ; Input a byte (data) from input port 02H. ANI 01 H ; Isolate bit A0. JNZ ODD ; Jump if Odd. MVI A, FF H ; Loads FF H to Acc. JMP END ; jump to END. ODD MVI A, 00 H ; Loads 00 H to Acc. END STA 2500 H ; Stores the answer in 2500 H. HLT ; Stop processing. PROBLEMS 1. 2. 3. 4. 5. 6. 7. 8.

Draw the block diagram of the architecture of SAP-II computers. Discuss the working of each block. What is the difference between the architectures of SAP-I and SAP-II computers? How the sign and zero flags work in arithmetic and logic unit of SAP-II computers? Name and discuss the five different categories in which the instruction set of SAP-II computers are divided. Name and discuss the different addressing modes to specify the instruction of SAP-II computers. Discuss Implied addressing to specify the data of instructions of SAP-II computers. Describe with examples one byte, two byte and three byte instructions of SAP-II computers. What is the difference between assembly language program and machine language program? What do you understand by mnemonics?

74

9.

10. 11.

12.

13. 14

15.

16. 17.

18. 19. 20.

How delay is introduced through software in SAP-II computers using only one register? How much maximum delay can be introduced with one register if the frequency of the clock is (i) 1 MHz (ii) 3 MHz? How much delay can be introduced using two registers in SAP-II computers, if the system frequency is 2 MHz? Write the subroutine program to introduce a delay of 1 sec using all the three registers of SAP-II computers. Further assume that the system clock frequency is 2 MHz. Write a program in assembly language using SAP-II instructions to multiply the two decimal numbers 13 and 10. The answer should be stored in memory location 2100 H. Write a program in assembly language using SAP-II instructions to complement a number lying at 2100 H memory location. Store the complement at 2101 H. Write a program in assembly language using SAP-II instructions to perform the following arithmetic operation: X + Y − Z −W where X, Y, Z and W are hexadecimal numbers stored in memory locations 2101 H to 2104 H. The final answer should be stored in 2100 H. Assume that there is no carry or borrow. Write a program in assembly language using SAP-II instructions to get 2’s complement of a number stored in memory location 2501 H. Store the answer at 2502 H . Write a program in assembly language using SAP-II instructions to add decimal numbers 70 and 36. Answer is to be stored in memory location 2100 H. Write a program in assembly language using SAP-II instructions to multiply two decimal numbers 33 and 6 and store the answer in memory location 2100 H. Use subroutine for multiplication. Write a subroutine program (in assembly language of SAP-II) to introduce a time delay of 20 msec. Let the system frequency is 2 MHz. Write a subroutine program (in assembly language of SAP-II) to introduce a time delay of 1 minute. Let the system frequency is 1 MHz. Write an assembly language program using SAP-II instructions to mask off A1 and A2 bits of a given number. Let the given number is 6E H. ___________

75

4 SAP – III In this chapter, programming model and instruction set of SAP-III computer will be discussed. After the study of this computer we will be in a position to understand the details of the popular 8-bit microprocessor 8085 with ease. 4.1 PROGRAMMING MODEL OF SAP-III COMPUTER One step head of the evolution of modern computers is the 8-bit microcomputer named as SAP-III computer. The CPU of this computer is upward compatible with 8085 microprocessor. The programming model or software model of SAP-III computer is given in figure 4.1. It consists of some more registers than SAP-II computers. In addition to Accumulator (A), B and C registers it contains four more 8-bit registers named as D, E, H and L registers. Because of these registers the flexibility in programming is much more. With special instructions the registers B, C, D, E, H and L may be used as extended register pairs B-C register pair, D-E register pair and H-L register pair, so that 16-bit data may be operated with these registers. It has 16-bit Program counter and 16-bit Stack pointer. The stack pointer is used for stack purposes which will be discussed later in this chapter.

Fig. 4.1 SAP-III computer has a four-bit flag register associated with Accumulator. The four flags are Sign flag (S), Zero flag (Z), Carry flag (CY) and Parity flag (P). Sign Flag (S)

The sign flag is set (S = 1), if accumulator content is negative and it is reset (S = 0) if accumulator content is positive. The logic circuit is the same as discussed for SAP-II computers. Zero Flag (Z) The zero flag is set (Z = 1), if accumulator content is zero and it is reset (Z = 0) if accumulator content is not zero. The logic circuit is the same as discussed for SAP-II computers. Carry Flag (CY) The carry flag (CY) is used to detect overflow in some arithmetic and logic operations. In SAP-III computer, the accumulator of CPU is only 8-bit wide. The unsigned binary numbers from 0 to 255 or signed numbers (2’s complement) from – 128 to +127 can be the content of the accumulator. The arithmetic operations addition and subtraction are performed using 2’s complement adder / subtractor circuit. The logic circuit diagram of such a 2’s complement adder / subtractor is shown in figure 4.2.

Fig. 4.2 In this circuit one input of each of the exclusive – OR gates are connected to common terminal named as SUB; this common terminal is also connected to carry bit of first full adder. During the addition, SUB terminal is kept low and for subtraction it is kept high. The working of this circuit may be described as given below. The accumulator content directly goes to full adders. The content, which is to be added to or subtracted from the accumulator content is applied to full adders through the exclusive OR gates. SUB terminal being low during the addition, so the exclusive-OR gates send directly the addend to the full adders. The full adders add the two contents. If there is any overflow, CARRY becomes high which finally sets CY flag. If on the other hand there is no overflow, CARRY is low and CY flag is reset. So CY = 1, if there is carry and CY = 0, if there is no carry. Similarly, during subtraction SUB = 1 and the exclusive OR gates converts the subtrahend to its equivalent 1’s complement. Since SUB terminal (SUB = 1) is connected to first full adder so 1’s complement of the subtrahend gets converted to its equivalent 2’s complement. For subtraction, 2’s complement of the subtrahend is added with the

77

accumulator content. If the CARRY signal is high (CARRY = 1), there is an end around carry (EAC), the final exclusive OR gate gives CY = 0 indicating there is no borrow. On the other hand, if there is no CARRY (CARRY = 0 or no EAC), carry flag CY will be set (CY = 1) indicating that there is borrow. So CY = 0 (Carry flag is restet) there is no carry or borrow. CY = 1 (Carry flag is set) there is carry or borrow. The carry flag acts as carry bit for addition and it works as borrow bit for subtraction. Parity Flag (P) In addition to sign, carry and zero flags there is also a parity flag. The parity flag is set if there are even number of 1’s in the accumulator and it is reset if there are odd number of 1’s. So P = 1 for even parity and P = 0 for odd parity. The logic circuit diagram of the parity bit generator for showing the correct parity is shown in figure 4.3.

Fig. 4.3 4.2 INSTRUCTION SET OF SAP-III COMPUTER All the instructions which have been discussed in SAP-II computers are also used in SAP-III computers. In addition to these instructions there are many more instructions which will be discussed here. The instruction set of SAP-III computers has been classified into following groups. 1. Data Transfer Group 2. Arithmetic Group 3. Branch Group 4. Stack, Input/Output and Machine Control Group

78

4.2.1

Data Transfer Group The function of data transfer group of instructions is to transfer the data from register to register, register to memory and also immediate transfer of data (given) to memory location. This group of instruction is also there in SAP-II computers but in SAPIII computers more instruction are there due to more registers. Data transfer group of instructions are given in table 4.1. These data transfer instructions can further be subdivided on the basis of modes of addressing i.e. direct, immediate and register addressing. Table 4.1 Data Transfer Group Instruction Op. AddressNo No of Flags Operation Code ing of bytes affected modes Tof state instr. s LDA address 3A Direct 13 3 None [A] ← [M address ] STA address 32 Direct 13 3 None [M address ] ← [A] MOV A, A MOV A, B MOV A, C MOV A, D MOV A, E MOV A, H MOV A, L MOV B, A MOV B, B MOV B, C MOV B, D MOV B, E MOV B, H MOV B, L MOV C, A MOV C, B MOV C, C MOV C, D MOV C, E MOV C, H MOV C, L MOV D, A MOV D, B

7F 78 79 7A 7B 7C 7D 47 40 41 42 43 44 45 4F 48 49 4A 4B 4C 4D 57 50

Register Register Register Register Register Register Register Register Register Register Register Register Register Register Register Register Register Register Register Register Register Register Register

4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 79

None None None None None None None None None None None None None None None None None None None None None None None

[A] ← [A] [A] ← [B ] [A] ← [C ] [A] ← [D] [A] ← [E ] [A] ← [H ] [A] ← [L] [B] ← [A] [B] ← [B] [B] ← [C ] [B] ← [D] [B] ← [E ] [B] ← [H ] [B] ← [L] [C ] ← [A] [C ] ← [B] [C ] ← [C ] [C ] ← [D] [C ] ← [E ] [C ] ← [H ] [C ] ← [L] [D] ← [A] [D] ← [B]

MOV D, C MOV D, D MOV D, E MOV D, H MOV D, L MOV E, A MOV E, B MOV E, C MOV E, D MOV E, E MOV E, H MOV E, L MOV H, A MOV H, B MOV H, C MOV H, D MOV H, E MOV H, H MOV H, L MOV L, A MOV L, B MOV L, C MOV L, D MOV L, E MOV L, H MOV L, L MOV A, M MOV B, M MOV C, M MOV D, M MOV E, M

51 52 53 54 55 5F 58 59 5A 5B 5C 5D 67 60 61 62 63 64 65 6F 68 69 6A 6B 6C 6D 7E 46 4E 56 5E

MOV H, M

66

MOV L, M MOV M, A

6E 77

MOV M, B

70

Register Register Register Register Register Register Register Register Register Register Register Register Register Register Register Register Register Register Register Register Register Register Register Register Register Register Register Register Register Register Register indirect Register indirect Register Register indirect Register

4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 7 7 7 7 7

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None

[D] ← [C ] [D] ← [D ] [D] ← [E ] [D] ← [H ] [D] ← [L] [E ] ← [A] [E ] ← [B ] [E ] ← [C ] [E ] ← [D] [E ] ← [E ] [E ] ← [H ] [E ] ← [L] [H ] ← [A] [H ] ← [B] [H ] ← [C ] [H ] ← [D] [H ] ← [E ] [H ] ← [H ] [H ] ← [L] [L] ← [A] [L] ← [B] [L] ← [C ] [L] ← [D] [L] ← [E ] [L] ← [H ] [L] ← [L] [A] ← [M H − L ] [A] ← [M H − L ] [A] ← [M H − L ] [A] ← [M H − L ] [A] ← [M H − L ]

7

1

None

[A] ← [M H − L ]

7 7

1 1

None None

[A] ← [M H − L ] [M H − L ] ← [A]

7

1

None

[M H − L ] ← [B]

80

MOV M, C

71

MOV M, D

72

MOV M, E

73

MOV M, H

74

MOV M, L

75

MVI A, data MVI B, data MVI C, data MVI D, data MVI E, data MVI H, data MVI L, data MVI M, data

3E 06 0E 16 1E 26 2E 36

Indirect Register indirect Register indirect Register indirect Register indirect Register indirect Immediate Immediate Immediate Immediate Immediate Immediate Immediate Immediate

7

1

None

[M H − L ] ← [C ]

7

1

None

[M H − L ] ← [D]

7

1

None

[M H − L ] ← [E ]

7

1

None

[M H − L ] ← [H ]

7

1

None

[M H − L ] ← [L]

7 7 7 7 7 7 7 10

2 2 2 2 2 2 2 2

None None None None None None None None

[A] ← data [B] ← data [C ] ← data [D] ← data [E ] ← data [H ] ← data [L] ← data [M H − L ] ← data

(a) Direct Data Transfer Instructions There is basically two direct data transfer instructions for SAP-III computers which are the same used in SAP-II computers. These are: (i) LDA address This is mnemonic for Loads the accumulator direct. It transfers the content stored in the addressed memory location (given by address) to accumulator. [A] ← [M address ] No flag is affected in this instruction. It is three byte instruction. For example if 2AH data is stored in memory location 2500H before the execution of LDA 2500H instruction, then after the execution of this instruction, the data 2AH will be transferred to accumulator. i.e. [A] ← 2 A (ii) STA address This is mnemonic for Stores the accumulator direct. It transfers the content stored in the accumulator to addressed memory location (given by address). [M address ] ← [A] No flag is affected in this instruction. It is also three byte instruction. For example if 16H data is stored in the accumulator before the execution of STA 2100H instruction, then after the execution of this instruction, the data 16H will be transferred to the addressed memory location. i.e. [M 2100 ] ← 16 (b) Register Data Transfer Instructions

81

These instructions transfer 8-bit data stored in one register to other register. The registers in SAP-III computer are A, B, C, D, E, H and L so the data stored in one of these registers may be transferred to other register. The format for this data transfer instruction is given as: (Move Register) MOV reg1, reg2 where reg1 = A, B, C, D, E, H or L reg2 = A, B, C, D, E, H or L This instruction copies (transfers) the content stored in reg2 to reg1. [reg1] ← [reg 2] Following are the possible combinations of MOV instruction. MOV A, A MOV B, A MOV A, B MOV B, B MOV A, C MOV B, C MOV A, D MOV B, D MOV A, E MOV B, E MOV A, H MOV B, H MOV A, L MOV B, L MOV MOV MOV MOV MOV MOV MOV

C, A C, B C, C C, D C, E C, H C, L

MOV MOV MOV MOV MOV MOV MOV

D, A D, B D, C D, D D, E D, H D, L

MOV MOV MOV MOV MOV MOV MOV

E, A E, B E, C E, D E, E E, H E, L

MOV MOV MOV MOV MOV MOV MOV

H, A H, B H, C H, D H, E H, H H, L

MOV L, A MOV L, B MOV L, C MOV L, D MOV L, E MOV L, H MOV L, L These instructions are of one byte instruction and no flag is affected in these instructions.

82

For example if L = 23 H before the execution of instruction MOV C, L then after the execution of this instruction 23 H data in register L will be transferred to register C. i.e. [L] ← 23H (c) Register Indirect Data Transfer Instructions In SAP-III computers, there are some register indirect data transfer instructions in which H-L register pair acts like ‘data pointer’. The data pointer is represented by M which denotes the memory location whose address is given in the H-L register pair. It is basically represented by M HL . For example H L = 2500 H then M ⇒ M HL represents the memory location whose address is 2500 H. It indicates the memory location M 2500 . The instructions related to register immediate data transfer are given as: (Moves register from memory) (i) MOV reg, M where reg = A, B, C, D, E, H or L This instruction is indirect read instruction. It moves / copies the data stored in memory location whose address is given in H-L register pair, to the given register. i.e. [reg ] ← [M HL ] The possible combinations of this instruction are: MOV A, M MOV B, M MOV C, M MOV D, M MOV E, M MOV H, M MOV L, M For example consider 12H data is stored in the memory location whose address is given in H-L register pair (i.e. H-L = 2500H). After the execution of the instruction MOV B, M the data 12H will be stored in B register. [B] ← 12 These are one byte instruction and no flag is affected in these instructions. (ii) MOV M, reg (Moves memory from register) where reg = A, B, C, D, E, H or L This instruction moves / copies the data in the given register to the memory location addressed by H-L register pair. i.e. [M HL ] ← [reg ] It performs reverse work of MOV reg, M instruction. The possible combinations of this instruction are: MOV M, A MOV M, B MOV M, C MOV M, D MOV M, E MOV M, H

83

MOV M, L For example let D = 4E H H = 23 H L = 00 H Then after execution of the instruction MOV M, D will produce the result: [M 2300 ] ← 4 E These are also one byte instructions and no flag is affected in these instructions. (d) Immediate Data Transfer Instructions The format for immediate data transfer instructions is (Move Immediate) MVI reg, data where reg = A, B, C, D, E, H, L orM This instruction transfers the given data to the register (reg). [reg ] ← data The possible combinations of move immediate instruction are given below: MVI A, data MVI B, data MVI C, data MVI D, data MVI E, data MVI H, data MVI L, data MVI M, data For example MVI E, 1AH means the given data 1AH will be copied into the register E. [E ] ← 1A Also MVI M, 2BH means the given data 2BH will be copied into the memory location whose address is given in H-L register pair. If H = 21 H L = 00 H then [M 2100 ] ← 2 B All these instructions are two byte instructions and no flag is affected. 4.2.2 Arithmetic Group of Instructions This group of instructions (given in table 4.2) includes the instructions for addition and subtraction. Some of these instructions are the same as discussed in SAP-II computer. Table 4.2 Arithmetic Group Instruction

ADD A ADD B ADD C ADD D ADD E

Op. Code

87 80 81 82 83

Addressing modes

No of TState s

No of bytes of instr.

Flags affected

Register Register Register Register Register

4 4 4 4 4

1 1 1 1 1

All All All All All

84

Operation

[A] ← [A] + [A] [A] ← [A] + [B] [A] ← [A] + [C ] [A] ← [A] + [D] [A] ← [A] + [E ]

ADD H ADD L ADD M

84 85 86

ADI data ADC A ADC B ADC C ADC D ADC E ADC H ADC L ADC M

C6 8F 88 89 8A 8B 8C 8D 8E

ACI data DAD B DAD D DAD H SUB A SUB B SUB C SUB D SUB E SUB H SUB L SUB M

CE 09 19 29 97 90 91 92 93 94 95 96

SUI data SBB A SBB B SBB C SBB D SBB E SBB H SBB L SBB M

D6 9F 98 99 9A 9B 9C 9D 9E

SBI data

DE

Register Register Register indirect Immediate Register Register Register Register Register Register Register Register indirect Immediate Register Register Register Register Register Register Register Register Register Register Register indirect Immediate Register Register Register Register Register Register Register Register indirect Immediate

4 4 7

1 1 1

All All All

[A] ← [A] + [H ] [A] ← [A] + [L] [A] ← [A] + [M H − L ]

7 4 4 4 4 4 4 4 7

2 1 1 1 1 1 1 1 1

All All All All All All All All All

[A] ← [A] + data [A] ← [A] + [A] + CY [A] ← [A] + [B] + CY [A] ← [A] + [C ] + CY [A] ← [A] + [D] + CY [A] ← [A] + [E ] + CY [A] ← [A] + [H ] + CY [A] ← [A] + [L] + CY [A] ← [A] + [M H − L ] + CY

7 10 10 10 4 4 4 4 4 4 4 7

2 1 1 1 1 1 1 1 1 1 1 1

All CY CY CY All All All All All All All All

7 4 4 4 4 4 4 4 7

2 1 1 1 1 1 1 1 1

All All All All All All All All All

[A] ← [A] − data [A] ← [A] − [A] − CY [A] ← [A] − [B ] − CY [A] ← [A] − [C ] − CY [A] ← [A] − [D] − CY [A] ← [A] − [E ] − CY [A] ← [A] − [H ] − CY [A] ← [A] − [L] − CY [A] ← [A] − [M H −L ] − CY

7

2

All

[A] ← [A] − data − CY

85

[A] ← [A] + data + CY BC ← BC + BC DE ← DE + DE HL ← HL + HL [A] ← [A] − [A] [A] ← [A] − [B] [A] ← [A] − [C ] [A] ← [A] − [D] [A] ← [A] − [E ] [A] ← [A] − [H ] [A] ← [A] − [L] [A] ← [A] − [M H − L ]

INR A

3C

Register

4

1

INR B

04

Register

4

1

INR C

0C

Register

4

1

INR D

14

Register

4

1

INR E

1C

Register

4

1

INR H

24

Register

4

1

INR L

2C

Register

4

1

INR M

34

10

1

INX B INX D INX H DCR A

03 13 23 3D

Register indirect Register Register Register Register

6 6 6 4

1 1 1 1

DCR B

05

Register

4

1

DCR C

0D

Register

4

1

DCR D

15

Register

4

1

DCR E

1D

Register

4

1

DCR H

25

Register

4

1

DCR L

2D

Register

4

1

DCR M

35

7

1

DCX B DCX D DCX H RLC

0B 1B 2B 07

Register indirect Register Register Register ---

6 6 6 4

1 1 1 1

All but not CY All but not CY All but not CY All but not CY All but not CY All but not CY All but not CY All but not CY None None None All but not CY All but not CY All but not CY All but not CY All but not CY All but not CY All but not CY All but not CY None None None CY

RAL RRC

17 0F

-----

4 4

1 1

CY CY

RAR

1F

---

4

1

CY

86

[A] ← [A] + 1 [B] ← [B] + 1 [C ] ← [C ] + 1 [D] ← [D] + 1

[E ] ← [E ] + 1 [H ] ← [H ] + 1 [L] ← [L] + 1 [M H − L ] ← [M H − L ] + 1 BC ← BC + 1 DE ← DE + 1 HL ← HL + 1 [A] ← [A] − 1

[B] ← [B] − 1

[C ] ← [C ] − 1 [D] ← [D] − 1 [E ] ← [E ] − 1 [H ] ← [H ] − 1 [L] ← [L] − 1

[M H − L ] ← [M H − L ] − 1 BC ← BC − 1 DE ← DE − 1 HL ← HL − 1 Rotate left through carry Rotate all left Rotate right through carry Rotate all right

(a)

Add instructions Following are the add instructions: (i) ADD reg (Add register) where reg = A, B, C, D, E, H or L. It adds the content stored in given register with the accumulator. The result of this addition is stored in accumulator. [A] ← [A] + [reg ] All the flags are affected with this ‘ADD reg’ instruction. The possible combinations of this instruction are as given below: ADD A ADD B ADD C ADD D ADD E ADD H ADD L Suppose before the execution of the instruction ADD E A = 10101111 E = 10110101 CY = 0 , S = 1 , Z = 0 and P = 1 then after the execution of the instruction ADD E we get the following result: A = 1 0 1 0 1 1 1 1 E = 1 0 1 1 0 1 0 1 _____________________________ A = 1 0 1 1 0 0 1 0 0 CY The flags will be affected as; CY = 1 , S = 0 , Z = 0 and P = 0 Since there is a final carry. CY = 1 Since Acc content is positive as MSB is zero. S =0 Since Acc content is non zero. Z =0 Since Acc content has odd parity. P=0

(ii) ADD M (Add Memory) This instruction is one byte instruction and adds the content of memory location whose address is given in H-L register pair with the accumulator and the answer is stored in accumulator. [A] ← [A] + [M HL ] In this instruction too all flags are affected. This instruction is similar to ADD reg. For example let A = 40 H H = 21 H L = 00 H and M 2100 = 3 AH Then after execution of the instruction ADD M will produce the result: A = 7A H All flag will, however, be affected as per the instruction. (iii) ADI data (Adds immediately the data)

87

It immediately adds the given data with the accumulator and the answer will be stored in Accumulator. [A] ← [A] + data This is a two-byte instruction. All flags will be affected with this instruction similar to ADD reg instruction. (iv) ADC instructions The format for ADC instruction is ADC reg (Add with carry) where reg = A, B, C, D, E, H or L. It adds the content stored in given register and content of CY flag with the content of accumulator. The result of this addition is stored in accumulator. [A] ← [A] + [reg ] + [CY ] All the flags are affected with this ‘ADC reg’ instruction. The possible combinations of this instruction are as given below: ADC A ADC B ADC C ADC D ADC E ADC H ADC L Suppose before the execution of the instruction ADC D A = 10101001 D = 10111101 CY = 1 , S = 1 , Z = 0 and P = 1 then after the execution of the instruction ADD D we get the following result: CY = 1 A = 1 0 1 0 1 0 0 1 D = 1 0 1 1 1 1 0 1 _____________________________ A = 1 0 1 1 0 0 1 1 1 CY All flags will be affected. (v) ADC M (Add Memory with Carry) This instruction is one byte instruction and adds the content of memory location whose address is given in H-L register pair to the accumulator with carry and the answer is stored in accumulator. [A] ← [A] + [M HL ] +CY In this instruction too all flags are affected. This instruction is similar to ADD reg. For example let A = 50 H CY = 1 H = 25 H L = 00 H and M 2500 = 3BH Then after execution of the instruction ADC M will produce the result: A = 8C H All flag will, however, be affected as per the result.

88

(vi) ACI data (Adds immediately the data with Carry) It immediately adds the given data to the accumulator with carry and the answer will be stored in Accumulator. [A] ← [A] + data +CY This is a two-byte instruction. All flags will be affected with this instruction. (vii) DAD Instruction The format for this instruction is DAD rp (Double Add) where rp stands for register pair. It may be B, D or H. rp as B represents B-C register pair, rp as D represents D-E register pair, rp as H represents H-L register pair. This instruction adds the contents of given register pair with the contents of H-L register pair. The answer will be stored in H-L register pair. [HL] ← [HL] + [rp] This instruction has the following combinations: DAD B [HL] ← [HL] + [BC ] DAD D [HL] ← [HL] + [DE ] DAD H [HL] ← [HL] + [HL] For example before the execution of the instruction DAD D, we have the following data in different registers. DE = 2AB6 H HL = 012 7 H After the execution of this instruction we HL = 2BDD H Only carry flag will be affected in this instruction. (b) Subtract Instructions Following are the subtract instructions: (i) SUB reg (Subtract Register) where reg = A, B, C, D, E, H or L. It subtracts the contents stored in given register from the accumulator. The result of this subtraction is stored in accumulator. [A] ← [A] − [reg ] All the flags are affected with this ‘SUB reg’ instruction. The possible combinations of this instruction are as given below: SUB A SUB B SUB C SUB D SUB E SUB H SUB L Suppose before the execution of the instruction SUB D A = 10101111 89

D = 10110101 CY = 0 , S = 1 , Z = 0 and P = 1 then after the execution of the instruction SUB D we get the following result: A = 1 0 1 0 1 1 1 1 D = 1 0 1 1 0 1 0 1 _____________________________ A = 1 1 1 1 1 1 0 1 0 CY All flags will be affected as per the accumulator contents. (ii) SUB M (Subtract Memory) This instruction is one byte instruction and subtracts the contents of memory location whose address is given in H-L register pair from the accumulator and the answer is stored in accumulator. [A] ← [A] − [M HL ] In this instruction too all flags are affected. For example let A = 56 H H = 22 H L = 01 H and M 2201 = 2CH Then after execution of the instruction SUB M will produce the result: A = 2A H All flag will however be affected as per the instruction. (iii) SUI data (Subtracts immediately the data) It immediately subtracts the given data with the accumulator contents and the answer will be stored in Accumulator. [A] ← [A] − data This is a two-byte instruction. All flags will be affected with this instruction. (iv) SBB reg (Subtract with Borrow) where reg = A, B, C, D, E, H or L. This instruction subtracts the contents stored in given register from the accumulator with borrow. The answer will be stored in accumulator. [A] ← [A] − [reg ] − [CY ] All the flags are affected in the operation of this instruction. The possible combinations of this instruction are as given below: SBB A SBB B SBB C SBB D SBB E SBB H SBB L Suppose before the execution of the instruction SBB H A = 10101111 H = 10110101 CY = 0 , S = 1 , Z = 0 and P = 1 then after the execution of the instruction SUB H we get the following result: A = 1 0 1 0 1 1 1 1

90

H = CY =

1 0 1 1 0 1 0 1 1 ____________________________ A = 1 1 1 1 1 1 0 0 1 CY All flags will be affected as per the accumulator contents. (v) SBB M (Subtract memory with Borrow) Similar to SBB reg, this instruction subtracts the content already stored in memory location addressed by H-L register pair with borrow bit (carry flag) from the accumulator contents and the answer is stored in accumulator. [A] ← [A] − [M HL ] − [CY ] All flags will be affected as per the accumulator contents. (vi) SBI data (Subtract immediate with Borrow) SBI data instruction subtracts the given data with borrow bit (carry flag) from the accumulator contents and it stores the answer in accumulator. [A] ← [A] − data − [CY ] All flags will be affected as per the accumulator contents. (c) Increment Instructions The increment instructions used in SAP-III computer are given below: (i) INR reg (Increment Register) where reg = A, B, C, D, E, H or L. It increments the contents of given register by one and answer is stored in the given register. [reg ] ← [reg ] + 1 The possible combinations of this instruction are: INR A INR B INR C INR D INR E INR H INR L These instructions do not affect the CY flag but affect all other flags. For example if Z = 0, S = 1, and CY = 0 and contents of register is C = 1 1 1 1 1 1 1 1 , then after the execution of the instruction INR C we have: C= 00000000 Z = 1, S = 0, and CY = 0 (ii) INR M (Increment Memory) It increments the contents of memory location addressed by H-L register pair by 1 and stores the answer in the addressed memory location. [M HL ] ← [M HL ] + 1 Similar to INR reg, all flags except carry flag will be affected after the execution of this instruction. (iii) INX rp (Increment register pair)

91

where rp is the register pair as B-C register pair, D-E register pair and H-L register pair. This instruction increments the contents given in register pair by one and the result is stored in the given register pair. [rp] ← [rp] + 1 The possible combinations of this instruction are: INX B INX D INX H No flag is affected with the execution of this instruction. For example if H = FF H and L = FF H CY = 1, Z = 0 After the execution of the instruction INX H, we have the contents in H-L pair as: H = 25 H and L = 01 H ; the contents of the flags will not be affected. So the carry and zero flag will have the same value as having before the execution of this instruction i.e. CY = 1, Z = 0 (d) Decrement Instructions The decrement instructions used in SAP-III computer are given below: (i) DCR reg (Decrement Register) where reg = A, B, C, D, E, H or L. It decrements the contents of given register by one and answer is stored in the given register. [reg ] ← [reg ] − 1 The possible combinations of this instruction are: DCR A DCR B DCR C DCR D DCR E DCR H DCR L These instructions do not affect the CY flag but affect all other flags. For example if Z = 0, S = 1, and CY = 0 and contents of D register is D = 0 0 0 0 0 0 0 0 , then after the execution of the instruction DCR D we have: C= 11111111 Z = 0, S = 1, and CY = 0 (ii) DCR M (Decrement Memory) It decrements the contents of memory location addressed by H-L register pair by 1 and stores the answer in the addressed memory location. [M HL ] ← [M HL ] − 1 Similar to DCR reg, all flags except carry flag will be affected after the execution of this instruction. (iii) DCX rp (Increment register pair) where rp is the register pair as B-C register pair, D-E register pair and H-L register pair. This instruction decrements the contents given in register pair by one and the result is stored in the given register pair. [rp] ← [rp] − 1 92

The possible combinations of this instruction are: DCX B DCX D DCX H No flag will be affected with the execution of this instruction like INX rp. For example if D = 23 H and E = 00 H After the execution of the instruction DCX D, we have the contents in D-E pair as: D = 22 H and E = FF H (e) Rotate Instructions In rotate instructions, the accumulator contents are shifted either left or right. In some instructions shifting may be through CY flag or without CY flag. Following are the rotate instructions. (i) RLC (Rotate Accumulator Left) In this instruction, the bits of the accumulator contents are shifted or rotated left. The LSB of the accumulator is changed as MSB (before the execution). The CY flag is modified as MSB (before the execution).

Fig. 4.4 For example A = AE H and CY = 0, before the execution of the instruction RLC. After the execution of the instruction MSB is saved in CY flag and also in the LSB of the accumulator. The other bits are shifted left as shown in figure 4.4. i.e. [An+1 ] ← [An ]

[A0 ] ← [A7 ]

also [CY ] ← [A7 ] Only carry flag CY will be affected in this instruction and all other flags will be unaffected. (ii) RAL (Rotate Accumulator Left Through Carry) In this instruction, the bits of the accumulator contents will be shifted / rotated left through carry. The content of carry flag CY will be stored in LSB of the accumulator and MSB of the accumulator will be stored in CY flag. All other bits of the accumulator will be shifted to the left. For example if A = 6A H and CY = 1 before the execution of RAL instruction, then after the execution of this instruction the accumulator contents will be shifted as shown in figure 4.5.

93

Fig. 4.5 In this instruction too only carry flag will be affected. (iii) RRC (Rotate Accumulator Right) In this instruction, all the bits of accumulator are shifted or rotated right. The MSB of the accumulator is changed as LSB (before the execution). The CY flag is modified as MSB (before the execution). For example A = 93 H and CY = 0, before the execution of the instruction RRC. After the execution of this instruction LSB is saved in CY flag and also in the MSB of the accumulator. The other bits are shifted left as shown in figure 4.6.

Fig. 4.6 In this instruction only carry flag CY will be affected and all other flags will be unaffected. (iv) RAR (Rotate Accumulator Right Through Carry) In this rotate instruction, all the bits of the accumulator contents will be shifted / rotated right through carry. The content of carry flag CY will be stored in MSB of the accumulator and LSB of the accumulator will be stored in CY flag; and all other bits of the accumulator will be shifted to the right.

94

For example if A = 76 H and CY = 1 before the execution of RAR instruction, then after the execution of this instruction the accumulator contents will be shifted as shown in figure 4.7.

Fig. 4.7 In this instruction too only carry flag will be affected. 4.2.3 Logic Transfer Group The logic group of instructions operates on registers, memory and conditional flags. This group of instructions contains ANDing, ORing, XORing, complementing and comparing of data (table 4.3). Table 4.3 Logic Transfer Group Instruction

Op. Code

Addressing modes

No of Tstates

No of bytes of instr.

Flags affected

All (CY=0) All (CY=0) All (CY=0) All (CY=0) All (CY=0) All (CY=0) All (CY=0) All (CY=0) All (CY=0)

ANA A

A7

Register

4

1

ANA B

A0

Register

4

1

ANA C

A1

Register

4

1

ANA D

A2

Register

4

1

ANA E

A3

Register

4

1

ANA H

A4

Register

4

1

ANA L

A5

Register

4

1

ANA M

A6

7

1

ANI data

E6

Register Indirect Immediate

7

2

95

Operation

[A] ← [A].AND.[A] [A] ← [A].AND.[B] [A] ← [A].AND.[C ]

[A] ← [A].AND.[D] [A] ← [A].AND.[E ] [A] ← [A]. AND.[H ] [A] ← [A]. AND.[L]

[A] ← [A]. AND.[M H − L ] [A] ← [A]. AND.data

ORA A

B7

Register

4

1

ORA B

B0

Register

4

1

ORA C

B1

Register

4

1

ORA D

B2

Register

4

1

ORA E

B3

Register

4

1

ORA H

B4

Register

4

1

ORA L ORA M

B5 B6

4 7

1 1

ORI data

F6

Register Register Indirect Immediate

7

2

XRA A

AF

Register

4

1

XRA B

A8

Register

4

1

XRA C

A9

Register

4

1

XRA D

AA

Register

4

1

XRA E

AB

Register

4

1

XRA H

AC

Register

4

1

XRA L

AD

Register

4

1

XRA M

AE

7

1

XRI data

EE

Register Indirect Immediate

7

2

CMP A CMP B CMP C CMP D CMP E CMP H CMP L CMP M

BF B8 B9 BA BB BC BD BE

4 4 4 4 4 4 4 7

1 1 1 1 1 1 1 1

All (CY=0) All (CY=0) All (CY=0) All (CY=0) All (CY=0) All (CY=0) All All (CY=0) All (CY=0) All (CY=0) All (CY=0) All (CY=0) All (CY=0) All (CY=0) All (CY=0) All (CY=0) All (CY=0) All (CY=0) All All All All All All All All

CPI data

FE

7

2

All

Register Register Register Register Register Register Register Register Indirect Immediate

96

[A] ← [A].OR.[A] [A] ← [A].OR.[B] [A] ← [A].OR.[C ] [A] ← [A].OR.[D]

[A] ← [A].OR.[E ] [A] ← [A].OR.[H ] [A] ← [A].OR.[L] [A] ← [A].OR.[M H − L ] [A] ← [A].OR.data [A] ← [A] ⊕ [A]

[A] ← [A] ⊕ [B] [A] ← [A] ⊕ [C ] [A] ← [A] ⊕ [D] [A] ← [A] ⊕ [E ] [A] ← [A] ⊕ .[H ] [A] ← [A] ⊕ [L]

[A] ← [A] ⊕ [M H − L ] [A] ← [A] ⊕ data

CMA

2F

---

4

1

None

[A] ← [A]

CMC STC

3F 37

-----

4 4

1 1

CY CY

CY ← CY CY ← 1

The details of these instructions are given below: (a) Logical Instructions (i) ANA reg (AND register) where reg = A, B, C, D, E, H or L. In this instruction each bit of the given register contents are ANDed with each bit of the accumulator contents (bit by bit). The result is saved in the accumulator. It does not affect the contents of the given register. [A] ← [A].AND.[reg ] The possible combinations of this instruction are: AND A ANA B ANA C ANA D ANA E ANA H ANA L The ANA reg instruction clears (resets) the CY flag and all other flags are modified according to the data conditions of the result. This instruction is one byte instruction. Let A = 73 H C = C3 H CY = 1 before the execution of the instruction ANA C. Then after the instruction is executed we get: A= 0 1 1 1 0 0 1 1 CY = 1 C= 1 1 0 0 0 0 1 1 __________________________ A= 0 1 0 0 0 0 1 1

CY = 0

(ii) ANA M (AND Memory) In this instruction each bit of the data stored in the memory location addressed by H-L register pair are ANDed with each bit of the accumulator contents (bit by bit). The result is stored in the accumulator like ANA reg. [A] ← [A]. AND.[M H − L ] Similar to ANA reg instruction data of the memory location addressed by H-L register pair will not be affected; the carry flag will, however, be reset after the execution of this instruction and other flags will be affected as per the data in the accumulator. Let A = 19 H H = 25 H L = 00 H M 2500 = 37 H and CY = 1 before the execution of the instruction ANA M. Then after the instruction is executed we get:

97

A=

0 0 0 1 1 0 0 1

CY = 1

M 2500 = 0 0 1 1 0 1 1 1 __________________________ A= 0 0 0 1 0 0 0 1 CY = 0 (iii) ANI data (AND Immediate) In this instruction each bit of the given data is immediately ANDed with each bit of the accumulator contents (bit by bit). The result is stored in the accumulator. The difference between ANA reg and ANI data instruction is that in ANA reg the data given in the register where as in the ANI data instruction, the data is given with the instruction itself. [A] ← [A]. AND.data The carry flag will be reset after the execution of this instruction and other flags will be affected as per the result. For example, if A = AB H and CY = 1 before the execution of ANI 06 H, then after the execution of this instruction we have: A= 1 0 1 0 1 0 1 1 CY = 1

data = 0 0 0 0 0 1 1 0 __________________________ A= 0 0 0 0 0 0 1 0 CY = 0 (iv) ORA reg (OR register) where reg = A, B, C, D, E, H or L. In this instruction each bit of the given register contents are ORed with each bit of the accumulator contents (bit by bit). The result is saved in the accumulator. It does not affect the contents of the given register. [A] ← [A].OR.[reg ] The possible combinations of this instruction are: ORA A ORA B ORA C ORA D ORA E ORA H ORA L The ORA reg instruction clears (resets) the CY flag and all other flags are modified according to the data conditions of the result. This instruction is one byte instruction. Let A = 73 H C = C3 H CY = 1 before the execution of the instruction ORA B. Then after the instruction is executed we get: A= 0 1 1 1 0 0 1 1 CY = 1 B= 1 1 0 0 0 0 1 1 __________________________ A= 1 1 1 1 0 0 1 1 98

CY = 0

(v) ORA M (OR Memory) In this instruction each bit of the data stored in the memory location addressed by H-L register pair are ORed with each bit of the accumulator contents (bit by bit). The result is stored in the accumulator. [A] ← [A].OR.[M H − L ] Similar to ORA reg instruction data of the memory location addressed by H-L register pair will not be affected; the carry flag will however be reset after the execution of this instruction and other flags will be affected as per the data in the accumulator. Let A = 19 H H = 21 H L = 00 H M 2100 = 37 H and CY = 1 before the execution of the instruction ORA M. Then after the instruction is executed we get: A= 0 0 0 1 1 0 0 1 CY = 1 M 2100 = 0 0 1 1 0 1 1 1 __________________________ A= 0 0 1 1 1 1 1 1 CY = 0 (vi) ORI data (OR Immediate) In this instruction each bit of the given data is immediately ORed with each bit of the accumulator contents (bit by bit). The result is stored in the accumulator. [A] ← [A].OR.data The carry flag will be reset after the execution of this instruction and other flags will be affected as per the result. For example, if A = AB H and CY = 1 before the execution of ANI 16 H, then after the execution of this instruction we have: A= 1 0 1 0 1 0 1 1 CY = 1 data = 0 0 0 1 0 1 1 0 __________________________ A= 1 0 1 1 1 1 1 1 CY = 0 (vii) XRA reg (Exclusive OR register) where reg = A, B, C, D, E, H or L. In this instruction each bit of the given register contents are XORed with each bit of the accumulator contents (bit by bit). The result is saved in the accumulator. It does not affect the contents of the given register. [A] ← [A]. XOR.[reg ] The possible combinations of this instruction are: XRA A XRA B XRA C XRA D XRA E XRA H XRA L

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The XRA reg instruction clears (resets) the CY flag and all other flags are modified according to the data conditions of the result. This instruction is one byte instruction. Let A = 73 H D = C3 H CY = 1 before the execution of the instruction XRA D. Then after the instruction is executed we get: A= 0 1 1 1 0 0 1 1 CY = 1 D= 1 1 0 0 0 0 1 1 __________________________ A= 1 0 1 1 0 0 0 0 CY = 0 (viii) XRA M (Exclusive OR Memory) In this instruction each bit of the memory location addressed by H-L register pair are XORed with each bit of the accumulator contents (bit by bit). The result is stored in the accumulator. [A] ← [A]. XOR.[M H − L ] The carry flag will be reset after the execution of this instruction and other flags will be affected as per the data in the accumulator. Let A = 19 H H = 22 H L = 00 H and CY = 1 M 2200 = 37 H before the execution of the instruction ORA M. Then after the instruction is executed we get: A= 0 0 0 1 1 0 0 1 CY = 1

M 2200 = 0 0 1 1 0 1 1 1 __________________________ A= 0 0 1 0 1 1 1 0 CY = 0 (ix) XRI data (Exclusive OR Immediate) In this instruction each bit of the given data is immediately XORed with each bit of the accumulator contents (bit by bit). The result is stored in the accumulator. [A] ← [A]. XOR.data The carry flag will be reset after the execution of this instruction and other flags will be affected as per the result. For example, if A = AB H and CY = 1 before the execution of ANI 12 H, then after the execution of this instruction we have: A= 1 0 1 0 1 0 1 1 CY = 1 data = 0 0 0 1 0 0 1 0 __________________________ A= 1 0 1 1 1 0 0 1 CY = 0 (x) CMA (Complement Accumulator) This is one byte implied addressing instruction as no operand is required with the instruction. The execution of this instruction inverts each bit of the accumulator contents and the result is saved in the accumulator. Basically it produces 1’s complement of the accumulator contents. No flag is affected with this instruction.

100

[A] ← [A] For example, if A = 0B H before the execution of CMA instruction, then after the execution of this instruction we have: A= 0 0 0 0 1 0 1 1 = 1 1 1 1 0 1 0 0 __________________________ A= 1 1 1 1 0 1 0 0 (F4) (b) Compare Instructions (i) CMP reg (Compare Register) The contents of the given register are compared with the accumulator contents. In fact the contents of the register are subtracted from the contents of accumulator and the accumulator contents remain unchanged. However, as a result of the subtraction the flags are modified as per the result. The zero flag Z is set if [ A] = [reg ] otherwise reset. Similarly, carry flag CY is set if [A] < [reg ] otherwise reset. The possible combinations of CMP reg are given below: CMP A CMP B CMP C CMP D CMP E CMP H CMP L To illustrate the above instruction let us consider the following assembly language program. Label Mnemonics Operand MVI B, 00 H MVI A, 09 H LOOP INR B CMP B JNZ LOOP ------------In this program before the loop A = 09 H and B = 00 H. The value of B will increase by each go in the loop and each time it is compared with accumulator contents. Till the contents of B register are not equal to the contents of Accumulator, the computer will execute the instructions inside the loop. When the value of B register becomes equal to 09 H, the zero flag will be set and it will allow coming out of the loop to execute the next instructions. (ii) CMP M (Compare Memory)

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It is similar to CMP reg instruction with the difference that the contents of the addressed memory location will be compared by the accumulator contents. The flags will be modified as per the result. (iii) CPI data (Compare immediate with data) It is similar to CMP instruction with the difference that the data is directly given with the instruction. In this instruction the given data is compared with the accumulator contents. The flags will be modified as per the result. (c) Miscellaneous Logical Instructions (i) CMC (Complement the carry) This instruction complements the carry flag. CY ← CY If CY = 1 before the execution of CMC instruction, the carry flag will be reset (CY = 0) after the execution of this instruction. Similarly, If CY = 0 before the execution of CMC instruction, the carry flag will be set (CY = 1) after the execution of this instruction. In this only carry flag will be affected and all other flags will not be affected. (ii) STC (Set the carry) It sets the carry flag. CY ← 1 The carry flag will be set (CY = 1) irrespective of the carry flag is set or reset before the execution of this instruction STC. Only carry flag gets affected with this instruction. 4.2.4 Branch Group This group of instructions changes the normal sequence of the program. The branch instructions include JUMP, CALL and RETURN instructions, which are further sub-divided as unconditional and conditional JUMP, CALL and RETURN instructions. Table 4.4 Branch Group Instruction

JMP addr JNZ addr JZ addr JNC addr JC addr JM addr JP addr JPO addr JPE addr CALL addr

Op. Code

C3 C2 CA D2 DA FA F2 E2 EA CD

Addressing modes

No of Tstates

No of bytes of instr.

Flags affected

Immediate Immediate Immediate Immediate Immediate Immediate Immediate Immediate Immediate Immediate

10 10/7 10/7 10/7 10/7 10/7 10/7 10/7 10/7 18

3 3 3 3 3 3 3 3 3 3

None None None None None None None None None None

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Operation

[PC ] ← [addr ] [PC ] ← [addr ] if Z=0. [PC ] ← [addr ] if Z=1. [PC ] ← [addr ] if CY=0. [PC ] ← [addr ] if CY=1. [PC ] ← [addr ] if S=1. [PC ] ← [addr ] if S=0. [PC ] ← [addr ] if P=0. [PC ] ← [addr ] if P=1. Calls subroutine program.

CNZ addr

C4

Immediate

18/9

3

None

CZ addr

CC

Immediate

18/9

3

None

CNC addr

D4

Immediate

18/9

3

None

CC addr

DC

Immediate

18/9

3

None

CM addr

FC

Immediate

18/9

3

None

CP addr

F4

Immediate

18/9

3

None

CPO addr

FE

Immediate

18/9

3

None

CPE addr

EC

Immediate

18/9

3

None

RNZ

C0

12/6

1

None

RZ

C8

12/6

1

None

RNC

D0

12/6

1

None

RC

D8

12/6

1

None

RM

F8

12/6

1

None

RP

F0

12/6

1

None

RPO

E0

12/6

1

None

RPE

E8

Register indirect Register indirect Register indirect Register indirect Register indirect Register indirect Register indirect Register indirect

12/6

1

None

Calls subroutine program if Z=1. Calls subroutine program if Z=0. Calls subroutine program if CY=1. Calls subroutine program if CY=0. Calls subroutine program if S=1. Calls subroutine program if S=0. Calls subroutine program if P=0. Calls subroutine program if P=1. Returns to main program if Z=1. Returns to main program if Z=0. Returns to main program if CY=0. Returns to main program if CY=1. Returns to main program if S=1. Returns to main program if S=0. Returns to main program if P=0. Returns to main program if P=1.

(a) Unconditional Jump Instructions (i) JMP address (label) (Jump to Address) This is an unconditional jump instruction. With the execution of this instruction, the program jump to the address (or label) specified with the instruction. This is a three byte instruction and no flag is affected. In fact during the execution of JMP address (label) instruction, the address of the label is copied in the program counter; and whenever the program fetches the next instruction the program counter will send the address of this given label. [PC ] ← [LABEL ] (a) Conditional Jump Instructions In conditional jump instructions the program jumps to the instructions specified by the address (or label) if the given condition is fulfilled. However, if the given condition is not satisfied, the program will not jump to the specified address (or label) 103

rather it will proceed to the normal sequence. In all these conditional jump instructions, if program jumps to the specified address after the given condition is satisfied, it will take 10 T-states for its execution otherwise it takes 7 T-states. Following are the conditional Jump instructions. Some of them have also been used in SAP-II computers. (i) JNZ address (label) (Jump if the result is not zero) When this instruction is executed, the program jumps to the instruction specified by the address (or label), if the result is not zero; otherwise it will proceed to the next instruction. Here the result of the preceding instruction is considered. In this case the address (or label) is copied in the program counter if zero flag is reset (Z = 0). [PC ] ← LABEL if Z = 0. This is illustrated if we consider the following instructions: Label Mnemonics Operand ------------DCR C JNZ NEXT MOV A, M NEXT STA 2500 H HLT For the execution of JNZ instruction, the result of C-register will be considered. If [C ] ≠ 0 (Z = 0), it will jump to the instruction (STA 2500 H) specified by the label NEXT, otherwise it will jump to the next instruction (MOV A, M). (ii) JZ address (label) (Jump if the result is zero) The condition of this instruction is reverse to that of JNZ address. In this case the program will jump to the instruction specified by the address (or label), if the result of the preceding instruction is zero (Z = 1) otherwise it will proceed to the next instruction in the normal sequence. The address of the label will be copied in the program counter if Z flag is set (or result is zero). [PC ] ← LABEL if Z = 1. (iii)JNC address (label) (Jump if no carry) During the execution of this instruction, it will check up the Carry flag modified by the preceding instruction. If there is no carry (CY = 0 or CY flag is reset), the program will jump to the instruction specified by the address (or label) otherwise it will proceed to the next instruction of the normal sequence. In this case the address of the label will be copied in the program counter if CY = 0 or CY is reset. [PC ] ← LABEL , if CY = 0 (iv) JC address (label) (Jump if carry) The program will jump to the instruction specified by the address (label) if the CY flag is set (CY = 1) which is modified by the preceding instruction. However, if the carry

104

is reset (CY = 0), it will proceed to the next instruction of the normal sequence. The condition of this instruction is opposite to that of the JNC address. In this case the address of the label will be copied in the program counter if CY = 1 or CY is set. [PC ] ← LABEL , if CY = 1 (v) JM address (label) (Jump if Minus) When this instruction is executed, the program will jump to the instruction specified by the address (label) if the result of the preceding instruction is minus or sign flag is set (S = 1) otherwise it will proceed to the next instruction of the normal sequence. [PC ] ← LABEL , if S = 1 (vi) JP address (label) (Jump if Positive) If the result of the preceding instruction is positive or sign flag is reset (S = 0), the program will jump to the instruction specified by the address (label). However, if the condition is not satisfied it will proceed to the next instruction of the normal sequence. [PC ] ← LABEL , if S = 0 (vii) JPO address (label) (Jump if Parity is Odd) If the parity is odd or parity flag is reset (P = 0) as a result of the preceding instruction, the program will jump to the instruction specified by the address (label) otherwise next instruction of the normal sequence will be executed. [PC ] ← LABEL , if P = 0 (vii) JPE address (label) (Jump if Parity is Even) If the parity is even or parity flag is set (P = 1) as a result of the preceding instruction, the program will jump to the instruction specified by the address (label) otherwise next instruction of the normal sequence will be executed. [PC ] ← LABEL , if P = 1 (c) CALL Instructions The call instructions allow calling the subroutine program. The address of the subroutine program is specified with the CALL instruction. During the execution of CALL instruction, the current contents of program counter are saved on the stack and the address of subroutine (specified with the CALL instruction) is copied in the program counter. Like the jump instructions, the CALL instructions are also of two types. 1. Unconditional Call Instructions 2. Conditional Call Instructions 1. Unconditional Call Instructions CALL address (Calls the addressed subroutine program) This is the format for unconditional call instruction which is of three bytes. The current contents of program counter are saved on the Stack and the address specified with CALL instruction is copied in the program counter. i.e. [SP −1] ← [PCH ] [SP − 2] ← [PCL] and [PC ] ← address To illustrate the CALL address instruction, consider the following assembly language program:

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In this program LXI SP, 2500 H initializes the stack pointer (stack pointer is represented by 2500 H.) i.e. the area or memory locations less than 2500 H will be used for stack purposes. When the instruction CALL 2300 H is executed, the address of the program counter will be 2109 H. The address of the program counter will be saved on the stack. For this stack pointer will be decremented by 1 and the high byte of the program counter (21 H) will be saved on to it; the stack pointer will further be decremented by 1 and lower byte of the program counter (09 H) will be stored on to it. The decremented of the stack pointer will be current position of the stack. This is shown in figure 4.8. The address given with the CALL instruction i.e. 2300 H will be saved or copied in the program counter.

Fig. 4.8 The subroutine program ends at the instruction RET i.e. RET instruction will be the last instruction of the subroutine program. The RET instruction takes the computer back to the main program. The return saved (or pushed) on to the stack will be popped back to the program counter. Further the data stored (or saved) at the top of the stack will be copied as the lower byte of the program counter i.e. [PCL ] ← [M SP ] . The program

106

counter will now be incremented by one and data stored in new stack will be saved to higher byte of the program counter i.e. [PCH ] ← [M SP +1 ] . In the above program, after the execution of RET instruction PC = 2109 H. 2. Conditional Call Instructions Similar to conditional jump instruction SAP-III computer has the following conditional instructions. (i) CNZ address (Call if not zero) This instruction will call the subroutine program specified by the address provided the zero flag is reset. i.e. if Z = 0 or the result is not zero then [SP −1] ← [PCH ] [SP − 2] ← [PCL] and [PC ] ← address (ii) CZ address (Call if zero) It will call the subroutine (specified by the address) if zero fags is set. i.e. if Z = 1 or the result is 1 zero then [SP −1] ← [PCH ] [SP − 2] ← [PCL] and [PC ] ← address (iii) CNC address (Call if no carry) This instruction will check the carry flag. If the carry flag is reset (or CY=0) as per the executed preceding instruction, then the computer will call the addressed subroutine program. i.e. if CY = 0 or there is no carry, then [SP −1] ← [PCH ] [SP − 2] ← [PCL] and [PC ] ← address (iv) CC address (Call if carry) The addressed subroutine will be called by the computer, there is a carry (or carry flag is set ; CY = 1) as per the result of the preceding instruction. i.e. if CY = 1 or there is a carry, then [SP −1] ← [PCH ] [SP − 2] ← [PCL] and [PC ] ← address (v) CM address (Call if minus) During the execution of this instruction the sign flag will be checked. If the result of the preceding instruction is negative or sign flag is set (S = 1), then only the computer will call the subroutine program specified by the address. So if S = 1, then [SP −1] ← [PCH ] [SP − 2] ← [PCL] [PC ] ← address and (vi) CP address (Call if positive) 107

In this CALL instruction too the sign flag will be checked. If the result of the preceding instruction is positive or sign flag is reset (S = 0), then the computer will call the subroutine program specified by the address. So if S = 0, then [SP −1] ← [PCH ] [SP − 2] ← [PCL] and [PC ] ← address (vii) CPO address (Call if parity is odd) If the parity of the result of the preceding instruction is odd (or parity flag is reset; P = 0), then the computer will call the addressed subroutine program. So if P = 0, then [SP −1] ← [PCH ] [SP − 2] ← [PCL] and [PC ] ← address (ix) CPE address (Call if parity is even) The computer will call the addressed subroutine program, if the parity of the result of the preceding instruction is even (or parity flag is set; P = 1), then. So if P = 0, then [SP −1] ← [PCH ] [SP − 2] ← [PCL] and [PC ] ← address Return Instructions As already discussed, the last instruction of the subroutine program is RET (Return instruction). This return instruction takes the computer back to the main program. The return instructions may also be conditional. The following are the conditional return instructions: RNZ Return if no zero RZ Return if zero RNC Return if no carry RC Return if carry RM Return if minus RP Return if positive RPO Return parity is odd RPE Return parity is even All the above return instructions are one byte instructions. If the specified condition is satisfied, it will return to the main program; otherwise the execution of the next instruction in the subroutine will be carried out. Further the return instruction will pop the return address to the program counter. For example, we consider the instruction RNC. It will check the carry flag. Only if the carry flag is reset (CY = 0 or no carry), the computer return to main program. i.e. if CY = 0 , then [PCL] ← [SP] [PCH ] ← [SP + 1]

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4.2.5

Stack and Input / Output Instructions Stack is a portion of read/write memory, which is primarily used for saving return address and data. As discussed earlier, in SAP-II computers, last two memory locations of the read / write memory FFFF H and FFFE H are exclusively used for return address of a subroutine call. In SAP-III computers, the programmer can specify any area of the memory for the stack purposes. The portion of memory located chosen by the programmer for the stack purposes can not be used for saving the return address of subroutine call. For this purpose a 16 bit register called stack pointer is provided. Table 4.5 Stack I/O Group Instruction

Op. Code

Addressing modes

No of TStates

No of bytes of instr.

Flags affected

LXI SP, addr PUSH B

31 C5

10 12

3 1

None None

PUSH D

D5

12

1

None

PUSH H

E5

12

1

None

PUSH PSW

F5

12

1

None

POP B

C1

10

1

None

POP D

D1

10

1

None

POP H

E1

10

1

None

POP PSW

F1

10

1

None

IN Port

DB D3

Immediate Register indirect Register indirect Register indirect Register indirect Register indirect Register indirect Register indirect Register indirect Immediate Immediate

10 10

2 2

None None

OUT Port

Operati on

The stack is initialized by the instruction given below: LXI SP, address (Load immediately the stack pointer)

109

For example LXI SP, 2500 H will indicate the stack pointer as 2500 H as

Fig. 4.9 shown in figure 4.9. So the memory locations lower than 2500 H may be used for stack purposes i.e. the data or return addresses may be pushed to stack in the sequence discussed earlier in CALL instructions. Following are the Stack instructions: (i) Push Instructions In the stack not only the return address of the main program during the execution of CALL address instruction is pushed but also the contents of registers may also be pushed to stack. For this following is the format of PUSH instructions: PUSH rp where rp stands for register pair. It may be B for B-C register pair, D for D-E register pair, H for H-L register pair, PSW is known as program status word; it represents the accumulator and the flag contents i.e. A F So we have the following PUSH instructions. PUSH B ; it pushes or saves the contents of B and C registers on the stack. PUSH D ; it pushes or saves the contents of D and E registers on the stack. PUSH H

; it pushes or saves the contents of H and L registers on the stack.

PUSH PSW

; it pushes or saves the contents of accumulator (A) and F (flag) registers on the stack. Following steps are carried out during the execution of PUSH rp instructions. 1. The stack pointer is decremented by one to get a new value of stack pointer as SP-1.

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2. The contents of higher register of the given register pair (say B register in B-C register pair. i.e. [M SP−1 ] ← [rp H ] 3. The stack pointer is further decremented by one to get new value of stack pointer as SP-2. 4. The contents of lower register ( C register in B-C register pair) is saved in the memory location specified by SP-2. i.e. [M SP−2 ] ← [rp L ] 5. SP-2 will now be the stack pointer for other PUSH instructions. For example we have

SP = 2500 H HL = 5678 H After the execution of PUSH H instruction 56 H will be loaded to memory location 24FF H and 78 H will be loaded to 24FE H memory location as shown in figure 4.10.

Fig. 4.10 (ii) Pop Instructions To retrieve the contents of registers from the stack, following POP instructions are used. POP B ; where B stands for B-C register pair. POP D ; where D stands for D-E register pair. POP H ; where H stands for H-L register pair. POP PSW

; where PSW stands for Program status word i.e. accumulator (A) and F (flag) register.

During the execution of POP instructions following steps are carried out.

111

1. The byte stored in memory location addressed by stack pointer is saved in the lower register of the given register pair (say C in B-C register pair). The contents of higher register of the given register pair (say B register in B-C register pair. i.e. [rp L ] ← [M SP ] 2. The stack pointer is incremented by one to get new value of stack pointer as SP+1. 3. The contents stored in the memory location addressed by stack pointer (new value as SP+1) is saved in higher register of the given register pair ( B register in B-C register pair). i.e. [rp H ] ← [M SP+1 ] 4. The stack pointer is further incremented by one to get the new value of stack pointer as SP+2 i.e. SP+2 will now work as stack pointer.

Suppose the data saved in stack is shown in figure 4.11. The stack pointer is shown as 24FC H. Let A = 01 H F = 00 H D = 12 H E = 6E H before the execution of POP PSW and POP D instructions. After the execution of these instructions we have the following data in the registers. F = 59 H A = 24 H E = 36 H D = 9F H Now 2500 H will be the new value of stack pointer.

Fig. 4.11 It should be remembered that when a subroutine is called, it should save the contents of any register being used in the main program using PUSH instruction in the stack; and when it returns back to the main program form the subroutine program the

112

contents of the register should be retrieved from the stack using POP instruction as discussed above. The sequence of PUSH and POP instructions should be as: PUSH PSW PUSH D PUSH B PUSH H ------------------POP H POP B POP D POP PSW It should be noted that POP retrieve the data from the stack just in reverse order of the data was PUSHed i.e. as Last In First Out (LIFO) method is used in the stack. PUSH and POP instructions may also be used in the main program. PUSH instruction is used before the CALL instruction and POP (in the reverse order) after the CALL instruction in the main program as given below: Main Program: ------------------PUSH PSW PUSH H CALL LABEL POP H POP PSW ---------------------In this program the contents of Accumulator, Flag, H and L registers are saved in the Stack before the execution of CALL instruction. After the execution of subroutine program the contents of the Accumulator, Flag, H and L registers are retrieved and next instructions of the main program will be executed with restoration of earlier values of the registers. Further, the PUSH and POP instructions may be used in the subroutine program as given below. This is generally done when the CALL instruction is used may times. Main Program: ------------------CALL LABEL --------------------Subroutine Progam:

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LABEL

PUSH PSW PUSH D PUSH B ------------------POP B POP D POP PSW RET

Input / Output Instructions The input / output instructions deal with the input / output operations. These instructions are same used in SAP-II computer. (i) IN Port (Inputs the data from the port) In this instruction the data available at the specified port address is moved to the accumulator. [A] ← data from port It is two byte instruction and no flag is affected after the execution of this instruction. This instruction is basically used to read the data from the input devices such as data read from key board, switches etc. during the computer run. (ii) OUT Port (Outputs the data to the port) This two byte output instruction is used to send the contents of accumulator to the specified port. Output ← [A] 4.3 TIME DELAY INTRODUCED BY A REGISTER PAIR The time delay introduced by different registers has been discussed in the last chapter using SAP-II instructions. The time delay can considerably be increased by using a register pair. A 16-bit number may be taken in two registers (register pair). Consider the following subroutine assembly language program: Label Mnemonics Operand Comments LXI D, F424 H ;Loads DE register pair with a 16-bit number. LOOP DCX D ;Decrements DE register pair by one. MOV A, E ;Moves the contents of E register to accumulator. ORA D ;ORing of the contents of D and E registers are performed to set the zero flag. JNZ LOOP ;If result ≠ 0 jump to loop RET ;Go back to main program. Total T-states used for the above program are given as:

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Mnemonics T-states LXI 10 DCX 5 MOV 5 ORA 4 JNZ LOOP 10/7 RET 10 24 T-states are used for the inner loop and 10+7+10 = 27 T-states are used for outer loop. In this program the execution of loop is for 62500 times (as F424 H = 62500 10). The condition for the check of zero flag can not be applied just after DCX instruction, since no flag gets affected with this instruction. So to check the zero flag ORA instruction affect the zero flag. The zero flag will be set if the contents of both D and E registers are zero. The time delay introduced by the inner loop is: TLOOP = 62500 x 24 x Time of one T-state. If the system clock frequency is 3 MHz, then 1 TLOOP = 62500 x 24 x µsec 3 = 500000 µsec = 0.5 sec. Delay introduced for outside loop is: 1 Tout = 27x1x µsec 3 = 9 µsec So the total time delay introduced by the above subroutine program is given by:

TDelay = 0.5 sec + 9 µsec ≈ 0.5 sec Example 4.1 What maximum delay can be introduced by the subroutine program using a register pair? Let the system clock frequency is 3 MHz. Solution. The subroutine program for the delay using a register pair is given as: Label

Mnemonics Operand LXI D, FFFF H LOOP DCX D MOV A, E ORA D JNZ LOOP RET The maximum delay can be introduced if the maximum number (FFFF H) is taken in DE register pair. FFFF H = 65535 10 1 1 So TLOOP = 65535 x 24 x µsec + 27x1x µsec 3 3 = 524280+9 µsec 115

= 524289 µsec = 0.52 sec Example 4.2 Write a program in assembly language to introduce a time delay of 1 sec using a register pair. Let the system clock frequency is 3 MHz. Solution. For one sec delay, the program discussed in section in 4.3 can be executed twice as given below: Main Program: Label Mnemonics Operand MVI C, 02 H LOOP1 CALL DELAY DCR C JNZ LOOP1 HLT Subroutine Program: Label Mnemonics Operand DELAY LXI D, F424 H LOOP DCX D MOV A, E ORA D JNZ LOOP RET In this program the subroutine program is run two times as subroutine program in one go introduces a time delay of 0.5 sec. Example 4.3 It is desired to clear the accumulator contents of a SAP-III computer. Explain the possible instructions for this purpose. Solution. To clear the accumulator contents, the possible instructions are: (i) MVI A, 00 H Two byte instruction and no flag gets affected. (ii) XRA A One byte instruction, CY flag will be reset and all other flags will be modified as per the result. (iii) ANI 00 H Two byte instruction, CY flag will be reset and all other flags will be modified as per the result. (iv) SUB A One byte instruction and all flags will be affected as per the result. Example 4.4 Write a program in assembly language using instructions of SAP-III computers to complement the 256 bytes stored in memory locations 2500 H through 25FF H. Store the complemented data in memory locations starting at 2600 H. Solution. Label Mnemonics Operand Comments LXI H, 2500 H ;Loads the address of the first number in H-L register pair. MVI C, FF H ; 256 bytes (FF H) is stored in C-register as index register. LOOP MOV A, M ;Moves the contents of memory location addressed

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CMA MVI H, MOV M,

26 H A

MVI H, INX H

25 H

DCR C JNZ

LOOP

by H-L register pair to accumulator. ;complements the accumulator contents. ;Stores 26 H in H-register ;Complemented data is stored in the destination memory location. ;Stores 25 H in H-register ;Increments the H-L register pair. ;Decrements the contents of C register. ;Go back to loop for the operation of next data.

HLT Example 4.5 Write a program in assembly language using instructions of SAP-III computers to find the smaller of two numbers stored in memory locations 2501 H and 2502 H. Store the result in 2503 H memory location. Solution. Label Mnemonics Operand Comments LXI H, 2501 H ;Loads the address of the first number in H-L register pair. MOV A, M ;Saves the first number in accumulator. INX H ;Increments the H-L register pair. CMP M ;compares the two numbers. JC NEXT ;if carry smaller number is in accumulator go to NEXT. MOV A, M ;If no carry then move the smaller number to accumulator. NEXT STA 2503 H ;Stores the smaller number in 2503 memory location . HLT Example 4.6 Write a program in assembly language using instructions of SAP-III computers to add two hexadecimal numbers stored in memory locations 2501 H and 2502 H. The answer should be stored in 2503 H memory location. The carry if any should be stored in 2504 H memory location. Solution. Label Mnemonics Operand Comments

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LXI H,

2501 H

MVI C,

00 H

MOV A,

M

INX H

NEXT

ADD M JNC INR C

NEXT

STA MOV A,

2503 H C

STA

2504 H

;Loads the address of the first number in H-L register pair. ;Clears C-register for carry (most significant bit). ;Saves the first number in accumulator. ;Increments the H-L register pair. ;Adds the two numbers. ;if no carry go to NEXT. ;Else increment the content of C-register. ;Stores the answer . ;Moves the contents of C register (carry contents) to accumulator ;Saves the contents of carry.

HLT Example 4.7 Write a program in assembly language for SAP-III computers to find the sum of a series 1+2+3+……+10 (or sum of first 10 natural numbers). Solution. Label Mnemonics Operand Comments MVI B, 01 H ;Loads first number of series to B-register. MVI C, 00 H ;Clears C-register. LOOP MOV A, C ;Saves the contents of Cregister to accumulator. ADD B ;Adds the contents of Bregister with the contents of accumulator. MOV C, A ;Saves the partial sum to Cregister. INR B ;increments the contents of B-register. CPI 0B H ;Compares with natural number 11. JNZ LOOP ;If not 11 go back to LOOP. MOV A, C ;Saves the answer to accumulator. STA 2500 H ;Saves the answer to memory location. HLT Example 4.8 Reset all the flags, in a subroutine program, without performing arithmetic or logical instructions. However the contents of other registers should not be changed. Solution.

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Label

Mnemonics PUSH H

Operand

PUSH PSW LXI H,

0000 H

PUSH H POP PSW POP H

MOV A,

H

POP H

Comments ;Saves the contents of H-L register pair to stack. ;Saves the contents of A-F to stack. ;Loads 0000 H to H-L register pair. ; Saves the contents of H-L register pair to stack. ;Saves the contents of stack in A-F registers. ; Retrieve the contents of H-L register pair from the stack. ;Moves the contents of Hregister to accumulator. ;Pops the contents from stack to H-L register pair.

RET Example 4.9 How will you exchange the contents of BC and HL register pairs? Solution. Following program may exchange the contents of BC and HL register pairs: Label Mnemonics Operand Comments LXI SP, XXX H ;Initializes the stack pointer. PUSH B ;Saves the contents of B-C register pair to stack. PUSH H ;Saves the contents of H-L register pair to stack. POP B ;Pops the contents of stack (H-L register pair contents) to B-C register pair. POP H ;Pops the contents of stack (B-C register pair contents) to H-L register pair. HLT Example 4.10 Write a subroutine program using SAP-III instructions, which will subtract the contents of D-E register pair from H-L register pair and the result is to be stored in H-L register pair. Solution. Label Mnemonics Operand Comments MOV A, L ;Transfer the contents of L register to accumulator. SUB E ;Contents of E register are subtracted from accumulator contents.

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MOV L,

A

MOV A,

H

SBB D

MOV H,

A

;Answer (list significant digit of the answer) is loaded to L register. ;Moves the contents of H register to accumulator. ;Subtracts the content of D register from acc. with carry. ;Most significant digit of the answer is saved in H register.

HLT Example 4.11 What will be the value of accumulator and flags (CY, S, P and Z), after the execution of the following program. Label Mnemonics Operand MVI D, 7F H MVI C, 3E H MOV A, C RLC RLC ANA D HLT Solution. After the execution of the above program we have: D= 01111111 C= 00111110 A= 00111110 After first RLC A= 01111100 CY = 0 After second RLC A= 11111000 CY = 0 ANDing of D = 01111111 -------------------------The value of accumulator is A = 0 1 1 1 1 0 0 0 = 78 H The values of Flag register are: CY = 0 (reset after ANDing) S = 0 P = 1 Z = 0 Example 4.12 Write a program using SAP-III instructions to check the even parity or the odd parity of the number stored in memory location 2010 H. Send 00 H or EE H at the output port 02 H if the parity is odd or even respectively. Solution. Label Mnemonics Operand Comments LXI H, 2010 H ;Initializes the H-L register pair with the address of the location. MOV A, M ;Moves the number to accumulator.

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ORA A

ODD

JPO

ODD

MVI A,

EE H

OUT

02 H

JMP MVI A,

END 00 H

;ORing of A with A will load the same number to accumulator. The parity flag will be affected with this operation. ;Jump to ODD if parity is odd. ;Load EE H to accumulator for even parity. ;EE is sent to output port 02H. ;Jump to end. ;Load 00 H to accumulator for odd parity. ;00 is sent to output port 02H.

OUT 02 H END HLT Example 4.13 (a) What will be the value of B-register after the following program is executed. Label Mnemonics Operand Comments MVI A, 07 H STC CMC RAL MOV B, A STC CMC RAL STC CMC RAL ADD B MOVB, A HLT (b) Suggest some alternative program that can perform the same operation. Solution. (a) In the beginning accumulator is loaded with a hexadecimal number 07 H. The instruction STC and CMC resets the carry flag and RAL instruction moves the accumulator contents left through carry giving us the contents 0E H (=1410) i.e. STC, CMC and RAL instructions multiplies the accumulator contents by a factor of two. The accumulator contents are now saved in register B. Three instructions STC, CMC and RAL are further used twice so that accumulator contents are multiplied by a factor of 4. This way after the third RAL in the program we have A = 8 X 07 H = 38 H = 5610. After ADD B we get: A = 38 H + 0E H = 46 H = 7010

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So this program multiplies the accumulator contents by a factor of 10 (decimal number) which is stored in B-register. So B = 46 H = 7010 (b) The program given in (a) multiplies the accumulator contents by a factor of 10 (decimal number) which is stored in B-register. The following program also perform the same operation. Label Mnemonics Operand Comments MVI A, 07 H ;Loads 07 H to accumulator. ANI FF H ;It clears the carry flag. RAL ;Shifts left by one bit or multiplies accumulator contents by a factor or two. MOV B, A ;Moves the answer to Bregister. ANI FF H ;It clears the carry flag. RAL ;Shifts left by one bit or multiplies accumulator contents by a factor or two. So A = 4 x A. ANI FF H ;It again clears the carry flag. RAL ;Shifts left by one bit or multiplies accumulator contents by a factor or two. So A = 8 x A. ADD B ; [A] ← [ A] + [B ] So it gives A = 10 x A MOV B, A ;Result is stored in B register. HLT This program does the same operation as given in (a), however, less number of instructions is used in this program. Example 4.14 A byte of data is stored in memory location 2500 H. Display at the output port 02 H the number of 1’s present in the data byte stored in memory location 2500 H. Solution. Label Mnemonics Operand Comments LDA 2500 H ;Loads the data byte in accumulator. MVI C, 08 H ;08 H is loaded to C-register to use it as a counter. MVI B, 00 H ; 00 H is loaded to B-register. LOOP RLC ;MSB is shifted to carry flag. JNC NEXT ;Checks the carry flag, if not zero go to next (i.e. no 1 is present at the MSB). INR B ;Increments the B-register by one.

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NEXT

DCR C JNZ MOV A,

LOOP B

OUT

02 H

;Decrements C-register. ;Jumps to LOOP if Z = 0. ;No. of 1’s present is loaded to accumulator. ;Sends the data to the output port.

HLT

1. 2. 3. 4. 5. 6. 7.

8. 9. 10. 11. 12. 13. 14. 15.

16.

PROBLEMS Give the programming model (Software model) of SAP-III computers. How many flags are used in SAP-III computers? How are these flags affected with the result? Explain with the help of block diagram how the carry flag gets affected with the result. In how many groups the instruction set of SAP-III computers are classified. Explain with examples the instructions of arithmetic group. Discuss the rotate instructions used in SAP-III computers. How the flags are affected with these instructions. What is the difference between the stack and stack pointer? Discuss PUSH and POP instructions. Explain what operations are performed when the following instructions are executed. Give at least one example for each operation. (i) LXI H, address (ii) ADD M (iii) CMP reg What is difference between CMP reg and SUB reg instructions? Explain with suitable examples. If carry flag is zero, then show that RAL instruction produces a multiplication of accumulator contents by a factor of 2. If carry flag is zero, then show that RAR instruction produces a division of accumulator contents by a factor of 2. Show that the instruction DAD H shifts left the data in H-L register pair by one bit. Discuss various addressing modes of SAP-III computers instructions and give at least two examples of each addressing mode. What do you understand by subroutine? Explain the use of stack and stack pointer in calling a subroutine. Explain any other use of stack. Write a program for SAP-III computers introduce a time delay of 0.5 sec if the system clock frequency is 6 MHz. Explain the following instruction of SAP-III computer. Also discuss which flags get affected with the execution of these instructions. ADD M, CMP B, POP PSW and MOV A, M. An ORA reg or ORI data instruction can be used to make a selected bit of a specified register as 1. Justify this statement. Also write the mnemonic of an instruction that will set bit 6 of the accumulator without changing any of the other bits in the register. (Ans.: ORI 40 H)

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17.

18.

19.

20.

21.

What will be contents of accumulator and flags (CY, S, P and Z), after the execution of ADD D instruction; if A = C3 H and D = 3D H. (Ans: A= 00 H, CY = 1, S = 0, P = 1 and Z = 1) What will be contents of accumulator and flags (CY, S, P and Z), after the execution of SUB D instruction; if A = C3 H and D = 3D H. (Ans: A= 85 H, CY = 0, S = 1, P = 0 and Z = 0) What will be contents of memory location 2500 H and flags (CY, S, P and Z), after the execution of the following program: MVI C, C8 H MVI A, 11 H ADD C STA 2500 H HLT (Ans: M 2500 = D9 H, CY = 0, S = 1, P = 0 and Z = 0) What will be the value of stack pointer, after the following program written in SAP-III instructions is executed. LXI SP, 27FF H PUSH D CALL SUBROUT POP D ADD D PUSH D HLT What will be the value of stack pointer after this program? (Ans: SP = 27FD H) What will be the contents in B-register, after the execution of the following assembly language program? Label Mnemonics Operand MVI A, 08 H STC CMC RAL MOV B, A HLT (Ans.: B = 10 H = 1610) __________

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5 The 8085 Microprocessor After the study of conceptual computers SAP-I, SAP-II and SAP-III, we are now in the position to understand the fundamentals of 8-bit microprocessor 8085. As discussed in the preceding chapters, the basic components of all the computers are Keyboard, Display devices, Memory devices and Central Processing unit. The central processing unit (CPU) is the heart of the computer and also called microprocessor. The technological revolution brought in recent years, the invention of microprogrammable computer on microprocessor chip. First four bit microprocessor chip INTEL-4004 was developed by Intel Corporation of America in 1971. Intel introduced in 1972 an 8-bit microprocessor 8008 and in 1973 another 8-bit microprocessor 8080. The microprocessor 8080 was the most popular microprocessor of the early 70s. In the year 1974, Intel developed a 40 pin microprocessor chip 8085, which was the enhanced version of 8080. Intel 8080 microprocessor was not in fact a complete CPU on a chip because the clock and controller were on separate chip. Further, it utilizes two separate power supplies. The 8085 microprocessor has the advantages over 8080 that it has onchip clock and control circuit. It needs only one power supply of +5 volts. 5.1 ARCHITECTURE OF 8085 MICROPROCESSOR Intel 8085, an 8-bit NMOS microprocessor is available in the form of 40 Pin dual in line IC package. It is fabricated on a single LSI chip. It operates on +5 V d.c. supply. The clock speed used in this microprocessor is about 3 MHZ. General Purpose 8-bit microprocessor is capable of addressing up to 64 K bytes (i.e. 216 = 65536 bytes) of memory. The functional block diagram is shown in figure 5.1.

The main functional components of 8085A microprocessor are as given below: (i) Register Section (ii) Arithmetic and Logic Unit (iii) Timing and Control Section (iv) Interrupt Control (v) Serial Input / Output Control

Fig. 5.1

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5.1.1

Register Section The 8085 microprocessor contains eight addressable 8-bit registers namely: A (Accumulator) register F Flag register (Flag flip-flops) B register C register D register E register H register L register

Out of these registers B, C, D, E, H and L registers are 8-bit general purpose registers. These registers can either be used as single register or a combination of two registers as 16 bit register pair. As discussed in SAP-III computers, the valid register pairs are B-C, D-E or H-L register pairs. The higher order byte of 16 bit data is stored in first register (B in B-C register pair), and low order byte in the second register (C in B-C register pair). The H-L register pair can also be used for register indirect addressing; since this register pair can also function as data pointer. The large number of general purpose registers gives more flexibility and ease in the programming. However, the general purpose registers are limited as registers occupy more space on the silicon chip. Beside these general purpose registers, the 8085 has remaining two 8-bit registers Accumulator (A) and Flag (F) as special purpose registers and two 16 bit registers namely Program counter (PC) and stack pointer (SP). Accumulator (A) As discussed in preceding chapters, accumulator is a 8 bit buffer register extensively used in arithmetic, logic, load and store operations as well as in input / output instructions. All the arithmetic and logical operations are performed on the accumulator contents; i.e. one of the operand is always taken into the accumulator. Flag (F) Register It is an 8-bit register associated with the execution of instructions in the microprocessor. Out of the 8 bits of flag register, 5 bits contains significant information in terms of status flags. The five flags are: (i) Sign flag (S) (ii) Zero flag (Z) (iii) Carry flag (CY) (iv) Parity flag (P) (v) Auxiliary Carry flag (AC) All the flags except the Auxiliary carry (AC) flag have been discussed in SAP-III computers.

127

The bit positions reserved for these flags in the flag register (F) is shown in figure 5.2.

(i) Sign flag (S)

Fig. 5.2 The sign flag is set (S = 1), if the result of the operation of the instruction is negative (MSB of the result is 1); otherwise it is reset (S = 0) for the positive result (MSB is zero).

(ii) Zero flag (Z)

The zero flag is set (Z = 1) if the result of the operation of the instruction is zero otherwise this flag is reset (Z = 0). i.e. Z = 1 if the result is zero, and Z = 0 if the result is not zero.

(iii) Carry flag (CY)

The carry flag is set to 1, if there exist a carry (or borrow) to the highest order bit (non-existent 9th position) as a result of the execution of addition or subtraction instructions. If there is no carry (or borrow) to the higher order bit, the carry flag is reset. i.e. CY = 1 if there is a carry to the highest order bit (or overflow), and CY = 0 if there is no carry to the highest order bit (or no overflow).

128

(iv) Parity flag (P)

After an arithmetic and logic operation, if the result has even number of 1s, then parity bit is set. If on the other hand the result has odd number of 1s, the parity flag is reset. i.e. P = 1, if the result has even number of 1s, and P = 0, if the result has odd number of 1s.

(v) Auxiliary carry (AC) This is a new flag in 8085 microprocessor. This flag (AC) is set to 1, if there is an overflow at bit 3 of the accumulator. AC flag is used in BCD arithmetic. This is illustrated as given below:

As shown in figure 5.2, the five bits in flag register are defined. The three bits are undefined. The Accumulator and 8 bits (including three undefined bits) of flag register form a Program Status Word (PSW). The accumulator and flag registers are treated as a 16 bit unit for stack operation. Program Counter – 16 bit register The program counter is a 16 bit register. It is used to send 16 bit address to fetch the instruction from the memory. It acts as a pointer which indicates the address of the next instruction to be fetched and executed. The program counter is updated after an instruction has been fetched by the processor. If an instruction is one byte instruction, then the program counter will be updated by one (i.e. PC = PC + 1). Similarly, for two and three byte instructions, the program counter will be updated by two (i.e. PC = PC + 2) or three (i.e. PC = PC + 3) locations respectively. Stack Pointer – 16 bit register The stack is an area of RAM (random access memory or read / write memory) in which temporary information is stored. It is stored on First-In-Last-Out (FILO) basis. An address in the RAM area is assigned to the stack pointer where the first information is stored as the first stack entry. This is done by initializing stack pointer by an instruction. Higher stack entries are made at the progressively decreasing addresses. 5.1.2 Address Buffer and Address-Data Buffer It has already been discussed that 8085 requires 8-bit data bus and 16-bit address bus, as the memory address is of 16 bits. More number of IC pins are required if separate address and data bus are introduced. To restrict the number of pins of 8085 to only 40, lower address lines A0-A7 and data lines D0-D7 are used in multiplexed mode. The multiplexed lines are designed as Address/Data Bus (AD0-AD7). So whenever 16-bit address is transmitted by the microprocessor 8 MSBs of the address lines are sent on the Address Bus (A15-A8) and 8 LSBs of the lines are sent on the Address/Data Bus (AD7AD0). The 8 LSBs of the address are then latched either into memory or external latch so that the complete address remains available for further operation. The 8-bit Address/Data Bus will now be free for the data transmission. 5.1.3

Arithmetic and Logical Unit (ALU)

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The arithmetic and logical unit (ALU) basically consists of accumulator (A), flag register (F) and a temporary register (which is inaccessible by the programmer or user). This unit carries out the arithmetic and logic calculations of the data stored in general purpose registers or in memory locations. The arithmetic operations are ADD, SUB, compare, increments, decrements and complements etc.; while logical operations are AND, OR, XOR and Rotate. The result of these operations could be placed in the accumulator or elsewhere through the internal bus. Arithmetic operations are usually carried out in 2’s complement adder / subtrator discussed in the preceding chapter. For these operations, ALU receives the control signals from the timing and control unit. 5.1.4 Timing and Control Unit This unit consists of the following sections: 1. Instruction Register and Decoder 2. Control signals 1. Instruction Register and Decoder As discussed in the preceding chapter, the CPU fetches an instruction from the memory for its execution. This instruction can be of 1-3 byte long. The first byte contains the op code of instruction which basically specifies the nature of operation to be performed indicating the length of the instruction. The first byte (op code of the instruction) transferred to 8-bit instruction register through the internal bus of the CPU, becomes available at the instruction decoder. The decoder decodes the op code and directs the control unit to produce the necessary control signals. 2. Control Signals Following are the control signals of 8085 microprocessor needed for the operation of CPU. (i) X1, X2 and CLK Out Two pins X1 and X2 are provided to be externally connected to a quartz crystal. The clock signal of fixed frequency is generated through the internal circuitry of the processor. The frequency at which the microprocessor 8085 works is half of the crystal frequency. The quartz crystal of 6.144 MHz is used in this processor. This gives the clock frequency of 3.072 MHz (half of the crystal frequency) of 50% duty cycle. The clock period is of about 320 nsec. The output of the clock frequency is also available at CLK out terminal. (ii) Address Latch Enable (ALE) The 16 bit address bus is basically divided into two sets. The most significant bits A7-A15 of the address bus are used separately and the least significant bits of the address AD0-AD7 are time multiplexed with the bits of bidirectional data bus (D0-D7). The AD0AD7 bus serves the dual purpose as they can be used as low-order address bus as well as bidirectional data bus at different times. This is used as address bus, during the first clock cycle of the machine cycle involving memory; and during the remaining clock cycle of the machine cycle, it acts as the data bus. This is accomplished by address latch enable (ALE) signal provided in the processor. During the first clock cycle of the machine cycle ALE is high which enables the lower 8-bit of the address to be latched either into the memory or external latch. (iii) RD (Read ) Signal

130

This is an active low signal to be connected to memory read input (output enable signal to memories) or to input / output read signal to enable input / output buffer. (iv) WR (Write) Signal Similar to read signal ( RD ), write signal ( WR ) is also active low. This signal is used to write to the memory or input / output devices. (v) IO/ M (Input Output / Memory) This signal IO/ M distinguishes that the address and data is meant for either I/O devices or memory. Whenever this signal is high (1), microprocessor will communicate to the I/O devices and whenever it is low (0), microprocessor will communicate to the memory. (vi) Status Signals (S0, S1) The status signals (S0, S1) along with IO/ M signal indicate the type of machine cycle in progress. The type of machine cycle are op code fetch cycle, memory read cycle, memory write cycle, I/O read cycle or I/O write cycle. Various types of status codes are given in table 5.2. Table 5.2 Machine Cycle S1 S0 IO/ M Op code fetch Cycle 0 1 1 Memory Read Cycle 0 1 0 Memory Write Cycle 0 0 1 I/O Read Cycle 1 1 0 I/O Write Cycle 1 0 1 INTR Acknowledge 1 1 1 Halt Hi-Z 0 0 (vi) Hold and HLDA HOLD and HLDA (Hold Acknowledge) signals are used for DMA (Direct Memory Access) operation. In a microprocessor, the data transfer between I/O devices and memory will take place through the microprocessor. The involvement of the processor slows down the data transfer between I/O devices and memory. The transfer of data directly from I/O devices to memory without involvement of microprocessor is called DMA. The DMA will save the time as CPU relinquishes the control of Buses. In this way DMA transfers the large amount of data in a relatively short time. The HOLD and HLDA signals are used in the operation. Whenever HOLD signal is high, CPU temporarily relinquishes its operation by floating the address, data and control buses; and DMA operation is started. A high HLDA (Hold Acknowledge) signal is also sent to DMA controller, indicating that CPU has received the hold request. Whenever the data transfer is complete, then the control to CPU is returned back by sending a HOLD signal. Further the HLDA signal goes low. (viii) READY signal (Input) Some peripheral devices connected to 8085 microprocessor operate at much slower speed than the processor. To synchronize the speed of CPU and peripheral devices or to slow down the speed of 8085, the READY signal is used. If the READY signal is high the peripheral device is ready and the processor can complete the data transfer. If

131

this signal is low the microprocessor waits (by generating a number of NOP T-states) till it goes high. (ix)

and RESET OUT

The signal may be low from the operator Reset button or from the processor. When the signal is low, the CPU will reset the program counter, instruction register and other circuits. It also sends a high RESET OUT. The RESET OUT signal goes to peripheral devices to reset or initialized. When signal goes high and RESET OUT goes low, the data processing may begin. 5.1.5 Interrupt Control Sometimes it is necessary to interrupt the execution of the main program. For this an interrupt request is obtained from the I/O devices. After receiving the interrupt request (INTR), processor temporarily stops what it was doing and attends to the I/O device. INTA is an interrupt acknowledge signal which is sent by the microprocessor after INTR signal is received. After the work of the I/O device is complete it returns to what it was doing earlier. Basically 8085A has five hardware interrupts namely: INTR RST 5.5 RST 6.5 RST 7.5 and TRAP If two or more of these interrupts are active at the same time, the 8085 takes them in order of priority level. The priority levels of these interrupts are given in table 5.3. Table 5.3 Interrupts Priority TRAP 1 RST 7.5 2 RST 6.5 3 RST 5.5 4 INTR 5 The details of these instructions will be discussed in chapter 7. 5.1.6 Serial I/O Control Serial input / output control circuit incorporated in this microprocessor is used for the data transmission. For this purpose two pins SID and SOD are provided in the serial input/output control unit. The SID (Serial Input Data) terminal receives the serial data stream from an input device, the control unit converts serial data stream to parallel data before it is used by the computer. After the conversion 8-bit parallel data is stored in the accumulator. Similarly, SOD (Serial Out Data) terminal outputs the 8-bit parallel available with the accumulator into serial form to the peripheral device connected with the computer. 5.2 PIN DESCRIPTION OF 8085

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The pin details and logical schematics of the 40 pin dual line package (DIP) IC 8085 are shown in figures 5.3(a) and (b) respectively. Fig. 5.3 (c) shows the shape of the microprocessor. The descriptions of various pins of the microprocessor are given below:

Fig. 5.3 (a)

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Fig. 5.3 (b)

Fig. 5.3 (c)

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PIN NOS. 1 and 2: These X1 and X2 pins are to be connected to an external quartz crystal, L-C or R-C network which drives the internal clock generator. The clock signal of appropriate frequency is determined when a quartz crystal is connected to the on-chip oscillator as shown in figure 5.4(a). The oscillator output from the Schmitt trigger drives a flip-flop which divides the frequency by a factor of two. The circuit produces two clock signals Φ1 (CLK) and Φ2 ( CLK ) to derive the internal circuit of the microprocessor. A 6.25 MHz crystal is used to provide 3.125 MHz internal clock frequency. Generally, quartz crystal is used for the On-chip oscillator for the accurate and stable clock frequency, though a parallel resonant L-C circuit may be used for the frequency determining network as shown in figure 5.4(b). The network produces a signal whose frequency tolerance is about ± 10% . The component values may be chosen from the following formula: 1 f = 2π L(C + C in ) The input capacitance Cin is approximately 15 Pf. To minimize the variations in frequency, it is recommended to choose C as 30 Pf.

Fig. 5.4(a)

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Fig. 5.4 (b) Fig. 5.4 (c) An R-C network may also be used as the frequency determining network for the on-chip oscillator of the microprocessor as shown in figure 5.4(c). The driving frequency generated by this circuit is approximately 3MHz. It is not recommended to use the frequencies higher or lower than this. PIN NO. 3 This is RESET OUT signal, which indicates that CPU is being reset. When it is high, system is reset. The signal is synchronized to the processor clock and lasts for an integral number for clock periods. When the RESET OUT signal goes low, the processing begins. PIN NOS. 4 and 5 Pin Nos. 4 and 5 indicate SOD (Serial Out Data) and SID (Serial In Data) terminals respectively. These pins are associated with Serial Input/Output control unit for 8085 microprocessor. As already discussed these pins are used for the serial data transmission. The SOD output pin can deliver a serial data stream to a peripheral device. On executing SIM (Set Interrupt Mask) instruction, if bit D6 is set to 1, the content of D7 bit (set or reset) of the accumulator is latched on the SOD pin as shown in figure 5.5(a).

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Fig. 5.5 (a) The data on the SID line (PIN 5) loads into accumulator at bit D7 whenever a RIM instruction is executed as shown in figure 5.5(b). The details of SIM and RIM instructions will be discussed in chapter 7.

Fig. 5.5 (b) PIN NOS. 6 to 11

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The interrupt control unit of the microprocessor contains these pins. The Pins 6 to 11 are restart interrupts named as: TRAP (Pin No.6) I Priority RST 7.5 (Pin No. 7) II Priority RST 6.5 (Pin No. 8) III Priority RST 5.5 (Pin No. 9) IV Priority INTR (Pin No. 10) V Priority The TRAP has the highest priority and INTR has the lowest priority. The priority level is of importance if two or more interrupts become active at the same time. The TRAP is non-maskable interrupt. It is both edge and level sensitive. The interrupts (TRAP, RST 7.5, RST 6.5 and RST 5.5) are also called vector interrupts, as each interrupt has fixed memory location (vector location) for the transfer of control from the normal execution of the routine. The vector locations of these interrupts are given in table 5.4. As soon as any of these pins 6 to 10 are active (high), the internal circuit of 8085 stops the normal execution of program and the program control is transferred to the corresponding memory location (vector location). Table 5.4 Interrupts Memory locations TRAP 0024 H RST 7.5 003C H RST 6.5 0034 H RST 5.5 002C H

INTR (Pin No. 10) is a general purpose interrupt and has the lowest priority. As soon as Pin No. 10 is high, the microprocessor stops the execution of normal program and after completing the instruction at hand, it goes to CALL instruction. The INTR is enabled or disabled by the instructions ET (Enable Interrupts) or DI (Disable Interrupts) respectively. The Pin No. 11 is an Interrupt Acknowledge ( INTA ) signal. A low (logic 0) to this pin indicate that the microprocessor has acknowledged the request from the peripheral device. It is also used to activate the interrupt controller. PIN NOS. 12 to 19 Pin Nos. 12 to 19 (AD0-AD7) form bi-directional multiplexed Address/Data Bus. The least significant 8 bits of the memory address (or I/O Address) appear on the bus during the first T-states of a machine cycle. It then becomes the data bus during the next T-states. PIN NO. 20 Pin No. 20 is the ground terminal. PIN NOS. 21 to 28 The Pin Nos. 21 to 28 (A8-A15) form unidirectional most significant 8 bits of memory address or 8 bits of the I/O address. It remains in the high impedance state during HOLD, HALT and RESET modes. PIN NOS. 29 to 33

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The Pin Nos. 29 to 33 labled as S0 and S1 respectively are known as status signals. These status signals along with IO/ M signal indicate the various operations as indicated in table 5.5. Table 5.5 Control signals Machine cycle Status IO/ M S1 S0 Op code Fetch 0 1 1 RD = 0 Memory Read

0

1

0

RD = 0

Memory Write

0

0

1

WR = 0

I/O Read

1

1

0

RD = 0

I/O Write

1

0

1

WR = 0

Interrupt Ack.

1

1

1

INTA = 0

HALT

HI-Z

0

0

HOLD

HI-Z

X

X

RD , WR = Z

RESET

HI-Z

X

X

INTA = 1

HI-Z = High Impedance State X = Unspecified PIN NO. 30 The Pin No. 30 is known as ALE (Address Latch Enable) terminal. When this signal is high the information carried on the multiplexed address/data bus (AD0-AD7) is the lower 8 bits of the address. It also enables the low order address (AD0-AD7) from the multiplexed address/data bus to latch either into the memory or the external latch. The ALE signal separates the low order address and data from the multiplexed Address/data Bus. This is illustrated in figure 5.6.

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Fig. 5.6 PIN NOS. 31, 32 and 34 The Pin Nos. 31 and 32 are the two control signals WR (Write bar) and RD (Read bar) respectively. The pin 34 carries IO/ M signal which is one of the status signals. The other status signals are S0 and S1 discussed earlier. A low WR signal generated by the microprocessor sends (writes) data into I/O devices or memory. Similarly, a low RD signal generated by the microprocessor reads (receives) the data from the I/O devices or memory locations. The IO/ M signal indicates whether the address on the address bus is meant for I/O devices. However, a low to this signal indicates that the address on the address bus is meant for memory location. The RD , WR and IO/ M signals function together. PIN NO. 35

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The Pin No. 35 is known as READ signal which forces the microprocessor to wait till the data become available from the memory or input/output devices. This signal is needed to synchronize the speed of the microprocessor with I/O devices or memory as the memory or I/O devices are not as fast as the microprocessor. When the READ signal is low, the microprocessor waits till the READY signal is 1. As soon as READY signal is 1, the microprocessor knows that the data are available from the memory or I/O devices. PIN NO. 36 This pin is signal. This input carrying signal may be operated by the operator using the RESET button provided externally or it may be operated directly from the other source. When this signal is low (momentarily), the CPU will reset the program counter, instruction register, all interrupts (except TRAP) are disabled, SOD signal becomes low and Data, address and control buses are floated. When this signal goes high, the data processing begins. PIN NO. 37 This pin carries CLK OUT signal. It is derived from the on-chip oscillator, which goes to peripherals to synchronize their timings. PIN NOS. 38-39 The Pin Nos. 38 and 39 are the HOLD and HLDA (Hold Acknowledge) signals respectively. These signals are used in DMA (Direct Memory Access) operations. As shown in figure 5.7, when any I/O device indicates that the data are ready for DMA transfer, a high HOLD signal is sent by the DMA controller to the 8085 microprocessor. It is in fact a request signal from the DMA controller to the microprocessor. The microprocessor then sends a high signal to DMA controller indicating that the microprocessor has received the request from the I/O devices and will relinquish the address, data and control bus after completing the current instruction. The DMA controller thus carries out the data transfer. A low HOLD signal will return the control to the microprocessor.

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Fig. 5.7 PIN NO. 40 The pin 40 is +VCC, which is to be externally connected to +5 volt d.c. supply. 5.3 INSTRUCTION SET OF 8085 MICROPROCESSOR The 8085 includes all the instructions of SAP-III. In addition there are few more instructions which will be discussed below. These new instructions were not considered in SAP-3 because of its architecture. LHLD address (Loads the H-L pair direct) This instruction loads the H-L pair direct with two bytes already stored in two consecutive memory locations starting at the specified memory address. The contents stored in the memory location whose address is given with the instruction will be loaded to the L-register; and the contents stored in the next memory location (address + 1) will be loaded to the H-register. [L] ← [M address ] i.e.

[H] ← [M address+1 ] and For example, let 2A H is stored in the memory location 2100 H and 2B H is stored in the memory location 2101 H, then after the execution of the instruction LHLD 2100 H , the L-register will have 2A H and H-register will have 2B H. None of the flags is affected with this instruction. SHLD address (Stores the H-L pair direct) This instruction does the reverse operation of LHLD. The instruction SHLD address stores the contents of L-register to memory location whose address is given with the instruction; and the contents of H-register are stored in the next consecutive memory location (address + 1). 142

i.e.

[M address ] ← [L] [M address+1 ] ← [H ]

and No flag is affected with this instruction too. For example, if [L] = 3A H and [H ] = 3B H, then after the execution of the instruction SHLD 2200 H will result.

[M 2200H ] ← 3 A [M 2201H ] ← 3B

and LDAX rp (Loads the Accumulator Indirect) This instruction loads the accumulator, the contents already stored in the memory location addressed by the register pair (rp). Here rp represents B-C or D-E register pair. The H-L register pair is not included in this instruction. i.e. [A] ← M rp The possible combinations of the instruction are: LDAX B LDAX D No flag is affected with the execution of this instruction. For example, if [D] = 25 H, [E] = 00 H and M2500 H = 34 H, then after the execution of the instruction LDAX D, the accumulator will have: [A] ← [M 2500H ] i.e. A = 34 H

[ ]

It is worth while to mention that the instruction LDAX H does not exist, because the contents stored in the memory location addressed by H-L register pair may be loaded to accumulator by the instruction MOV A, M. STAX rp (Stores the Accumulator Indirect) The STAX rp instruction does the reverse operation of LDAX rp. This instruction stores the accumulator contents in the memory location addressed by the register pair (rp). Here too rp represents B-C or D-E register pair. The H-L register pair is not included in this instruction. i.e. M rp ← [ A] The possible combination of this instruction are: STAX B STAX D No flag is affected with the execution of this instruction. For example, if B = 21 H, C = 00 H and A = 3A H, then after the execution of the instruction STAX B, 3A H will be stored in the memory location 2100 H. i.e. [M 2100H ] = 3 AH The combination STAX H is not included in this instruction as MOV A, M performs the same operation.

[ ]

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XCHG (Exchange the contents of H-L register with D-E register) This is one byte instruction and no operand is needed with it. It exchanges the contents of H and L register with D and E registers respectively. i.e. [H] ↔ [D] and [L] ↔ [E ] For example: If H = 25 H , L = 32 H and D = 12 H, E = 1B H then after the execution of XCHG instruction, we have: H = 12 H, L = 1B H and D = 25 H, E = 32 H The instruction XCHG is generally used to keep track of more than one memory location at a time without using LDAX and STAX instructions. Let us write a program to add two numbers stored in memory locations 2100 H and 2201 H without using LDAX and STAX instructions. The answer is to be loaded in the memory location 2100 H. LXI H, 2201 H ; Loads H = 22 H and L = 01 H LXI D, 2100 H ; Loads D = 21 H and E = 00 H MOV A, M ; [A] ← [M 2201H ] XCHG ; H = 21 H, L = 00 H and D = 22 H, E = 01 H ADD M ; [A] ← [ A] + [M 2100 H ] MOV M, A ; [M 2100 H ] ← [ A] HLT In this program no LDAX and STAX instructions are used. DAA (Decimal Adjust the Accumulator) The DAA is one byte instruction and no operand is needed with this instruction. It adjusts the accumulator to packed BCD (Binary Coded Decimal) after addition of two BCDs. In other words, after addition of two hexadecimal numbers if this instruction is used then the result in decimal form is obtained. For this Auxiliary Carry Flag (AC) and Carry Flag (CY) take care of this instruction. It functions in two steps: 1. If the lower nibble (lower 4-bits) of the accumulator is greater than 9 or Auxiliary carry flag is set, then it adds 06 H to the accumulator. 2. Subsequently, if the higher nibble (higher 4-bits) of the accumulator is now greater than 9 or the carry flag (CY) is set, it adds 60 H to the accumulator. All the flags are affected with this instruction. Example 5.1 What will be the value of accumulator, CY and AC flags after the execution of the following program: MVI A, 38 H ADI 87 H DAA HLT Solution. A = 38 H 0011 1000 Adds 87 H 1000 0111 ----------------------

144

1011 1111 0000 0110 -----------------------1100 0101 0110 0000 ------------------------10010 0101

Lower nibble is more than 9 AC = 1 Upper nibble is more than 9

Result = 125 (Decimal) A=0010 0101

CY = 1

AC = 1

PCHL

(Copies H-L to PC) This is one byte instruction and no operand is needed with this instruction. It copies the contents of H-register to high-order byte of the program counter (PC) and the contents of L-register to low order byte of the program counter. i.e. [PC] ← [HL] [PCH ] ← [H] and [PCL] ← [L] For example if PC = 2106 H and HL = 2500 H then after the execution of the instruction PCHL will result: PC = 2500 H No flag is affected with the instruction. This instruction is basically an unconditional jump instruction as is evident from the above example. SPHL (Copies HL to Stack Pointer SP) This is also one byte instruction as no operand is used. The SPHL instruction copies the contents of H-register to high order byte stack pointer (SP) and the contents of L-register to low order byte of stack pointer (SP). [SP] ← [HL] i.e. [SPH] ← [H] and [SPL] ← [L]

None of the flags is affected with this instruction. For example if H = 23 H and L = 45 H and SP = 2501 H then after the execution of the instruction SPHL will result: SP = 2501 H This is another way of initialization the stack pointer. XTHL (Exchanges the top of the stack with H-L register pair) The XTHL is one byte instruction and does not require any operand. The top byte of the stack is exchanged with L-register and next byte of the stack is exchanged with Hregister. i.e. [L] ↔ [MSP ] and [H] ↔ [MSP +1 ] For example if H = 21 H L = 02 H and MSP =1A H MSP+1 = 2C H as shown in figure 5.8(a), then after the execution of the instruction XTHL will result: H = 2C H L = 1A H and MSP = 02 H MSP+1 = 21 H as shown in figure 5. 8(b). No flag is affected with the instruction.

145

Fig. 5.8 (a)

Fig. 5.8 (b)

5.4 TIMING DIAGRAM FOR 8085 INSTRUCTIONS The working of 8085 microprocessor can best be understood by considering the timing diagrams of its few instructions. The graphical representation depicting the necessary steps carried out in a machine cycle is known as Timing Diagram. As is well known that the total time required for the execution of an instruction is the time required to fetch and execute an instruction. i.e. Instruction Cycle = Instruction fetch + Instruction execution The instruction cycle may be of one, two or three bytes. During the fetch cycle, an instruction of the program (op code) is extracted from the memory locations and copied in the instruction register (IR) of C.P.U. The op code of the instruction copied in the instruction register (IR) is decoded during the execution cycle to perform the specific activities. It may further be mentioned that an instruction cycle may take one to five machine cycles. Generally, first machine cycle known as op code fetch cycle, has either four or six T-states and the remaining machine cycles called execution cycles, have two or three T-states. A T-state represents one clock cycle. The NOP is the shortest instruction which takes only one machine cycle with four T-states. However, the CALL is the longest instruction which takes five machine cycles with 18 T-states. Here the timing diagrams of a few instructions will be discussed.

5.4.1 Timing Diagram of MOV reg, M The timing diagram of the instruction

146

MOV reg, M is shown in figure 5.9. This is an indirect read instruction and takes two memory cycles (M1 and M2). The first machine cycle (M1) is known as instruction fetch cycle, during which the op code of the instruction is fetched from the memory. This machine cycle takes four Tstates. The second machine cycle M2 is known as the execution cycle during which the data from the memory location addressed by H-L register pair is transferred to the given register. The second machine takes three states. During the first T-state (T1) of M1 cycle, microprocessor sends the address of the memory location where the op code of the instruction MOV reg, M is stored, to the address lines. The high order byte of the PC (PCH) is placed on A8-A15 lines and it stays on till T4. The low order byte of PC (PCL) is placed on the address data lines (AD0-AD7) which stays on only during T1-state. For this purpose ALE (Address Latch Enable) signal gives a positive pulse midway through first T-state (T1), which latches the low order byte of the address into the memory chips. The IO / M signal goes low at the beginning of T1 state; this enables the peripheral chips for a memory operation rather than input/output operation. It is customary to represent the address lines by double sided waveforms as the address bits may be high or low (ref. fig. 5.9). MOV reg, M

Fig. 5.9 During the second T-state (T2) of this op code fetch cycle, program counter (PC) is incremented (PC = PC + 1). The address disappears from the address data bus (AD7AD0) at the beginning of T2 state. This is shown by dashed line indicating the data on the 147

bus is invalid or meaningless. At the beginning of T2 state RD signal goes low and remains low till the middle of the T3 state. During the third T-state (T3) of M1 machine cycle, the op code of the instruction is read out from the memory which is sent to the instruction register (IR) i.e. INSTR → IR . The fourth T-state (T4) of M1 machine cycle is denoted by X which indicates that this T-state is needed for the instruction decoding and other internal operations before the execution cycle. Now the second machine cycle M2 known as execution cycle starts. During the first T-state of this execution cycle the contents of H-L register pair are placed on the address bus and address data bus. Basically, it performs the same operation as the T1-state of M1 cycle. During T2 and T3 states of M2 machine cycle the data is read from the memory and copied in the specified register. This completes the instruction MOV reg, M. It may be noted that this instruction needs two machine cycles with 7 T-states. 5.4.2 Timing Diagram of MOV M, reg This is an indirect write instruction. The timing diagram of MOV M, reg instruction is shown in figure 5.10. The first three states of memory fetch cycle M1 are the same as for MOV reg, M. During fourth T-state (T4) of M1, the contents of specified register are copied in the temporary register. During the T1-state of second machine cycle M2, the contents of H-L pair are placed on the address and address data bus. As usual during this state ALE sends a high pulse. During T2 and T3 states of machine cycle M2, contents of temporary register are transferred (copied) to the specified address. Since it is memory write instruction, so at the beginning of T2-state WR signal activates (becomes low) and it remains low till half way through its T3-state. This instruction also takes two machine cycles with 7 T-states.

148

MOV M, reg

Fig. 5.10 5.4.3 Timing Diagram of MVI reg, data Figure 5.11 illustrates the timing diagram of the instruction MVI reg, data. This is an immediate move instruction. It is two byte instruction; one byte is used for the op code of the instruction and the other byte is used for the data. During T1, T2 states of op code fetch cycle M1 the op code of the instruction (INSTR) is loaded in the instruction register (IR). The operation for these T-states is similar to other instructions discussed earlier. The T4-state of this cycle M1 is for decoding. In the second machine cycle M2, the contents of the program counter (PC) is placed on the address and address data buses during its T1 state. This is the address of the second byte. During T2 of M2 cycle, the PC is incremented. At the same time memory is accessed and immediate read data is loaded to the specified register during T3-state of M2 machine cycle. This instruction takes two machine cycles with 7 T-states.

149

MVI reg, data

Fig. 5.11 5.4.4 Timing Diagram of MOV reg2, reg1 The timing diagram of MOV reg2, reg1 is shown in figure 5.12. This instruction copies the contents of reg2 to reg1. So T1, T2 and T3 states of the op code fetch cycle M1 as usual indicate PC OUT, increment state ( PC + 1 → PC ) , copying of the op code on the instruction to the instruction register ( INSTR → IR ) operations respectively. Accordingly, ALE sends a high pulse at the beginning of T1-state, RD activates (low) at the beginning of T2 state till the middle of T3 state till the middle of T3 state of M1 cycle. The IO / M signal becomes low at the beginning of T1 till the end of T3 of M2 machine cycle. During T4 state the contents of reg2 is copied in Temporary register ( reg 2 → TMP ). This instruction does not need address bus and address data bus during the second machine cycle M2. The only thing to happen during M2 cycle is the transfer of the contents of Temporary register to reg1, for which address and address data buses are not required. So time process starts i.e. during the second machine cycle M2 of the instruction MOV reg2, reg1, fetching operation of the next instruction will take place. This is called Fetch Execute Overlap (FEO). Because of FEO, the new address of PC is placed on the address and address data buses during T1 state of M2 machine cycle. Thus at the trailing

150

edge of ALE signal, this address is latched into the memory chips. The contents of temporary register are copied into reg1 at the T2 state of this machine cycle. This completes the execution MOV reg2, reg1 instruction. However at the same T-state, program counter is incremented. The op code of the next instruction is copied in IR during T3-state of M2. It may be mentioned here that as shown in figure 5.12, this instruction takes two machine cycles with 7 T-states; but because of FEO only one machine cycle with 4 Tstates are counted to fetch and execute this instruction. MOV reg2, reg1

Fig. 5.12 5.4.5 Timing Diagram of MVI M, data The timing diagram of MVI M, data instruction is shown in figure 5.13. This is a two byte instruction which takes 3 machine cycles with 10 T-states. The machine cycle M1 is the op code fetch cycle, whose operation has already been discussed. In the T1 state of M2 cycle, the incremented address of PC is latched into memory chips. The T2-state is the increment state and during the T3 state of M2 data is transferred to temporary register. This machine cycle is memory read cycle. The third machine cycle is basically memory write cycle during which the contents of temporary register are copied in the memory location addressed by H-L register pair. In the T1 state of the machine cycle M3, the contents of H-l register pair is placed on the address bus and address data bus. It is then latched in the memory chips. In T2 state the WR signal is low till the middle of T3 state of this cycle. So the contents of 151

temporary register are copied in MH-L location during T2 and T3 state of M3 machine cycle. MVI M, data

Fig. 5.13

152

5.4.6 Timing Diagram of XCHG Let us discuss the timing diagram of one byte instruction XCHG. Its timing diagram is shown in figure 5.14. It exchanges the contents of H-L register pair with contents of D-E register pair. The operation of M1 machine cycle of this instruction is similar to other instructions discussed above. In this instruction the contents of H-L and D-E register pairs are to be exchanged, so address bus and address data bus are not needed. For this the operation FEO (Fetch Execute Overlap) occurs and as usual the next instruction is fetched from the memory for the M2 machine cycle. However, during T2 state of this machine cycle the contents of H-E and D-E pairs are exchanged ( H − L ↔ D − E ). Because of FEO, XCHG instruction is considered to take one machine cycle with 4 T-states. XCHG

Fig. 5.14 5.4.7 Timing Diagram of LXI rp, dbyte The timing diagram of 3-byte instruction LXI rp, dbyte is shown in figure 5.15. It loads the low byte of dbyte (double byte data) to the lower register of the given register pair rp and high byte to the high register of rp. This instruction takes three memory cycles with 10 T-states. First machine cycle is the op code fetch cycle which fetches the

153

op code of the instruction using the same procedure as discussed above for the other examples. LXI rp, data

Fig. 5.15

154

In the T1-state of the second machine cycle, address bus and address data bus are used to fetch the second byte (low byte of dbyte), for which ALE is enable at the beginning to the middle of this T-state. During T2 state of M2, PC is incremented and at T3-state low byte of the dbyte is stored in lower register of rp (Low byte → rp L ). This is a read cycle so RD is low at the beginning of this T-state to the middle of T3 state. Same operation as for M2 is, therefore, performed during M3 machine cycle so that high byte of dbyte is stored in high register of register pair rp (High byte → rp H ). 5.4.8 Timing Diagram of IN byte The timing diagram of IN byte shown in figure 5.16 will now be discussed. This is an I/O read cycle and the microprocessor reads the data available at an input port or input device. The address of the port is of one byte given with the instruction. The data read out from the output port will be placed in the accumulator (A). This instruction is a two byte long and takes three memory cycles with 10 T-states. First machine cycle is an op code fetch cycle, the second is memory read cycle and the third is output read cycle. We are familiar with the op code fetch cycle M1. So the discussion will be made for the second and third machine cycles. In the T1-state of second machine cycle M2, the address of PC (incremented address) will be latched into the memory chips. At the beginning of T1 state ALE sends a high pulse. During the T2-state PC is incremented ( PC + 1 → PC ). Near the end of T2-state of M2, a byte appears on address data bus. During the T3-state of M2 machine cycle, this byte is copied in the W and Z registers (byte → Z, W), i.e. W and Z registers have the same byte. This byte is port address which is of 8 bits. During T1-state of the third machine cycle M3, IO / M signal goes high which enables the peripheral chips for an I/O operation rather than memory operation. During this T-state, the contents of W-register are placed on the address bus and the contents of Z-register on address data bus (WZ OUT). In case of I/O device or I/O port the address is only of 8 bit long and therefore, the address of I/O device is duplicated on both address bus and address data bus. During T2-state of M3 cycle, RD signal goes low which indicates that it is I/O read operation. The data read out from the input port (input device) will be copied in the accumulator during T2 and T3 states.

155

156

PROBLEMS 1. 2. 3. 4. 5. 6. 7.

8. 9. 10. 11. 12. 13. 14. 15. 16. 17.

18.

19. 20.

Draw and discuss the architecture of 8085 microprocessor. Mention various flags provided in 8085 microprocessor and discuss their roles. Discuss the functions of program counter, Stack pointer and status flags in the architecture of 8085 microprocessor. Discuss the role of address buffer and address data buffer in the architecture of 8085 microprocessor. Discuss the functions of the following signals of 8085 microprocessor: ALE, WR , RD , S0 and S1. Discuss LHLD address, SHLD address, LDAX rp and STAX rp instructions of 8085. Discuss the following instructions of 8085 XCHG, XTHL, SPHL and PCHL Which flags are affected by these instructions? Discuss DAA instructions of 8085. Explain how flags are affected with this instruction. Draw and discuss the timing diagram of MOV reg2, reg1. Draw and discuss the timing diagram of MOV reg, M. Draw and discuss the timing diagram of MOV M, reg. Draw and discuss the timing diagram of MVI reg, data. Draw and discuss the timing diagram of MVI M, data. Draw and discuss the timing diagram of LXI rp, dbyte. Draw and discuss the timing diagram of XCHG. Draw and discuss the timing diagram of IN byte. Discuss LDAX rp instruction of 8085. What instruction should be used to move the contents stored in memory location whose address is stored in H-L register pair. What instruction should be used to store the accumulator contents to the memory location addressed by D-E register pair? Discuss that instruction in detail. Discuss PCHL instruction of 8085. Explain how this instruction is said to be used as unconditional jump instruction. What will be contents of accumulator and flag register, after the execution of following program: MVI A, 47 H MVI B, 37 H ADD B DAA HLT __________

157

6 Programming of 8085 In this chapter assembly language programming of different programs will be discussed. It will help readers to go into the details of 8085 programming operations and their applications. For this, one is supposed to be well acquainted with 8085 instruction set discussed in the preceding chapters. Though some programming examples have also been discussed in these chapters, yet this chapter will exclusively deal with some more programming examples. The assembly language program written by the programmer in mnemonic form is also called as source program. The instructions, operand and data may be converted to binary (machine language) either by hand assembler or machine assembler. In case of hand assembler the hexadecimal data (op code / operand and data) are fed to the microprocessor kit through the hexadecimal key board. But in machine assembler, instructions (in mnemonic form) with data or operand are directly fed to the microprocessor kit through Alpha-numeric key board (computer key board). Here we are concerned with the assembly language program (source program). In computers high level language like C, C++, Pascal, BASIC etc are used, which are easier than the assembly language. The computer is used for the conversion of high level language to assembly language. The advantage of using assembly language is that it can directly go into the details of the microprocessor’s register and manipulate as the requirement. 6.1 SIMPLE PROGAMS The simple programs based on the instruction set of 8085 microprocessor are given in the following examples. Example 6.1. Write an assembly language program of 8085 to find 1’s complement of the data stored in memory location 2500 H and the result is to be stored in memory location 2501 H. Solution. Program: Label Mnemonics Operand Comments LDA 2500 H ; Load the data from 2500 H memory location to accumulator. CMA ; Complement the contents of accumulator (Converts in 1’s complement). STA 2501 H ; Store the result in memory location 2501 H. HLT ; Stop processing.

Example 6.2. Write an assembly language program of 8085 to find 2’s complement of the data stored in memory location 2100 H and the result is to be stored in memory location 2101 H. Solution. Program: Label Mnemonics Operand Comments LDA 2100 H ; Load the data from 2100 H memory location to accumulator. CMA ; Complement the contents of accumulator (Converts in 1’s complement). ADI 01 H ; 01 is added to the accumulator contents to get the 2’s complement. STA 2101 H ; Store the result in memory location 2101 H. HLT ; Stop processing. Example 6.3. Write an assembly language program of 8085 to find 1’s complement of n (decimal number) bytes of data stored in memory location starting at 2501 H. The number n (decimal number) is stored in memory location 2500 H. Store the result in memory locations starting at 2601 H. Solution. Program: Label Mnemonics Operand Comments LXI D, 2601 H ; Get first address of the destination in D-E register pair. LXI H, 2500 H ; Get H-L pair with 2500 H. MOV C, M ; Data in 2500 H is loaded to Cregister which will be used as counter. INXH ; Increment H-L register pair. LOOP MOV A, M ; Accumulator is loaded with the data. CMA ; Complement the contents of accumulator (Converts in 1’s complement) STAX D ; Store the result in memory location addressed by D-E register pair. INX D ; Increment D-E register pair. INX H ; Increment H-L register pair. DCR C ; Decrement the C-register data. JNZ LOOP ; If data in C-reg. is not zero jump to LOOP for next conversion. HLT ; Stop processing. Example 6.4. Write an assembly language program of 8085 to find 9’s complement of n bytes (in BCD) of data stored in memory location starting from 2501 H. The number n

159

(decimal number) is stored in memory location 2500 H. Store the result in memory locations starting from 2601 H. Solution. Program: Label Mnemonics Operand Comments LXI D, 2601 H ; Get first address of the destination in D-E register pair. LXI H, 2500 H ; Get H-L pair with 2500 H. MOV C, M ; Data in 2500 H is loaded to Cregister which will be used as counter. INX H ; Increment H-L register pair. LOOP MVI A, 99 H ; Get 99 H in accumulator. SUB M ; Subtract each byte by 99 H to get 9’s complement. STAX D ; Store the result in memory location addressed by D-E register pair. INX D ; Increment D-E register pair. INX H ; Increment H-L register pair. DCR C ; Decrement the C-register data. JNZ LOOP ; If data in C-reg. is not zero jump to loop for next conversion. HLT ; Stop processing. It is clear from this example that for 9’s complement each BCD byte is subtracted from 99. Example 6.5. Write an assembly language program of 8085 to find 2’s complement of a 16 bit number stored in memory locations 2101 H and 2102 H. The least significant byte is in 2101 H. The result is to be stored in memory locations 2103 H and 2104 H. Solution. Program: Label Mnemonics Operand Comments LXI H, 2101 H ; Get H-L pair with 2101 H. MVI B, 00 H ; Store 00 to register B which will be used to store carry. MOV A, M ; Accumulator is loaded with the data. CMA ; Complement the contents of accumulator (Converts in 1’s complement). ADI 01 H ; Add 01 H to the accumulator content to get 2’s complement. STA 2103 H ; Store the result in memory location 2103 H. JNC NXT ; If there is no carry jump to NXT. INR B ; Increment 1 to B-register as carry.

160

NXT

INX H MOV A,

; Increment H-L register pair for the second byte. ; Move the second byte to accumulator. ; Complement the contents of accumulator. ; Add carry stored in register B. ; Store in 2504 H. ; Stop processing.

M

CMA ADD B STA HLT

2504 H

From this example it is clear that 1 is added to the 1’s complement of LS byte and to the 1’s complement of MS byte 1 is added if there is a carry from the previous byte. Example 6.6. Write an assembly language program of 8085 to find 10’s complement of a 16 bit number (BCD) stored in memory locations 2101 H and 2102 H. The least significant byte is in 2101 H. The result is to be stored in memory locations 2103 H and 2104 H. Solution. Program: Label Mnemonics Operand Comments LXI H, 2101 H ; Get H-L pair with 2101 H. MVI B, 00 H ; Store 00 to register B which will be used to store carry. MVI A, 99 H ; Store 99 in accumulator SUB M ; Subtract each byte by 99 H to get 9’s complement. ADI 01 H ; Add 01 H to the accumulator content to get 10’s complement. STA 2103 H ; Store the result in memory location 2103 H. JNC NXT ; If there is no carry jump to NXT. INR B ; Increment 1 to B-register as carry. NXT INX H ; Increment H-L register pair for the second byte. MVI A, 99 H ; Store 99 in accumulator SUB M ; Subtract each byte by 99 H to get 9’s complement. ADD B ; Add carry stored in register B. STA 2104 H ; Store in 2104 H. HLT ; Stop processing. From this example it is clear that 1 is added to the 9’s complement of LS byte and to the 9’s complement of MS byte 1 is added if there is a carry from the previous byte. Example 6.7. Write an assembly language program of 8085 to find 2’s complement of N bytes ( N ≥ 2 ). The number of bytes N in hexadecimal is stored in 2100 H. The bytes are stored in memory locations starting at 2101 H. The least significant byte is in 2101 H. The result is to be stored in memory locations starting at 2201 H.

161

Solution. Program: Label

Mnemonics LXI H, LXI D, MOV C,

Operand 2100 H 2201 H M

Comments ; Get H-L pair with 2100 H. ; Get D-E pair with 2201 H. ; Get the number N in c-register to be used as counter. INX H ; Increment H-L pair. MOV A, M ; Accumulator is loaded with first data. CMA ; Complement the contents of accumulator (Converts in 1’s complement). ADI 01 H ; Add 01 H to the accumulator content to get 2’s complement. STAX D ; Store the result in memory location addressed by D-E pair. JNC NXT ; If there is no carry jump to NXT. MVI B, 01 H ; Store 01 to B-register as carry. JMP NXT1 ; Jump to NXT1. NXT MVI B, 00 H ; Store 00 to B-register as carry. NXT1 DCR C ; Decrement C-reg. LOOP INX H ; Increment H-L pair. INX D ; Increment D-E pair. MOV A, M ; Move the next byte to accumulator. CMA ; Complement the contents of accumulator. ADD B ; Add carry stored in register B. STAX D ; Store in the memory location addressed by D-E pair. JNC NXT2 ; If there is no carry jump to NXT2. MVI B, 01 H ; Store 01 to B-register as carry. JMP NXT3 ; Jump to NXT3. NXT2 MVI B, 00 H ; Store 00 to b-register as carry. NXT3 DCR C ; Decrement C-reg. JNZ LOOP ; If not zero jump to LOOP. HLT ; Stop processing. Example 6.8. Write an assembly language program of 8085 to find 10’s complement of N bytes ( N ≥ 2 ). The number of bytes N in hexadecimal is stored in 2100 H. The bytes are stored in memory locations starting at 2101 H. The least significant byte is in 2101 H. The result is to be stored in memory locations starting at 2201 H. Solution. Program: Label Mnemonics Operand Comments LXI H, 2100 H ; Get H-L pair with 2100 H. LXI D, 2201 H ; Get D-E pair with 2201 H.

162

MOV C,

M

INX H MVI A, SUB M

99 H

ADI

01 H

; Get the number N in c-register to be used as counter. ; Increment H-L pair. ; Accumulator is loaded with 99 H. ; Get the 9’s Complement of the number stored in location addressed by H-L pair. ; Add 01 H to the accumulator content to get 2’s complement. ; Store the result in memory location addressed by D-E pair. ; If there is no carry jump to NXT. ; Store 01 to B-register as carry. ; Jump to NXT1. ; Store 00 to b-register as carry. ; Decrement C-reg. ; Increment H-L pair. ; Increment D-E pair. ; Get 99 in accumulator. ; Get 9’s Complement of the contents of accumulator. ; Add carry stored in register B to get 10’s complement. ; Store in the memory location addressed by D-E pair. ; If there is no carry jump to NXT2. ; Store 01 to B-register as carry. ; Jump to NXT3. ; Store 00 to b-register as carry. ; Decrement C-reg. ; If not zero jump to LOOP. ; Stop processing.

STAX D

NXT NXT1 LOOP

JNC MVI B, JMP MVI B, DCR C INX H INX D MVI A, SUB M

NXT 01 H NXT1 00 H

99 H

ADD B STAX D

NXT2 NXT3

JNC MVI B, JMP MVI B, DCR C JNZ HLT

NXT2 01 H NXT3 00 H LOOP

Example 6.9. Write an assembly language program of 8085 to combine two hex nibbles stored in 2500 H and 2501 H memory locations, to form a byte. The least significant nibble is stored in 2500 H and most significant nibble is stored in 2501 H. The byte thus combined should be stored in 2502 H. (Let 08 H is stored in 2500 H and 09 H is stored in 2501 H, after the program is executed 2502 H should be loaded with the combined byte 89 H). Solution. Program: Label Mnemonics Operand Comments LXI H, 2500 H ; Get H-L pair with 2500 H. MOV A, M ; Data in 2500 H is loaded to Accumulator. RLC ; Rotate left

163

RLC RLC RLC

; Rotate left ; Rotate left ; Rotate left (Rotated left four times so that it is moved to MS nibble). ; Increment H-L register pair. ; Oring of two nibbles combines them to form a byte in accumulator. ; Increment H-L register pair. ; Move the accumulator content (required byte) to the memory location addressed by H-L register pair. ; Stop processing.

INX H ORA M

INX H MOV M,

A

HLT

Example 6.10. Write an assembly language program of 8085 to separate a hexadecimal number into two nibbles. The hexadecimal number is stored in 2501 H memory location. The least significant nibble of the byte is to be stored in 2502 memory location and the most significant nibble is to be stored in 2503 H memory location. (Suppose 3A H is a byte stored in memory location 2501 H and the lower nibble 0A should be stored in 2502 H and 03 should be stored in 2503 H) Solution. Program: Label

Mnemonics LXI H, MOV A,

Operand 2501 H M

MOV B,

A

ANI

0F H

INX H MOV M,

A

MOV A,

B

ANI INX H MOV M,

F0 H A

HLT

164

Comments ; Get H-L pair with 2501 H. ; Data in 2501 H is loaded to Accumulator. ; Accumulator content are also loaded to B register. ; Mask off the first four digits (higher nibble). ; Increment H-L register pair. ; Lower nibble is loaded to the memory location addressed by H-L register pair. ; Get the byte again in the accumulator. ; Mask off the lower nibble. ; Increment H-L register pair. ; Higher nibble is loaded to the memory location addressed by H-L register pair. ; Stop processing.

Example 6.11. Write an assembly language program of 8085 to check a hexadecimal number stored in 2500 H memory location for odd or even parity. If the parity is even store data EE H to memory location 2501H otherwise store 00 H in 2501 H. Solution. Program: Label

EVEN

DONE

Mnemonics LXI H, MOV A,

Operand 2500 H M

ORA A JPE

EVEN

INX H MVI M,

00 H

JMP INX H MVI M,

DONE EE H

HLT

Comments ; Get H-L pair with 2500 H. ; Data in 2500 H is loaded to Accumulator. ; Set the flag. ; Check for even parity, if parity is even jump to EVEN. ; Increment H-L register pair. ; Load 00 H to the memory location addressed by H-L register pair. ; Jump to DONE. ; Increment H-L register pair. ; Load EE H to the memory location addressed by H-L register pair. ; Stop processing.

Example 6.12. n (decimal number) data bytes are stored in the memory locations starting at 2501 H. Write an assembly language program of 8085 to check if 12 H is stored in any of the given locations. If any of the locations has 12 H then store 12 H in that location else load 00 H in that memory location. Solution. Program: Label

LOOP

NXT

Mnemonics LXI H, MOV C,

Operand 2500 H M

INX H MOV A,

M

CPI

12 H

JZ MVI M,

NXT 00 H

JMP MVI M,

DONE 12 H

165

Comments ; Get H-L pair with 2500 H. ; Data in 2500 H is loaded to C reg. which is used as the counter. ; Increment H-L register pair. ; Load the content of MHL to accumulator. ; Compare if the accumulator data are 12 H. ; If it is 12 H then jump to NXT. ; Else load 00 H to the memory location addressed by H-L register pair. ; Jump to DONE. ; Load 12 H to the memory location addressed by H-L register pair.

DONE

DCR C JNZ

; Decrement the content of C-reg. for next byte. ; If the contents of C-reg. are not zero then jump to LOOP. ; Stop processing.

LOOP

HLT

Example 6.13. 16 data bytes are stored in memory locations 2001 H to 2010 H. Write an assembly language program of 8085 to transfer this block of data bytes to memory locations 2501 to 2510 H. Solution. Program: Label

LOOP

Mnemonics LXI H, LXI D,

Operand 2001 H 2501 H

MVI C,

10 H

MOV A,

M

STAX D

INX H INX D DCR C JNZ

LOOP

HLT

Comments ; Get H-L pair with 2001 H. ; Get the address of the memory location (destination) in D-E register pair ; Get 10 H (1610) Data in C register which is used as the counter. ; Load the content of MHL to accumulator. ; Load the content of accumulator to the memory locations addressed by D-E register pair. ; Increment H-L register pair. ; Increment D-E register pair. ; Decrement the content of C-reg. for next byte. ; If the contents of C-reg. are not zero then jump to LOOP. ; Stop processing.

Example 6.14. 16 data bytes are stored in memory locations 2001 H to 2010 H. Write an assembly language program of 8085 to transfer this block of data bytes to memory locations 2501 to 2510 H in the reverse order (i.e. the data of 2001 is to transferred to 2510 H and data of 2002 H to 250F H and so on). Solution. Program: Label

Mnemonics LXI H, LXI D,

Operand 2001 H 2510 H

MVI C,

10 H

166

Comments ; Get H-L pair with 2001 H. ; Get the address of the memory location (destination) in D-E register pair ; Get 10 H (1610) Data in C register which is used as the counter.

LOOP

MOV A,

M

; Load the content of MHL to accumulator. ; Load the content of accumulator to the memory locations addressed by D-E register pair. ; Increment H-L register pair. ; Decrement D-E register pair. ; Decrement the content of C-reg. for next byte. ; If the contents of C-reg. are not zero then jump to LOOP. ; Stop processing.

STAX D

INX H DCX D DCR C JNZ

LOOP

HLT

Example 6.15. Write an assembly language program of 8085 to clear the memory locations starting at 2001 (i.e. each location should have 00 H). The length of data bytes is given in 2000 H memory location. Solution. Program: Label

LOOP

Mnemonics LXI H, MOV C, XRA A INX H MOV M,

Operand 2000 H M

A

DCR C JNZ

LOOP

HLT

Comments ; Get H-L pair with 2000 H. ; Use C register as counter. ; Clear the accumulator. ; Increment H-L register pair. ; Load the accumulator content to the memory location. ; Decrement the content of C-reg. for next byte. ; If the contents of C-reg. are not zero then jump to LOOP. ; Stop processing.

Example 6.16. Write an assembly language program of 8085 to add five bytes of data stored in memory locations starting at 2000 H. If the sum generates a carry, stop addition and store 01 H to the memory location 2501 H; else continue addition and store the sum at 2501 memory location.. Solution. Program: Label

LOOP

Mnemonics LXI H, MVI C,

Operand 2000 H 05 H

XRA A ADD M

167

Comments ; Get H-L pair with 2000 H. ; Store the number of data bytes in C register as counter. ; Clear the accumulator and CY flag. ; Add the byte in accumulator.

NXT

JC INX H DCR C

NXT

JNZ

LOOP

STA

2501 H

HLT MVI A,

01 H

STA HLT

; If there is a carry jump to NXT. ; Increment the H-L register pair. ; Decrement the content of C-reg. for next byte. ; If the contents of C-reg. are not zero then jump to LOOP. ; Store the sum in memory location 2501 H. ; Stop processing. ; If carry occurs load 01 to accumulator. ; Store 01 H to 2501 H. ; Stop processing.

2501 H

Example 6.17. Write an assembly language program of 8085 to add five bytes of data stored in memory locations starting at 2000 H. The sum may be more than one byte. Store the result at two consecutive memory locations2500 H and 2501 H. Solution. Program: Label

LOOP

NXT

Mnemonics LXI H, MVI C,

Operand 2000 H 05 H

XRA A MOV B,

A

ADD M JNC INR B INX H DCR C

NXT

JNZ

LOOP

LXI H,

2500 H

Comments ; Get H-L pair with 2000 H. ; Store the number of data bytes in C register as counter. ; Clear the accumulator and CY flag. ; Store the accumulator contents to B-register also for the carry. ; Add the byte in accumulator. ; If there is a no carry jump to NXT. ; Increment B as carry is generated. ; Increment the H-L register pair. ; Decrement the content of C-reg. for next byte. ; If the contents of C-reg. are not zero then jump to LOOP. ; Store H-L pair with 2500 H (destination address).

MOV M, A INX H ; Store the sum to 2500 H. MOV M, B ; Content of B are stored in 2501 H. HLT ; Stop processing. Example 6.18. Write a program in assembly language of 8085 to test 6th bit (D6 bit) of a byte stored at 2500 H memory location. If the bit D6 is zero then store 00 H at 2501 H else store the same number at 2501 H. Solution. Program:

168

Label

Mnemonics LXI H, MOV A, ANI JZ MOV A,

Operand 2500 H M 40 H END M

Comments ; Get H-L pair with 2500 H. ; Store the byte in accumulator ; Reset all the bits except D6. ; If this bit is zero jump to END. ; Store the byte in accumulator again. INX H ; Increment H-L pair. MOV M, A ; The byte is stored in 2501 H. HLT ; Stop processing. END XRA A ; Clear accumulator. INX H ; Increment H-L pair. MOV M, A ; 00 H is stored in 2501 H. HLT ; Stop processing. Example 6.19. Write an ALP (Assembly Language Program) of 8085 to find logical OR and exclusive OR of two numbers stored at 2501 H and 2502 H memory locations. The results should be stored at 2503 H (logical OR operation) and 2504 H (XOR operation) memory locations. Solution. Program: Label Mnemonics Operand Comments LXI H, 2501 H ; Get H-L pair with 2501 H. MOV B, M ; Store the byte in B-register. MOV A, B ; Store this byte in accumulator also. INX H ; Increment H-L pair. MOV C, M ; Store second byte to C register. ORA C ; Logical OR of two bytes. INX H ; Increment H-L pair. MOV M, A ; Store the result (OR) in 2503 H. MOV A, B ; Load the first number in accumulator. XRA C ; Ex-OR the two number. INX H ; Increment H-L pair. MOV M, A ; Store the result (XOR) HLT ; Stop processing. Example 6.20. Write an ALP (Assembly Language Program) for 8085 to shift an 8-bit number left by one bit. The number is stored in 2101 H memory location. The result is to be stored in 2102 H memory location. Solution. Program: Label Mnemonics Operand Comments LDA 2101 H ; Get the number is accumulator. ADD A ; Shift it left by one bit. STA 2102 H ; Store the result in 2502 H. HLT ; Stop processing.

169

Example 6.21. Write an ALP 8085 to shift a 16-bit number left by one bit. The number is stored in 2101 H and 2102 H memory locations. The result is to be stored in 2103 H and 2104 H memory locations. Solution. Program: Label Mnemonics Operand Comments LHLD 2101 H ; Get the 16 bit number in H-L register pair. DAD H ; Shift left by one bit. SHLD 2103 H ; Store the result in 2103 H and 2104 H memory locations. HLT ; Stop processing. 6.2 PROGAMS ON CODE CONVERSION The programs on code conversion will now be discussed. 6.2.1 BCD to Binary Conversion Suppose we have 0 to 99 decimal numbers (BCD numbers) and we wish to convert any of these numbers to its equivalent binary number, we proceed in the following way: For example 49 (4 x 10 + 9) is the given decimal number, its binary equivalent is (00011 00012 = 31 H). Step I Unpack the number in MSD and LSD form. 0000 1001 LSD in four least significant nibble in a register. 0000 0100 MSD in four least significant nibble in anther register. Step II Multiply MSD by decimal number 10. or MSD is added 10 times with 0000. So we get (4 x 10 = 0010 1000). Step III ADD LSD to the result of step II. i.e. 00101000 + 00001001 = 00110001 Hence we get the result. Example 6.22. A BCD number (0 to 99) is stored in a memory location 2500 H, write an ALP of 8085 to convert the BCD number into its equivalent binary number. Store the result in 2600 H memory location. Solution. Main Program: Label Mnemonics Operand Comments LXI SP, XXXX H ; Initialize the stack pointer. LXI H, 2500 H ; Get H-L pair with 2500 H. LXI D, 2600 H ; Get D-E pair with 2600 H. MOV A, M ; Load the byte to accumulator. CALL CONV ; Call conversion subroutine program. STAX D ; Store the result in 2600 H. HLT Subroutine Program:

170

Label CONV

Mnemonics PUSH D

Operand

PUSH H

SUM

ANI MOV C, MOV A, ANI RRC RRC RRC RRC MOV D, XRA A MVI E,

0F H A M F0 H

0A H

ADD D DCR E JNZ

SUM

A

ADD C POP H POP D RET

6.2.2

Comments ; Push the contents of D-E register pair to stack. ; Push the contents of H-L register pair to stack. ; Separate LSD ; Store it to C-register. ; Load the byte to accumulator again. ; Separate MSD. ; Rotate right four times ; to shift MSD to four ; least significant nibble ; of accumulator. ; Store MSD to D register. ; Clear accumulator. ; Get 0A (decimal number 10) to Eregister. ; Add MSD ten times to 00 H. ; Decrement C ; If addition not complete then move to SUM. ; Add LSD to 10 X MSD ; Pop the contents of H-L pair. ; Pop the contents of D-E pair. ; Go back to main program.

Binary to BCD (Unpacked) Conversion

For example binary number is 1111 1111 (FF H). Its decimal equivalent is 25510 having the unpacked BCD numbers as 05 (0000 0101) BCD 1 05 (0000 0101) BCD 2 02 (0000 0010) BCD 3 The procedure for converting the 8 bit binary number (0000 0000 to 1111 1111) into unpacked BCD number is given in the following steps. Step I If the number is less than 100 go to step II. If the number is more than 100, divide the number by 100 or subtract 100 repeatedly till the reminder is less than 100. The quotient is MS BCD (BCD 3). Step II If the number (or remainder) is less than 10, go to step III. If number is >10 < 100, then subtract 10 repeatedly till the remainder is less than 10. The quotient is BCD 2. Step III The remainder from step II is BCD 1.

171

Example 6.23. A binary number (between 00 H to FF H) is stored in a memory location 2500 H, write an ALP of 8085 to convert this number into BCD number. Store each BCD as unpacked BCD digit in the memory locations at 2601 H to 2603 H. Solution. Main Program: Label Mnemonics Operand Comments LXI SP, XXXX H ; Initialize the stack pointer. LXI H, 2500 H ; Get H-L pair with 2500 H. MOV A, M ; Load the byte to accumulator. CALL CONV ; Call conversion subroutine program. HLT Subroutine Program 1: Label Mnemonics Operand Comments CONV LXI H, 2601 H ; Get H-L pair with 2601 H. MVI B, 64 H ; Load 100 in B-reg. CALL CONV1 ; Call another subroutine program for the division by 100. MVI B, 0A H ; Load 10 in B-reg. CALL CONV1 ; Call the subroutine again for the division by 10. MOV M, A ; Load the accumulator contents to the memory location. RET ; Go back to main program. Subroutine Program 2: Label Mnemonics Operand Comments CONV1 MVI M, FF H ; Get FF H in the MH-L. NXT INR M ; Increment [M H − L ] SUB B ; Subtract the content of B from accumulator. JNC NXT ; Jump to NXT if no carry. ADD B ; Add the contents of B to accumulator. INX H ; Increment H-L register pair. RET ; Go back. Example 6.24. Write ALP of 8085 for the following statement: A set of three packed BCD numbers (six digits or three bytes) are stored in memory locations starting at 2500 H. The seven segment codes of the digits 0 to 9 for common cathode LED are stored in memory locations starting at 2050 H; and the answer is to be stored in memory locations starting at 2070 H. Solution. Main Program: Label Mnemonics Operand Comments LXI SP, XXXX H ; Initialize the stack pointer. LXI H, 2500 H ; Get H-L pair with 2500 H.

172

MVI D,

03 H

CALL

CONV

HLT Subroutine Program 1: Label Mnemonics CONV LXI B, NXT MOV A, ANI RRC RRC RRC RRC CALL

INX B MOV A, ANI CALL

; Number of bytes to be converted is placed in D-register. ; Call conversion subroutine program.

Operand 2070 H M F0 H

SEGMENT

M 0F H SEGMENT

INX B INX H DCR D JNZ RET Subroutine Program 2: Label Mnemonics SEGMENT PUSH H

NXT

Operand

LXI H, ADD L

2050 H

MOV L, MOV A,

A M

STAX B

173

Comments ; Get B-C pair with 2070 H. ; Move the content of [M H − L ] to accumulator. ; Separate MSD. ; Rotate right four times ; to shift MSD to four ; least significant nibble ; of accumulator. ; Call subroutine program for the conversion of unpacked BCD to seven segment. ; Increment B-C register pair. ; Get the byte again. ; Separate LSD. ; Call subroutine program for the conversion of unpacked BCD (LSD) to seven segment. ; Increment B-C register pair. ; Increment H-L register pair. ; Decrement the contents of D register. ; If the content in D register is not then jump to NXT for next byte. ; Return to main program. Comments ; Push the contents of H-L register pair to stack. ; Get H-L pair with 2050 H. ; Add the content of L register to accumulator to get right location for the digit from the look-up table. ; Store it to L-register. ; Load the corresponding data from the look-up table to accumulator. ; Store the result in the memory location addressed by B-C register pair.

POP H

; Get the contents of H-L register pair from the stack. RET ; Go back DATA (in the form of look-up table) is stored in the following memory locations: 2050 H 3F H (Digit 0) 2051 H 06 H (Digit 1) 2052 H 5B H (Digit 2) 2053 H 4F H (Digit 3) 2054 H 66 H (Digit 4) 2055 H 6D H (Digit 5) 2056 H 7D H (Digit 6) 2057 H 07 H (Digit 7) 2058 H 7F H (Digit 8) 2059 H 6F H (Digit 9) The 3F H data is given for the digit 0. It is clear from the figure 6.1.

Fig. 6.1 Binary to ASCII Conversion ASCII (American Standard Code for Information Interchange) is a most commonly used alphanumeric code. It is a seven bit code. The hexadecimal numbers 30 to 39 (0011 0000 to 0011 1001) represent 0 to 9 ASCII decimal numbers. Similarly, 41 H to 5A H (0100 0001 to 0101 1010) represent capital letters A to Z in ASCII. For example, the ASCII representation of a binary number 8E is 38 H and 45 H (as 8 is represented by 0011 1000 or 38 H; and E is represented by 0100 0101 or 45 H). The following steps are carried out for the conversion of Binary to ASCII

6.2.3

Step I

First separate the LSD and MSD of the given binary number (or byte). Each digit is then converted to ASCII. Step II If the digit is less than 10 (0A H) then add 30 H (0011 0000) to the binary number else add 37 H (0011 0111). For binary number 8E H, 30 is added to 08 and we get 38 H (the ASCII Code for 8) and 37 is added to 0E H to get 45 H (the ASCII Code for E). Example 6.25. An eight bit binary number is stored in 2500 H. Write an ALP for 8085 to convert the binary number to its equivalent ASCII code. The ASCII code for most 174

significant binary digit should be stored to 2601 H location; and the code for least significant binary digit should be stored to 2602 H location. Solution. Main Program: Label Mnemonics Operand Comments LXI SP, XXXX H ; Initialize the stack pointer. LXI H, 2500 H ; Get H-L pair with 2500 H. LXI D, 2601 H ; Get D-E pair with 2601 H. MOV A, M ; Move the content of [M H − L ] to accumulator. MOV B, A ; Move the accumulator content to B-register. RRC ; Rotate right four times RRC ; to shift MSD to four RRC ; least significant nibble RRC ; of accumulator. CALL ASCII ; Call the subroutine to convert MSD to ASCII. STAX D ; Store the ASCII code of MS digit to the memory location addressed by D-E register pair. INX D ; Increment D-E register pair. MOV A, B ; Move the binary number again to accumulator. CALL ASCII ; Call the subroutine to convert LSD to ASCII. STAX D ; Store the ASCII code of LS digit to the memory location addressed by D-E register pair. HLT ; Stop processing. Subroutine Program: Label ASCII

NXT

6.2.4

Mnemonics ANI CPI JC ADI ADI RET

Operand 0F H 0A NXT 07 H 30 H

Comments ; Isolate MS digit. ; Compare with 10 (0A H). ; If it less than 10, jump to NXT. ; Else add 07 H. ; Add 30 H. ; Go back to main program.

ASCII to Binary Conversion The following steps are carried out to convert the ASCII code to binary (Hex):

Step I Step II

Subtract 30 H (0011 0000) from the given binary (Hex) number. If the difference after subtraction in step I is less than 10, then it is the required binary (Hex) number.

175

Step III

If the difference after subtraction in step II is more than 10 then subtract 07 also from it. This will then give the required binary (Hex) number. Example 6.26. An ASCII number is stored in 2500 H memory location. Write an ALP for 8085 to convert this number into its equivalent binary (Hex) number and store it to 2501 memory location. Solution. Main Program: Label Mnemonics Operand Comments LXI SP, XXXX H ; Initialize the stack pointer. LXI H, 2500 H ; Get H-L pair with 2500 H. MOV A, M ; Move the content of [M H − L ] to accumulator. CALL CONV ; Call the subroutine to convert ASCII to binary. INX H ; Increment H-L register pair. MOV M, A ; Store the binary number to required memory location. HLT ; Stop processing. Subroutine Program: Label Mnemonics CONV SUI CPI RC

Operand 30 H 0A

Comments ; Subtract 30 H from accumulator. ; Compare with 10 (0A H). ; If it less than 10 go back to main program. SUI 07 H ; Else subtract 07 H. RET ; Go back to main program. 6.3 PROGAMS ON ADDITION AND SUBTRACTION Now we shall take up the problems on BCD or decimal addition and subtraction of two bytes or multibyte. These problems are self explanatory and can be understood by considering proper logic. Example 6.27. Write an ALP for 8085 to add two 16-bit numbers. The augend’s LS byte is stored in 2101 H and MS byte in 2102 H. The addend’s LS and MS byte are stored in 2103 H and 2104 H respectively. The result is to be stored in 2105 H to 2107 H. Solution. Main Program: Label Mnemonics Operand Comments LHLD 2101 H ; Load the H-L pair direct with the contents of 2101 H and 2102 H Locations. XCHG ; Exchange the contents of H-L and D-E pair. LHLD 2103 H ; Load the H-L pair direct with the contents of 2103 H and 2104 H Locations.

176

MVI C, DAD D

00 H

; Store 00 H to C register for carry. ; Add the contents of H-L and D-E register pair and result is in H-L pair. JNC NXT ; If there is no carry after the addition jump to NXT. INR C ; Increment the carry. NXT SHLD 2105 H ; Store the contents in the required locations. MOV A, C ; Move carry to accumulator. STA 2107 H ; Store carry in 2107 H. HLT ; Stop processing. Example 6.28. Write an ALP for 8085 to add two N byte numbers. The augend’s bytes are stored in memory locations starting at 2101 H and the addend’s bytes are stored in memory locations starting at 2201 H. The number N is stored in memory location 2100 H. The result is to be stored in the memory locations starting at 2201 H. Solution. Main Program: Label Mnemonics Operand Comments LXI H, 2100 H ; Get H-L pair with 2100 H. MOV C, M ; Move the number N to C-register for counter. INX H ; Increment the H-L pair. LXI D, 2201 H ; Get D-E pair with 2201 H. XRA A ; Clear the accumulator and carry flag. LOOP LDAX D ; Get the addend byte to accumulator. ADC M ; Add with carry the two bytes. MOV M, A ; Store the result in the location addressed by H-L pair. INX D ; Increment the D-E pair. INX H ; Increment the H-L pair. DCR C ; Decrement C. JNZ LOOP ; If C is not zero, then jump to LOOP. HLT ; Stop processing. Example 6.29. Write an ALP for 8085 to add two N byte numbers. The augend’s bytes are stored in memory locations starting at 2101 H and the addend’s bytes are stored in memory locations starting at 2201 H. The number N is stored in memory location 2100 H. The result should in decimal form and is to be stored in the memory locations starting at 2201 H. Solution. Main Program: Label Mnemonics Operand Comments

177

LXI H, MOV C,

2100 H M

; Get H-L pair with 2100 H. ; Move the number N to C-register for counter. INX H ; Increment the H-L pair. LXI D, 2201 H ; Get D-E pair with 2201 H. XRA A ; Clear the accumulator and carry flag. LOOP LDAX D ; Get the addend byte to accumulator. ADC M ; Add with carry the two bytes. DAA ; Decimal adjust the accumulator for the result in decimal form. MOV M, A ; Store the result in the location addressed by H-L pair. INX D ; Increment the D-E pair. INX H ; Increment the H-L pair. DCR C ; Decrement C. JNZ LOOP ; If C is not zero, then jump to LOOP. HLT ; Stop processing. It may be noted from this example that DAA (decimal adjust the accumulator) instruction is used after ADC M for the conversion of the result in decimal form. Example 6.30. Write an ALP for 8085 for multibyte (N bytes) subtraction. The number of bytes (N) is stored in 2100 H location. The minuend bytes are stored in the memory locations starting at 2101 H and the subtrahend bytes are stored in the memory locations starting at 2201 H. The answer should be stored in the memory locations starting at 2101 H. Solution. Main Program: Label Mnemonics Operand Comments LXI H, 2100 H ; Get H-L pair with 2100 H. MOV C, M ; Move the number N to C-register for counter. INX H ; Increment the H-L pair. LXI D, 2201 H ; Get D-E pair with 2201 H. XRA A ; Clear the accumulator and carry flag. LOOP LDAX D ; Get the addend byte to accumulator. SBB M ; Subtract with borrow the contents of [M H − L ] from the accumulator contents. MOV M, A ; Store the result in the location addressed by H-L pair. INX D ; Increment the D-E pair. INX H ; Increment the H-L pair.

178

DCR C JNZ

; Decrement C. ; If C is not zero, then jump to LOOP. ; Stop processing.

LOOP

HLT Decimal Subtraction It may be noted from the above example that SBB M (subtract with borrow) instruction is used for the subtraction. The result will not be obtained in the decimal form as DAA instruction can not be used after Subtract instructions. For decimal subtractions, the subtrahend number should be converted to its equivalent 10’s complement which will then be added to minuend. Example 6.31. Write an ALP for 8085 to subtract 78 from 96. The answer in decimal form should be stored in 2100 H memory location. Solution. Main Program: Label Mnemonics Operand Comments MVI C, 96 H ; Get 96 in C register. MVI B, 78 H ; Get 78 in B register. MVI A, 99 H ; Get 99 in accumulator. SUB B ; Subtract the content of B-register from 99 to get the 9’s complement of 78. INR A ; Increment accumulator to get 10’s complement. ADD C ; Add the content of C to the accumulator. DAA ; Decimal adjust the accumulator, to get the answer in decimal for. STA 2100 H ; Store the answer in decimal form at 2100 H location. HLT ; Stop processing. Example 6.32. Write an ALP for 8085 for multibyte (N bytes) decimal subtraction. The number of bytes (N) is stored in 2100 H location. The minuend bytes are stored in the memory locations starting at 2101 H and the subtrahend bytes are stored in the memory locations starting at 2201 H. The answer obtained in decimal form should be stored in the memory locations starting at 2101 H. Solution. Main Program: Label Mnemonics Operand Comments LXI SP, XXXX H ; Initialize the stack pointer. LXI H, 2100 H ; Get H-L pair with 2100 H. MOV C, M ; Move the number N to C-register for counter. INX H ; Increment the H-L pair. LXI D, 2201 H ; Get D-E pair with 2201 H. LDAX D ; Get the subtrahend byte in accumulator.

179

MOV B,

A

; Move the accumulator content to Bregister. MVI A, 99 H ; Store 99 to accumulator. SUB B ; Get 9’s complement of the subtrahend. INR A ; Get 10’s complement of the subtrahend. ADD M ; Add 10’s complement of the subtrahend to minuend. DAA ; Give the answer in decimal form. PUSH PSW ; Push the carry to stack. MOV M, A ; Store the result in the location addressed by H-L pair. LOOP INX D ; Increment the D-E pair. INX H ; Increment the H-L pair. LDAX D ; Get the second number to accumulator. MOV B, A ; Store it to B-register. MVI A, 99 H ; Store 99 to accumulator. SUB B ; Get 9’s complement. MOV B, A ; Store it to B-register. POP PSW ; Get the carry of the previous addition from the stack. MOV A, B ; Get the B-register content to accumulator. ADC M ; Add with carry. DAA ; Give the answer in decimal form. PUH PSW ; Store the carry to stack for further addition. MOV M, A ; Store the result in the memory location addressed by H-L register pair. DCR C ; Decrement the content of Cregister. JNZ LOOP ; If C is not zero, then jump to LOOP. HLT ; Stop processing. 6.4 PROGAMS TO FIND LARGEST OR SMALLEST NUMBER Example 6.33 Write an ALP for 8085 to find the larger of two numbers stored in memory locations 2101 H and 2102 H. Store the result in memory location 2103 H. Solution. Main Program: Label Mnemonics Operand Comments LXI H, 2101 H ; Get H-L pair with 2101 H. MOV A, M ; Move the first number in accumulator.

180

INX H CMP M

NXT

JNC

NXT

MOV A, INX H MOV M,

M

; Increment the H-L pair. ; Compare the second number with first number. ; If the accumulator content is larger then jump to NXT. ; Else move [M H − L ] to accumulator. ; Increment the H-L pair. ; Store the result in the required memory location. ; Stop processing.

A

HLT

Note: To get the smaller number from the given two numbers, use the instruction JC in place of JNC. Example 6.34. Write an ALP for 8085 to find the largest number among three numbers stored in memory locations staring at 2101 H. Store the result in memory location 2104H. Solution. Main Program: Label Mnemonics Operand Comments LXI H, 2101 H ; Get H-L pair with 2101 H. MOV A, M ; Move the first number in accumulator. INX H ; Increment the H-L pair. CMP M ; Compare the second number with first number. JNC NXT ; If the accumulator content is larger then jump to NXT. MOV A, M ; Else move [M H − L ] to accumulator. NXT INX H ; Increment the H-L pair. CMP M ; Compare the third number with the larger of first two numbers. JNC NXT1 ; If the accumulator content is larger then jump to NXT1. MOV A, M ; Else move [M H − L ] to accumulator. NXT1 INX H ; Increment the H-L pair. MOV M,

A

; Store the result in the required memory location. ; Stop processing.

HLT

Example 6.35. Write an ALP for 8085 to find the largest number among a series of N numbers stored in memory locations staring at 2101 H. The number N is stored in memory location 2100 H. Store the result in memory location 2201 H. Solution. Main Program: Label Mnemonics Operand Comments 181

LOOP

NXT

LXI H, MOV C,

2100 H M

INX H MOV A,

M

; Get H-L pair with 2100 H. ; Store the number N in C-register which will be used as the counter. ; Increment the H-L pair. ; Move the first number in accumulator. ; Decrement count. ; Increment the H-L pair. ; Compare the second number with first number. ; If the accumulator content is larger then jump to NXT. ; Else move [M H − L ] to accumulator. ; Decrement count. ; Jump to LOOP if not zero. ; Store the result in 2201 H. ; Stop processing.

DCR C INX H CMP M JNC

NXT

MOV A, DCR C JNZ STA HLT

M LOOP 2201 H

6.5

PROGAMS TO ARRANGE A GIVEN SERIES IN ASCENDING OR DESCENDING ORDER Example 6.36. Write an ALP for 8085 to arrange a series of N-numbers in descending order. The number N is stored in memory location 2100 H. The series is stored in memory location starting at 2101 H. The result is to be stored in memory locations starting at 2201 H. Solution. Main Program: Label Mnemonics Operand Comments LXI SP, XXXX H ; Initialize stack pointer. LXI D, 2201 H ; Get D-E pair with 2201 H. LXI H, 2100 H ; Get H-L pair with 2100 H. MOV B, M ; Store the count N in B-register. START LXI H, 2100 H ; Get H-L pair with 2100 H. MOV C, M ; Store the number N in C-register also. INX H ; Increment the H-L pair. MOV A, M ; Move the first number in accumulator. DCR C ; Decrement count. LOOP INX H ; Increment the H-L pair. CMP M ; Compare the second number with first number. JNC NXT ; If the accumulator content is larger then jump to NXT. MOV A, M ; Else move [M H − L ] to accumulator. NXT DCR C ; Decrement count. JNZ LOOP ; Jump to LOOP if not zero.

182

STAX D

CALL

INX D DCR B JNZ HLT Subroutine Program: Label Mnemonics SUBR LXI H, MOV C,

; Store the largest number in memory location addressed by D-E register pair. ; Call the subroutine SUBR to put 00 H to the memory location where the largest number was found. ; Increment D-E register pair. ; Decrement B. ; Jump to START if not zero. ; Stop processing.

SUBR

START

Operand 2100 H M

Comments ; Get H-L pair with 2100 H. ; Store the number N is C-register which will be used as the counter. AGAIN INX H ; Increment the H-L pair. CMP M ; Compare the number with the largest number obtained in the main program. JZ NXT ; If it is largest jump to NXT. DCR C ; Decrement count. JNZ AGAIN ; If counts not complete jump to AGAIN. MVI A, 00 H ; Store 00 H to the accumulator. MOV M, A ; Put 00 H to the location at which the largest number was found. RET ; Go back to main program. Example 6.37. Write an ALP for 8085 to arrange a series of N-numbers in ascending order. The number N is stored in memory location 2100 H. The series is stored in memory location starting at 2101 H. The result is to be stored in memory locations starting at 2201 H. Solution. Main Program: Label Mnemonics Operand Comments LXI SP, XXXX H ; Initialize stack pointer. LXI D, 2201 H ; Get D-E pair with 2201 H. LXI H, 2100 H ; Get H-L pair with 2100 H. MOV B, M ; Store the count N in B-register. START LXI H, 2100 H ; Get H-L pair with 2100 H. MOV C, M ; Store the number N in C-register also. INX H ; Increment the H-L pair. MOV A, M ; Move the first number in accumulator. DCR C ; Decrement count. LOOP INX H ; Increment the H-L pair.

183

CMP M

NXT

JC

NXT

MOV A, DCR C JNZ STAX D

M

CALL

INX D DCR B JNZ HLT Subroutine Program: Label Mnemonics SUBR LXI H, MOV C, AGAIN

; Compare the second number with first number. ; If the accumulator content is smaller then jump to NXT. ; Else move [M H − L ] to accumulator. ; Decrement count. ; Jump to LOOP if not zero. ; Store the largest number in memory location addressed by D-E register pair. ; Call the subroutine SUBR to put FF H to the memory location where the smallest number was found. ; Increment D-E register pair. ; Decrement B. ; Jump to START if not zero. ; Stop processing.

LOOP

SUBR

START

Operand 2100 H M

INX H CMP M

JZ DCR C JNZ

NXT AGAIN

MVI A, MOV M,

FF H A

Comments ; Get H-L pair with 2100 H. ; Store the number N is C-register which will be used as the counter. ; Increment the H-L pair. ; Compare the number with the smalest number obtained in the main program. ; If it is smallest jump to NXT. ; Decrement count. ; If counts not complete jump to AGAIN. ; Store FF H to the accumulator. ; Put FF H to the location at which the smallest number was found. ; Go back to main program.

RET PROGRAMS ON MULTIPLICATION There are two methods for multiplication of two numbers. 1. Repetitive Addition Method 2. Shift and Add Method Repetitive Addition Method In this method multiplicand is added by the multiplier times. For example, we wish to multiply 8 and 4 numbers. So add 08 to 00 for four times. i.e. 6.6

184

Shift and Add Method For example, we wish to multiply two decimal numbers 32 and 12 as:

In this example, first of all multiplicand 32 is multiplied by 2 and the result 64 is copied in the temporary register (or written on the scratch pad). Again 32 is multiplied by 1 and result 32 is shifted left by one digit to make it 32o. Now 64 and 320 are added and we get the answer 384. Similar method used in binary multiplication. In binary multiplication, when a multiplicand is multiplied by 1, we get the product equal to multiplicand. When a multiplicand is multiplied by 0, we the product zero. For example 08 and 04 are multiplied as:

The answer is 0020 H (3210). It may be noted that the answer is not in BCD. This method may further be illustrated using the following flow chart.

185

Fig. 6.1

186

Example 6.38. Write an ALP for 8085 to multiply any number (stored in memory location 2101 H) by 2 and store the result in 2102 H memory location. Solution. Program: Label Mnemonics Operand Comments LXI H, 2101 H ; Get the H-L pair with 2101 H. MOV A, M ; Move the number in accumulator. STC ; Set the carry flag. CMC ; Complement the carry ( it clear the carry. RAL ; Rotate accumulator with carry i.e. it multiplies the accumulator content by two. INX H ; Increment the H-L pair. MOV M, A ; Store the result in 2102 H memory location. HLT ; Stop processing. Example 6.39. Write an ALP for 8085 to multiply two numbers using repetitive addition method. The two numbers are in memory locations 2101 H and 2102 H. Store the result in 2103 H and 2104 H. Solution. Main Program: Label Mnemonics Operand Comments LXI H, 2101 H ; Get H-L pair with 2101 H. MOV B, M ; Get first number in B-register. INX H ; Increment H-L pair. MOV A, M ; Get the second number in accumulator. CMP B ; Compare the two numbers. JNC NXT ; If A < B then use A as counter. MVI D, 00 H ; Move 00 to D register. MOV E, B ; Move first number to E register. JMP NXT1 ; Jump to NXT1. NXT MVI D, 00 H ; If A>B, so B should be used as counter. MOV E, A ; Store accumulator content in Eregister. MOV A, B ; Store B-register content in accumulator. NXT1 LXI H, 0000 H ; Put 00 to H and L registers. ORA A ; ORing of A with A to find if A = 00 H. JZ END ; If zero jump to End. DAD D ; Add the contents of H-L pair with D-E pair and the result is in H-L pair.

187

END

DCR A JNZ SHLD HLT

; Decrement count. ; If not zero jump to LOOP. ; Store the result. ; Stop processing.

LOOP 2103 H

Example 6.40. Write an ALP for 8085 to multiply two numbers using shift and add method. The two numbers are in memory locations 2101 H and 2102 H. Store the result in 2103 H and 2104 H. Solution. Main Program: Label Mnemonics Operand Comments LXI H, 2101 H ; Get H-L pair with 2101 H. MOV E, M ; Get first number in E-register. MVI D, 00 H ; Extend to 16 bits. INX H ; Increment H-L pair. MOV A, M ; Get the multiplier in accumulator. LXI H, 0000 H ; Put 00 to H and L registers. MVI B, 08 H ; Get count = 08. MULT DAD H ; Multiplicand = 2 x Multiplicand.. RAL ; Rotate accumulator left to find if most significant bit is 1. JNC NXT ; If no carry jump to NXT. DAD D ; Get Product = product + multiplicand. NXT DCR B ; Decrement B. JNZ MULT ; If not zero jump to MULT. SHLD 2103 H ; Store the result in 2103 H and 2104 H . HLT ; Stop processing. 6.7

PROGRAM ON 8-BIT DIVISION To divide 16 bit dividend with 8 bit divisor, the divisor is subtracted from the 8 most significant bits of the dividend. If there is no borrow, the bit of the quotient is set to 1, otherwise 0. The dividend is then shifted left by one bit before each trial of subtraction. The dividend and quotient share a register pair. Due to shift of dividend one bit of the register falls vacant in each subtraction. The quotient is stored in vacant bit positions. It is illustrated by the flow chart shown in figure 6.2. If the dividend of the division is an 8-bit number, then it is extended to a 16-bit number by placing zeros in the MSBs positions.

188

Fig. 6.2 189

Example 6.41. Write an ALP for 8085 to divide a 16-bit number by an 8-bit number. The dividend bytes are stored in memory locations 2101 H and 2102 H. (LS byte in 2101 H and MS byte in 2102 H ). The divisor is stored in memory location 2103 H. The quotient is to be stored in the memory location 2104 H and the remainder is to be stored in the memory location 2105 H. Solution. Main Program: Label Mnemonics Operand Comments LHLD 2101 H ; Get 16-bit dividend in H-L pair. LDA 2103 H ; Get divisor in accumulator. MVI C, 08 H ; Get count 08 in C-register. MVI D, 00 H ; Quotient = 00. MOV B, A ; Keep the divisor in B-register also. LOOP DAD H ; Shift dividend left by one bit. MOV A, D ; Keep the quotient in accumulator. ADD A ; Shift quotient left by one bit. MOV D, A ; Store the quotient in D-register. SUB B ; Perform trial subtraction. JC NXT ; If carry then dividend = previous dividend. MOV H, A ; Put most significant bits of dividend in register H. INR D ; Increment quotient by 1. NXT DCR C ; Decrement C. JNZ LOOP ; If not zero jump to LOOP. MOV L. D ; Store the quotient in L-register. SHLD 2104 H ; Store the result in 2104 H and 2105 H . HLT ; Stop processing. 6.8 MISCELLANEOUS PROGRAMS Example 6.42. Write an ALP for 8085 to find the square of a given number stored in memory location 2101 H and the result is to be stored in memory location 2102 H. Use Look-up table starting at 2200 H. Solution. Main Program: Label Mnemonics Operand Comments LXI D, 2200 H ; Get D-E pair with 2200 H (Starting address of the look-up table). LDA 2101 H ; Get the number in accumulator. MOV L, A : Load the number to L-register. MVI H, 00 H ; Get 00 H to H-register. DAD D ; Get effective address in H-L register pair. MOV A, M ; Get the result in accumulator.

190

STA

2102 H

; Store the result in the required memory location. ; Stop processing.

HLT Look-up table: Location Data

2200 H 00 H 2201 H 01 H 2202 H 04 H 2203 H 09 H 2204 H 10 H 2205 H 19 H 2206 H 24 H 2207 H 31 H 2208 H 40 H 2209 H 51 H 220A H 64 H 220B H 79 H 220C H 90 H 220D H A9 H 220E H C4 H 220F H E1 H Example 6.43. Write an ALP for 8085 to find the square of a given number stored in memory location 2101 H and the result is to be stored in memory location 2102 H. Use the addition of successive odd integers. Solution. Main Program: Label Mnemonics Operand Comments LDA 2101 H ; Get the number in accumulator. MVI L, 00H : Load 00 H to L-register. ORA L ; Find if number is zero. JZ END ; If number is zero then no need to find the square and jump to END. MOV C, A ; Move the number to C-register. MOV A, L ; Move the content of L-reg to accumulator so that square is zero. MVI B, 01 H ; Move 01 to B-register (first odd number). LOOP ADD B ; Add next odd number. INR B ; Find next odd number to add INR B ; 02. DCR C ; Decrement C-register contents. JNZ LOOP ; Continue if not zero. END STA 2102 H ; Store the result in the memory location 2102 H.

191

HLT ; Stop processing. Example 6.44. Write an ALP for 8085 to find the square root of a given number (perfect positive square) stored in memory location 2101 H and the result is to be stored in memory location 2102 H. Use the subtraction of successive odd integers. Solution. Main Program: Label Mnemonics Operand Comments LDA 2101 H ; Get the number in accumulator. ORA A ; Find if number is zero. JZ END ; If number is zero then no need to find the square root and jump to END. MVI B, 01 H ; Move 01 to B-register (first odd number). MVI C, 01 H ; Initial value of square root as one. LOOP SUB B ; Subtract next odd number. JZ END ; If number is zero then jump to END. INR B ; Find next odd number to add INR B ; 02. INR C ; Decrement square root value by 1. JNC LOOP ; Continue if no carry. END MOV A, C ; Store the result in accumulator. STA 2102 H ; Store the result in the memory location 2102 H. HLT ; Stop processing. Example 6.45. Write an ALP for 8085 to find the Fibonacci series. Sixteen terms of this series are to be store in the memory locations starting at 2101 H. Let 00 H and 01 H data are stored in memory locations 2101 H and 2102 H respectively before the execution of the program. Solution. The terms of Fibonacci series are given as: 1, 1, 2, 3, 5, 8, 13, 21,. . . . . This sequence is defined by assuming first two terms have the same value 1, and each term afterwards is the sum of the previous two terms, that is, 1 + 1 = 2, 1 + 2 = 3, 2 + 3 = 5, 3 + 5 = 8, and so on. The required terms of the Main Program: Label Mnemonics MVI C,

LOOP

LXI H, MOV A, INX H ADD M

Operand 10 H

2100 H M

192

Comments ; Decimal number 16 (10 H) is stored in C-register which will be used as counter. ; Get H-L pair with 2100 H. ; Move first data to accumulator. ; Point to next data. ; Get next term of the series.

INX H

1. 2.

3.

4.

5. 6. 7.

8.

9.

10.

MOV M, DCX H

A

MOV A, INX H DCR C JNZ HLT

M

; Point to the next memory location for storing the next term. ; Store the next term. ; Get previous term of the Fibonacci series. ; Get this term in accumulator. ; Point to the next memory location. ; Decrement count. ; If not zero jump to LOOP. ; Stop processing.

LOOP

Data stored before the execution of the program. 2100 H 00 H 2101 H 01 H PROBLEMS Write an assembly language program of 8085 to fill the RAM area from 2500 H to 25FF H with a byte 33 H. Sixteen bytes of data are stored in memory locations 2001 H to 2010 H. Write an assembly language program of 8085 to transfer this block of data to 2006 H to 2015 H. (Hint: In this case data will be transferred in the reverse order otherwise some of the data will coincide.) Write a program (WAP) in assembly language of 8085 to compare two hexadecimal numbers, stored in 2001 H and 2002 H memory locations, for equality. If the numbers are equal, the number itself will be stored in 2003 H memory location, else 00 H will be stored in the memory location 2003 H. WAP in assembly language of 8085 to test 3rd bit (D3 bit) of a byte stored at 2000 H memory location. If the bit D3 is zero store 00 at 2101 H else store the same number at 2101 H. Write an assembly language program (ALP) of 8085 to find the logical AND and Logical OR of 26 H and 39 H. Store the result in 2500 H and 2501 H. Write an ALP of 8085 to load EE H to the memory locations starting at 2501 H. The length of data bytes is given in 2500 H memory location. Write an ALP for 8085 to add two 8-bit numbers stored in memory locations 2101 H and 2102 H. The result should be stored in 2103 H and the carry if any should be stored in 2104 H. Write an assembly language program for 8085 to add two 8 bit numbers stored in memory locations 2101 H and 2102 H. The answer is required in decimal form and it should be stored in 2103 H and the carry if any should be stored in 2104 H. Write an ALP for 8085 to add 833 and 776 decimal numbers. The result should be stored in 2101 H to 2103 H memory locations. The memory location 2103 H should store the carry bit if any. (Hint: First convert the decimal numbers 833 and 776 to hexadecimal numbers.) Write an ALP for 8085 to subtract an 8 bit number (stored in 2101 H memory location) from another 8 bit number (stored in 2102 H memory location). The

193

11. 12. 13. 14.

15. 16.

17.

answer should be stored in 2103 H and the borrow bit if any should be stored in 2104 H. Repeat the problem 10 to get the result in decimal form. Write an ALP for 8085 to find smaller of two numbers stored in 2301 H and 2302 H. Store the smaller number in memory location 2303 H. Write an ALP for 8085 to find the smallest of the three numbers stored in memory locations starting at 2301 H. Store he smallest number in 2304 H. Write an ALP for 8085 to find the smallest number among a series of 16 numbers stored in the memory locations starting at 2301 H. The number 16 (10 H) is stored in 2300 H. The smallest number should be should be stored in 2401 H. Write an ALP to find 13 terms of Fibonacci series. The terms of the series are to be stored in the memory locations starting at 2501 H. Write an ALP for 8085 to shift an 8-bit number left by two bits. The number is stored in memory location 2501 H and the result is to be stored in 2502 H memory location. (Hint: Keep the number in accumulator and use ADD A instruction twice.) Write an ALP for 8085 to shift a 16-bit number left by two bits. The number is stored in memory locations 2501 H and 2502 H. The result is to be stored in 2503 H and 2504 H memory locations.

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7 Interrupt Instructions of 8085 In the preceding chapters the architecture, instruction set and programming details of 8085 microprocessor were discussed. The microprocessor forms the parts of microcomputers. Many complicated and sophisticated operations can be performed by using the microprocessor based systems. These systems have the facilities to transfer the data from the microprocessor to the outside world or vice-versa. The transfer of data takes place through the data bus with the help of address and control buses. Thus special circuitry is needed to convert data from a wide range of input devices into suitable form for microprocessor buses. The circuitries used between the microprocessor and input/output devices are known as interfaces. This chapter deals how the external devices (peripherals) get connected to the microprocessor. In addition, different ways of data transfer from the microprocessor to the peripheral devices and vice-versa, and the restart instructions will also be discussed. 7.1 METHODS OF I/O OPERATIONS There are two ways for the transfer of data from microprocessor to I/O devices and vice-versa. 1. Memory Mapped I/O 2. I/O Mapped I/O or Isolated I/O 7.1.1 Memory Mapped I/O Memory Mapped I/O system is used in smaller system. In this system there is only one address space, some addresses are assigned to memories and some addresses to I/O devices i.e. the addresses to I/O devices are different from the addresses which have been assigned to memories. In other words the I/O devices and memory share the memory map, with some address reserved for the I/O devices and rest for the memory. This scheme is shown in figure 7.1. The microprocessor use R/W signals to determine the direction of data flow. The main advantage of this scheme is that it does not require additional decoding circuitry and the set of instructions may be used to fetch data either from the I/O devices or from the memory locations. Following instructions may be used for the data transfer in this scheme: MOV M, A

It moves the contents of accumulator to MH-L. If H-L pair contains the address of memory location, then the data will be transferred to memory location; if on the other hand H-L pair contains the address of the I/O devices, then the accumulator data will be transferred to I/O devices.

MOV A, M

STA address

LDA address

It moves the contents of MH-L to accumulator. If H-L pair contains the address of memory location, then the data will be transferred from memory location; similarly if H-L pair contains the address of the I/O devices, then the data from I/O devices will be transferred to accumulator. It stores the contents of accumulator to addressed location. If the address represents the address of memory location then the accumulator contents will be stored to memory location; if on the other hand address represents the address of the I/O devices, then the accumulator data will be transferred to I/O devices. It stores the addressed contents to the accumulator. If the address represents the address of memory location then the contents stored in memory location will be transferred to accumulator; if on the other hand address represents the address of the I/O devices, then the data from the I/O devices will be transferred to the accumulator.

Fig. 7.1 Many other instructions like LDAX, STAX and other arithmetic and logic instructions etc may also be used in this memory mapped I/O systems. 7.1.2 I/O Mapped I/O or Isolated I/O

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Larger systems use this technique for the data communication to I/O devices. Figure 7.2 shows this system used in 8085 microprocessor. In this technique the

Fig 7.2 microprocessor treats the memory and I/O devices separately, using different control lines for each of them. In 8085A the IO / M signal is used for this purpose. If this signal is low (0), it represents the memory. However, if this signal is high (1), it represents the I/O operations. RD and WR signals in association with IO / M signal help in performing I/O read/write operations or memory read/write operations. Table 7.1 shows the operations of these signals. Table 7.1 Operations Address RD WR IO / M 0 1 0 A15-A0 MEMR Memory Read 1 0 0 A15-A0 MEMW Memory Write 0 1 1 A7-A0 I/O Read IOR 1 0 1 A7-A0 I/O Write IOW

Figure 7.3 shows the generation of MEMR (Memory Read), MEMW (Memory Write), IOR (I/O Read) and IOW ( I/O Write) signals.

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In this scheme, special instructions are used to perform the I/O operations. The special instructions are: IN XX H (XX H is the Port address of 1 byte , which is in between 00 H to FF H) OUT XX H (XX H is the Port address of 1 byte , which is in between 00 H to FF H) The address XX H of the I/O port is duplicated on both the high and low order address bus and the signal IO / M ensures that the memory location corresponding to that address (XXXX H) does not respond.

Fig. 7.3 Comparison of Memory Mapped I/O and I/O Mapped I/O is given in table 7.2.

Memory Mapped I/O I/O Mapped I/O 1. Large Number of instructions like Only two instructions IN Port, OUT Port MOV A, M, MOV M, A, LDA, STA are used for the data transfer from etc are used for the data transfer. microprocessor to I/O devices and vice versa. 2. Data transfer is possible between any Data transfer is possible only between register of C.P.U. and I/O devices. Accumulator and I/O devices. 3. Arithmetic and logic operations can be Arithmetic and logic operations can not be performed with the data of I/O Ports performed in this scheme. using with the instructions like ORA M, XRA M, ANA M, ADD M, SUB M etc.

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4. Memory mapping of 64 K byte is shared 256 (FF H) I/O devices may be interfaced. between system memory and I/O ports. 5. 16-bit address lines are needed.

8-bit address lines are needed.

6. It takes different T-states depending on It takes 10 T-states for its execution. the instructions.

7.2 DATA TRANSFER SCHEMES In microprocessor based systems several input / output devices are connected and data transfer may take place between microprocessor and memory, microprocessor and I/O devices and memory & I/O devices. Not much of the problems arise for the data communication between microprocessor and memory as same technology is used in the manufacturing of memory and microprocessor. The speed of the memory is almost compatible with the speed of microprocessor. But for the data transfer between the microprocessor and I/O devices, the problems arise due to mismatch of the speed of the I/O devices and the speed of microprocessor or memory. To overcome the problem of speed mismatch between the microprocessor and I/O devices following data transfer schemes (fig. 7.4) may be considered. The data transfer schemes were categorized depending upon the capabilities of I/O devices for accepting serial or parallel data.

Fig. 7.4

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The 8085 microprocessor is a parallel device i.e. it transfers eight bits of data simultaneously over eight data lines (parallel I/O mode). However in many situations, the parallel I/O mode is either impractical or impossible. For example, parallel data communication over a long distance becomes very expensive. Similarly, parallel data communication is not possible with devices such as CRT terminal or Cassette tape etc. For these devices, therefore, serial I/O mode is used which transfer a single bit on a single line at a tine. For serial data transmission, 8-bit parallel word is converted to a stream of eight serial bit using parallel-to-serial conversion. Similarly, in serial reception of data, the microprocessor receives a stream of 8-bit one by one which are then converted to 8bit parallel word using serial-to-parallel conversion. The parallel data transfer will now be discussed in the following sub-sections. 7.2.1 Programmed I/O Data Transfer This method of data transfer is generally used in the simple microprocessor systems where speed is unimportant. This method uses instructions to get the data into or out of the microprocessor. The data transfer can be synchronous or asynchronous depending upon the type and the speed of the I/O devices. Synchronous type of data transfer can be used when the speed of the I/O devices matches with the speed of the microprocessor. The common clock pulse synchronizes the microprocessor and the I/O devices. In such data transfer scheme because of the matching of the speed, the microprocessor does not have to wait for the availability of the data; the microprocessor immediately sends data for the transfer as soon as the microprocessor issues a signal. The asynchronous data transfer method is used when the speed of the I/O devices is slower than the speed of the microprocessor. Because of the mismatch of the speed, the

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internal timing of the I/O device is independent from the microprocessor and thus two

Fig. 7.5 units are said to be asynchronous to each other. The asynchronous data transfer is normally implemented using ‘handshaking’ mode. In the handshaking mode some signals are exchanged between the I/O device and microprocessor before the data transfer takes place. The microprocessor has to check the status to the input/output device, if the device is ready for the data transfer. The microprocessor initiates the I/O device to get ready; the status of the I/O device is continuously checked by the microprocessor till the I/O device becomes ready, the microprocessor sends instructions to transfer the data. Flow chart for this mode of data transfer is shown in figure 7.5. Fig. 7.6 illustrates the asynchronous handshaking process to transfer the data from the microprocessor to I/O device. In this figure, the microprocessor sends a ready signal to I/O device. When the device is ready to accept the data, the I/O device sends an ‘ACK’ (Acknowledge) signal to microprocessor indicating that the I/O device has acknowledged the ‘Ready’ signal and is ready for the transfer of data.

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Fig. 7.6 Figure 7.7 shows the asynchronous handshaking process to transfer the data from the I/O device to microprocessor. In this case I/O device issues the ready signal to microprocessor indicating that I/O device is ready to send the data to microprocessor. In response to this signal, valid data signal is sent by the microprocessor to I/O device and then the valid data is put on the data bus for the transfer.

Fig. 7.7 7.2.2 Interrupt Driven I/O Data Transfer In the programmed I/O data transfer method discussed above, the microprocessor is busy all the time in checking for the availability of data from the slower I/O devices and also in checking if I/O device is ready for the data transfer. In other words in this data transfer scheme, some of the microprocessor time is wasted in waiting while an I/O device is getting ready. The interrupt driven I/O data transfer method is efficient as no microprocessor time is wasted in waiting for an I/O device to be ready. The I/O device informs the microprocessor for the data transfer whenever the I/O device is ready. This is achieved by interrupting the microprocessor. The interrupt is hardware facilities provided on the microprocessor. In the beginning the microprocessor initiates data transfer by requesting the I/O device ‘to get ready’ and then continue executing its original program rather wasting its time by checking the status of I/O device. Whenever the device is ready to accept or supply data, it informs the processor through a control signal known as 202

interrupt signal. In response to this interrupt signal, the microprocessor sends back an interrupt acknowledge signal to the I/O device indicating that it received the request (Fig. 7.8). It then suspends its job after executing the current instruction. It saves the contents

Fig. 7.8 of program counter and status to stack and jumps to the subroutine program. This subroutine program is called Interrupt Service Subroutine (ISS) program. The ISS saves the processor status into stack; and after executing the instruction for the data transfer, it restores the processor status and then returns to main program. The flow chart for this method of data transfer is shown in figure 7.9.

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Fig. 7.9 As already discussed, several input/output devices may be connected to microprocessor using Interrupt Driven Data Transfer Scheme. Following interrupt request configuration may arise while interfacing the I/O devices to microprocessor. 1. Single Interrupt system 2. Multi Interrupt System 1. Single Interrupt System When only one interrupt line is available with the microprocessor and several I/O devices are to be connected, then the method is known as Single Interrupt System. Figure 7.10(a) shows the way to connect several devices to one active low input interrupt terminal ( INTR ) of the microprocessor. However, to connect the several I/O devices to active high interrupt terminal ( INTR ) is shown in figure 7.10(b). In the active low interrupt line of the microprocessor the devices are connected to INTR terminal through different open collector NOT gates; when any of the devices is active it provides a low

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signal to INTR enabling the interrupt line. Similarly, in the active high interrupt line the I/O devices are connected through an OR gate. When any of the device is high the output of OR gate sends a high signal to interrupt line (INTR).

Fig. 7.10(a)

Fig. 7.10(b) When the interrupt line is active in either of the two methods discussed above, then the microprocessor will not know which device has sent the interrupt signal. Three techniques are commonly used to solve the problem for the microprocessor that is requesting the interrupt and resolving any simultaneous requests by two or more devices. These are: 1. Polling: The interrupt signal from each device can be used to set one bit of a register wired as an input port. When an interrupt occurs, the ISS polls this port to see who requested service. A priority is automatically established by the order of polling. This technique is very simple but has the negative of degrading response time. 2. Daisy Chain: This technique has been shown in figure 7.11. In this method each I/O device has an Interrupt Enable Input (IEI) and an Interrupt Enable Output (IEO). An interrupt request can be made only if IEI is high. A serial 205

connection like a chain of all the I/O devices is made. The highest priority I/O device is placed at the first position followed by the lower priority devices in sequence. If any device sends an interrupt signal i.e. low to the interrupt line, then the INTR line of the processor is enabled. The interrupt acknowledge signal (INTA) is enabled in response to low INTR line. In figure 7.11, device 2 is requesting an interrupt causing its IEO to be low. This in turn disables devices 3 and 4. It may be noted that device 1 is still able to request an interrupt because it has a higher priority. The interrupt acknowledge signal can be used to reset IEO of the interrupting device.

Fig. 7.11 3. Priority Interrupt Controller (PIC): In this method several I/O devices may be connected to a single interrupt line through programmable interrupt controller (IC 8259). Up to 8 input/output devices may be connected to the microprocessor. If more than 8 I/O devices to be connected, more PICs (programmable interrupt controllers) are used in cascade. The details of PIC will be discussed in a later chapter. 2. Multi Interrupt System When the microprocessor has several interrupt terminals and one I/O device is to be connected to each interrupt terminal, then it is known as multi interrupt system. In this scheme, the number of I/O devices to be connected to the interrupt lines should be equal to or less than the number of interrupt terminals. In this way one device is connected to each level of interrupt. So when a device interrupts the microprocessor, it immediately knows which device has interrupted. Such an interrupt scheme is known as vectored interrupt. 7.2.3 Direct Memory Access (DMA) Data Transfer In programmed I/O or interrupt driven I/O methods of data transfer between the I/O devices and external memory is via the accumulator. For bulk data transfer from I/O

206

devices to memory or vice-versa, these two methods discussed above are time consuming and quite uneconomical even though the speed of I/O devices matches with the speed of microprocessor; since the data is first transferred to accumulator and then to concerned device. The Direct Memory Access (DMA) data transfer method is used for bulk data transfer from I/O devices to microprocessor or vice-versa. In this method I/O devices are

Fig. 7.12 allowed to transfer the data directly to the external memory without being routed through accumulator. For this the microprocessor relinquishes the control over the data bus and address bus, so that these can be used for transfer of data between the devices. For the data transfer using DMA process, a request to the microprocessor by the I/O device is sent and on receipt of such request, the microprocessor relinquishes the address and data buses and informs the I/O devices of the situation by sending Acknowledge signal as shown in figures 7.12 and 7.13. The I/O device withdraws the request when the data transfer between the I/O device and external memory is complete.

Fig. 7.13

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It may be mentioned here that DMA transfer the data of the following types: • Memory to I/O device • I/O device to memory • Memory to memory • I/O device to I/O device For transferring the data through DMA, an interfacing chip known as DMA Controller is used with the microprocessor that helps to generate the addresses for the data to be transferred from the I/O devices (Fig. 7.14). The peripheral device sends the request signal (DMARQ) to the DMA controller and the DMA controller in turn passes it to the microprocessor (HOLD signal). On receipt of the DMA request the microprocessor sends an acknowledge signal (HLDA) to the DMA controller. On receipt of this signal (HLDA) the DMA controller sends a DMA acknowledge signal (DMACK) to the I/O device. The DMA controller then takes over the control of the buses of microprocessor and controls the data transfer between RAM and I/O device. When the data transfer is complete, DMA controller returns the control over the buses to the microprocessor by disabling the HOLD and DMACK signals.

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7.3 THE 8085 INTERRUPTS As already discussed, in Interrupt Driven I/O data transfer methods the microprocessor gets interrupted by the I/O device when it is ready to transfer the data. The microprocessor suspends its job after executing the current instruction. It saves the contents of program counter to stack and jumps to the subroutine program. This subroutine program is called Interrupt Service Subroutine (ISS) program. The ISS saves the processor status into stack; and after executing the instruction for the data transfer, it restores the processor status and then returns to main program. The ISS executes the relevant set of instructions stored at a predetermined memory block. The Intel 8085 microprocessor has five hardware interrupt inputs on its chip. Besides these, the microprocessor has eight interrupt instruction in the instruction set. The microprocessor responds to both the hardware and software interrupts. In the following sections the details of both software and hardware interrupts will be discussed. 7.4 SOFTWARE INTERRUPTS The 8085 microprocessor has eight software interrupts namely, RST 0, RST 1, RST 2, RST 3, RST 4, RST 5, RST 6 and RST 7. The syntax for these interrupt instructions is given by: RST n where n varies from 0 to 7. These instructions are single byte instructions. When an interrupt occurs, a CALL instruction to a predetermined location of the memory is executed. The effect of each restart instruction is shown in table 7. 4.

Instruction Effect RST 0 CALL 0000 H RST 1 CALL 0008 H RST 2 CALL 0010 H RST 3 CALL 0018 H RST 4 CALL 0020 H RST 5 CALL 0028 H RST 6 CALL 0030 H RST 7 CALL 0038 H

Table 7.4 Op Code Binary equivalent C7 1100 0111 CF 1100 1111 D7 1101 0111 DF 1101 1111 E7 1110 0111 EF 1110 1111 F7 1111 0111 FF 1111 1111

Vector Location 0000 H 0008 H 0010 H 0018 H 0020 H 0028 H 0030 H 0038 H

These RST instructions are like vectors because they point to specific locations in the memory. The starting address of each instruction is called a Vector Location. The vector location for RST 0 is 0000 H and for RST 1 is 0008 H and so on. The vector locations of each instruction are 8 bytes apart. Therefore 8 bytes of instructions can be stored beginning at any vector location. Figure 7.15 shows the hardware for the implementation of the software interrupt instruction. This circuit is for the implementation of an instruction RST0. In response to the interrupt request signal, the 8085 microprocessor sends the I NTA (interrupt acknowledge) signal, which is used to enable the buffer. The hex code C7 H of RST 0 will be placed on the data bus.

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Fig. 7.15 Figure 7.16 illustrates how software interrupt instructions are executed. Suppose in the main program RST2 instruction is given, and when this instruction is executed the contents of the program counter is pushed onto the stack. Then the program counter jumps to the address 0010 H. The subroutine located from 0010 H to 0017 H is executed, with the RET instruction as the last instruction of the subroutine program. So as the RET instruction is executed it returns to the main program. Similarly, if another restart instruction RST4 is encountered in the main program, then the contents of the program counter are again pushed onto the stack. The program jumps to the subroutine program whose starting address is given by 0020 H. After the execution of this subroutine program it returns to the main program as shown in figure 7.16.

211

Fig. 7.16 From the above discussion it is clear that the software interrupt instructions are basically special kind of CALL instructions; when any of these instructions is executed it branches to the predetermined address. Notice that all these instructions are of one byte (ref. table 7.4) while the standard CALL instruction is of three bytes. The vector addresses of these 8 software interrupts are 8 bytes apart. So 8 bytes of instructions can be stored in the subroutine program associated with each of these instructions. But generally, the subroutine programs may require more than 8 bytes. For this reason the complete subroutine program are usually not stored in the vector locations, rather the vector locations are used to specify the starting address of the longer subroutine program i.e. in the vector location of these instructions JMP XXXX H may be stored. The XXXX H represents the starting address of the longer subroutine program. The last instruction of the program will be RET, so that after completing the subroutine program it jumps to the main program as shown in figure 7.17.

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Fig. 7.17 The hardware solution to multi-interrupt problem is carried out by the circuit shown in figure 7.18. The multi-interrupt problem means the possibility of two requests arriving simultaneously. This circuit will accept eight interrupt request and work as per their priority and separate RST instruction for each request is generated. For the generation of all eight RST instructions, a 3-to-8 priority encoder (IC 74LS148) along with a tri-state octal buffer (IC 74LS244) is used as shown in figure 7.18. The 3-to-8 priority encoder generates a 3 bit binary code corresponding to active input. If two or more inputs are active simultaneously, the highest numbered input will be encoded. The three bits are inverted by the inverted buffer and then applied to an octal buffer (IC 74LS244). The op code corresponding to the input will be generated which is latched on to the data bus if INTA signal is active. The op codes for each RST instruction given in table 7.4 are reproduced below: Instruction Op Code Binary equivalent RST 0 C7 1100 0111 RST 1 CF 1100 1111 RST 2 D7 1101 0111 RST 3 DF 1101 1111 RST 4 E7 1110 0111 RST 5 EF 1110 1111 RST 6 F7 1111 0111 RST 7 FF 1111 1111 It may be noted from this op code table that D0 to D2 and D6 to D7 bits of the op codes are same for all the RST instructions (RST 0 to RST 7). The bits D3 to D5 are different and are in the sequence of 3 bit binary numbers for the RST 0 to RST 7. In general the code for RST instructions may be written as: 11CCC111

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where CCC is 000 for RST 0 001 for RST 1 010 for RST 2 011 for RST 3 100 for RST 4 101 for RST 5 110 for RST 6 111 for RST 7 This sequence permits to use the 3-to-8 priority encoder. It can be understood that a signal say INT 3 is low then A0 A1 A2 will be100 which will be inverted by the inverter buffer as 011 (I3 I4 I5). Since the other lines I0, I1, I2, I6, I7 are all high, the octal buffer will provide the op code DF H (op code for RST 3) on the 8085 data bus as soon as the interrupt acknowledge signal ( INTA ) is made low in response to the interrupt request signal. Similarly by activating other inputs of the priority encoder, the vector CALL instructions can be generated on the 8085 data bus.

Fig. 7.18

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7.5 HARDWARE INTERRUPTS In addition of software interrupts discussed above the 8085 has five hardware interrupts also. For this, five hardware input pins are provided in the microprocessor. The hardware interrupts are initiated by an external device, by placing an appropriate signal at the interrupt pin of the microprocessor. The five interrupts RST 5.5, RST 6.5, RST 7.5, TRAP and INTR are shown in table 7.5. Out of these interrupts RST 5.5, RST 6.5, RST 7.5 and TRAP are vector interrupts and INTR is the non-vectored interrupt. In vector interrupts the microprocessor automatically sends the specific address to program counter in response to an interrupt request signal. However, in non-vectored interrupt, the interrupt device has to give the address of the interrupt service subroutine. Table 7.5 Interrupt Priority Vector Location TRAP 1 0024 H RST 7.5 2 003C H RST 6.5 3 0034 H RST 5.5 4 002C H INTR 5 ----It may be noted from the table that TRAP has the highest priority, RST 7.5 next highest and so on. If two or more hardware interrupts are served at the same time then the microprocessor executes them in order of their priority level; i.e. TRAP is served first, then RST 7.5 and so on. When highest priority interrupt is executed, the lower priority interrupts remain pending rather they are known as pending interrupts. The RST 7.5, RST 6.5 and RST 5.5 are the maskable interrupts and TRAP is nonmaskable interrupt. The maskable means the prevention of any interrupt. Some times it may be required to prevent one or more interrupts when a certain task is being carried out by the microprocessor; for this the masking of these interrupts is done. The masking of any interrupt is carried out by an instruction known as SIM (Set Interrupt Mask). The SIM is one byte instruction. To find the status of the interrupts i.e. to know which interrupt is masked or which interrupt is pending, another instruction known as RIM (Read Interrupt Mask) is used. These two instructions RIM and SIM will be discussed in section 7.7. 7.6 INTERRUPT CONTROL CIRCUIT Figure 7.19 shows the interrupt control circuit with 8085 microprocessor. The TRAP is non-maskable interrupt i.e. it is neither be affected by any flag nor can be masked. It is used to handle very important functions. Since it is a highest priority interrupt, so it is used to take care of parity errors, power failure and other events that needs immediate attention. In the case of power failure, it may execute a routine to transfer the contents of the main memory to the back up memory (if any); and also for parity errors, the data may be corrected before carrying on. It is edge and level trigger which means the input has to go high and stays high. The rising edge and level triggered TRAP signal triggers the D flip-flop. The logic ‘1’ at the output of D flip-flop and logic ‘1’ of the TRAP input enable the AND gate to trigger the TRAP interrupt i.e. it calls the vector location 0024 H as shown in figure 7.19. Once the TRAP is recognized, further inputs at the TRAP will not be considered unless the interrupt is reset. The TRAP interrupt will be reset if the RESET signal is active (low) or internal TRAP

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Acknowledge signal is high. After the 8085 microprocessor recognizes a TRAP interrupt, it will send a high TRAP acknowledge signal which will reset the D flip-flop. RST 7.5 is a maskable interrupt which can be enabled or disabled by using SIM instruction. This is an edge triggered interrupt. When a leading edge signal appears at the RST 7.5 pin of 8085 microprocessor, D flip-flop 2 will be set (ref. figure 7.19). The output of this flip-flop is labeled as I 7.5 which is known as pending interrupt. This is one input of AND gate 2. The AND gate 2 will not be enabled until other two inputs of the gates are high. The RST flip-flop will be reset either by having a high R 7.5 bit or by having a high RST Acknowledge signal. The interrupt Acknowledge signal resets it for future RST 7.5 interrupt. RST 6.5 and RST 5.5 are also maskable interrupts which may be enabled or disabled using SIM instruction. Both are level triggered interrupts. When a high signal (constant voltage of +5 V) appears at RST 6.5 pin of the microprocessor, it will enable one pin of AND gate 3. Till RST 6.5 interrupt pin is high and other two pins of AND gate 3 are low, this interrupt is known as pending interrupt (I 6.5). Similarly, when a high signal appears on RST 5.5 pin of the microprocessor, it will enable one terminal of AND gate 4. This interrupt will be pending interrupt (I 5.5) till RST 5.5 pin is high and other two inputs of AND gate 4 are low. It may be noted from the figure 7.19 that one input each of the AND gates 2, 3 and 4 is connected to IE signal (called interrupt enable flag). The second pin of these gates will be enabled if IE signal is high. The IE signal may be made to high by enabling

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the EI (Enable Interrupt) signal, which may be enabled by a software instruction EI. This instruction will be discussed in the succeeding section. The mask bits M 7.5, M 6.5 and M 5.5 for the interrupts may be set using the SIM instruction. To mask an interrupt, the corresponding mask bit has to be set. So to enable a pending interrupt, the corresponding mask bit should be made low (by SIM instruction) and interrupt enable flag should made high (by EI instruction). All the maskable interrupts may be disabled by either sending a low signal to RESETIN terminal or a high signal to ‘Any Interrupt Acknowledge’ terminal. The DI signal may also disable all the maskable interrupts. The DI (Disable Interrupts) is a software instruction. All these hardware interrupts discussed above, once enabled will execute the corresponding hardware CALL instruction specified by their vector locations, as per their priority levels. INTR is a lowest priority, maskable and level triggered interrupt. It uses handshaking. A high signal to INTR pin of the microprocessor will cause the current instruction to complete and will put the contents of the program counter into stack. The microprocessor will then generate a low INTA (interrupt acknowledge) signal. This signal is then used to enable a tristate buffer for the execution of hardware CALL instruction. It will execute the service subroutine program corresponding to any of the 8 software interrupts (RST 0 through RST 7). 7.7 INTERRUPT INSTRUCTIONS Once the microprocessor recognizes any of the interrupts, it immediately disables all the interrupts except TRAP. This is done just to ensure that no further interrupts are recognized while the interrupt service subroutine (ISS) is being executed. Once the ISS is complete the program is required to enable the interrupts again. For this one byte instruction EI is introduced just before the RET instruction of ISS.

Fig. 7.20

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Some portion of the main program may, sometimes be executed without being enabled the interrupt signals. For this the interrupts are to be disabled. The interrupts may be disabled by one byte instruction DI (Disable Interrupts). Later the interrupts may be enabled as shown in figure 7.20. EI and DI Instructions The instruction EI stands for Enable Interrupt. When this instruction is executed, it produces a high EI signal (fig. 7.19), which sets the flip-flop 3 and produces a high signal to interrupt enable flag (IE). This way EI instruction enables all the interrupts except TRAP. The instruction DI stands for Disable Interrupts. When this instruction is executed, it produces a high DI bit of flip-flop 3 (fig. 7.19). This resets the flip-flop and results a low IE (interrupt enable flag) signal. The low IE signal disables all the interrupts except TRAP. SIM and RIM Instructions It is often required to selectively enable a few interrupts and disable others. The selectively enabling or disabling the interrupts can be done by an instruction SIM It stands for set interrupt masks. This instruction is used by loading the accumulator as shown in figure 7.21. The accumulator is loaded by MVI A, data (data bits are as per the requirements) instruction. The SIM instruction is then executed.

Fig. 7.21 The meaning of the different mask bits are given below: 219

The bits D0 to D2 are the mask bits (M 5.5 to M 7.5). A high to either of these bits represents that the particular interrupt is masked and a low, however, to either of these bits represents the enabling of that particular interrupt. The bit D3 is known as MSE (Mask Set Enable). When this bit is low, the mask bits D0 to D2 are ignored. A high to this bit indicates that the bits D0 to D2 are valid as described above. The bit D4 when high resets the flip-flop 2 (figure 7.19), in order to override RST 7.5 without servicing it. D5 is undefined bit. The bits D6 to D7 are used for the serial transfer of data through the SOD line. The working of these pins will be described later. Let us take an example to illustrate the function of SIM instruction. For example we have MVI A, 0C H SIM instructions in an assembly language program for 8085 microprocessor. When first instruction MVI A, 0C H is executed it will have the data (as shown in figure 7.22) for

Fig.7.22 the execution of SIM. The SIM instruction after its execution will enable MSE signal (as D3 bit is high). RST 7.5 interrupt is masked (bit D2 is 1) and RST 5.5 and RST 6.5 interrupts are unmasked (enabled) as bits D0 and D1 are both 0. It will prevent the RST 7.5 interrupt from arriving at the final output. The another interrupt instruction is RIM It stands for Read Interrupt Mask. This instruction will give the present status of the interrupt. This instruction loads the accumulator with 8 bit data whose details are given in figure 7.23. The meanings of the different bits for RIM are given below: The bits D0 to D2 represent the masking of RST 5.5, RST 6.5 and RST 7.5 interrupts. A high to either of these bits represents that the particular interrupt is enabled; and a low to either of these bits represents that the particular interrupt is disabled. The bit D3 is known as interrupt enable flag (IE). When this bit is low, all the interrupts except TRAP are disabled and a high to this bit mask the bits D0 to D2 are ignored. A high to this bit indicates that the bits D0 to D2 are valid as described above. The bits D4 to D6 represent the pending interrupts. A high to either of these bits represents that particular interrupt is pending; and a low to either of these bits represents that particular interrupt is not pending. The bit D7 is a serial input data and used for the serial input data through SID line. The working of this bit will be discussed later.

220

Fig. 7.23 Let us take an example to illustrate the function of RIM instruction. Suppose after the execution of RIM instruction, the accumulator contains 2A H as the data as shown in figure 7.24. The high to I 6.5, IE and M 6.5 bits indicate that RST 6.5 is a pending interrupt, the interrupt system is enabled and the RST 6.5 is currently masked.

Fig. 7.24 Example 7.1. Write an assembly language program for 8085 microprocessor to enable RST 5.5 interrupt and disable RST 6.5 and RST 7.5 interrupts. Solution. To enable RST 5.5, the bit D0 (M 5.5) for the accumulator should be 0 (unmask); and for disabling RST 6.5 and RST 7.5, the bits D1 and D2 (M 6.5 and M 7.5) should be masked (1). Also MSE should be 1 (enable). The program will, therefore, be as given below: D7 D6 D5 D4 D3 D2 D1 D0 SOD SOE XX R 7.5 MSE M 7.5 M 6.5 M 5.5 0 0 0 0 1 1 1 0 =0E H EI MVI A, 0E H SIM Example 7.2. Write an assembly language program for 8085 microprocessor to enable all the interrupts. Solution. The program for this case will be as given below. The bits D0 to D2 should be unmask and MSE should be enabled. 221

D7 SOD 0

D6 SOE 0

D5 XX 0

D4 R 7.5 0

D3 MSE 1

D2 M 7.5 0

D1 M 6.5 0

D0 M 5.5 0 =08 H

EI MVI A, 08 H SIM Example 7.3. Write an assembly language program for 8085 microprocessor to enable RST 5.5 and RST 6.5 interrupt and reset 7.5 interrupt. Solution. The program for this case will be as given below. The bits D0 and D1should be unmasked and MSE should be enabled. For resetting of RST 7.5, the bit D4 (R 7.5) should also be 1. D7 D6 D5 D4 D3 D2 D1 D0 SOD SOE XX R 7.5 MSE M 7.5 M 6.5 M 5.5 0 0 0 1 1 1 0 0 =1C H EI MVI A, 1C H SIM Example 7.4. Write an assembly language program for 8085 microprocessor to check if RST 5.5 is pending. If it is pending, enable it without affecting any other interrupt else return to main program.. Solution. The program for this problem is given below. The RIM instruction will check if RST 5.5 is a pending interrupt. For this bit pattern of the accumulator will be checked. If bit D4 is 1, the RST 5.5 is pending interrupt otherwise not. For RIM D7 D6 D5 D4 D3 D2 D1 D0 SID I 7.5 I 6.5 I 5.5 IE M 7.5 M 6.5 M 5.5 For SIM D7 D6 D5 D4 D3 D2 D1 D0 SOD SOE XX R 7.5 MSE M 7.5 M 6.5 M 5.5 Label Mnemonics Operand Comments RIM ; Read Interrupt mask MOV B, A ; Mask information is moved to Breg. ANI 10 H ; Check if RST 5.5 is pending. JNZ NXT ; Jump to NXT if it is pending interrupt. EI ; Enable interrupts. RET ; RST 5.5 is not pending return to main program. NXT MOV A, B ; Get bit pattern (RST 5.5 is pending). ANI 0E H ; Enable RST 5.5 by not masking D0 bit (For SIM). ORI 08 H ; Enable MSE for SIM.

222

SIM JMP

ISS

; Jump to service subroutine for RS T5.5.

7.8 SERIAL INPUT AND OUTPUT DATA TRANSFER As already discussed in the architecture of 8085, two pins (Pin Nos. 4 and 5) are provided for SOD (Serial Out Data) and SID (Serial In Data) lines. These lines are used for serial data transfer. The data transfer to or from the SID or SOD lines is possible using the Instructions RIM (Read Interrupt Mask) and SIM (Set Interrupt Mask).

Fig. 7.25 The data on the SID line (Pin 5 of 8085) is loaded into accumulator at bit D7 whenever a RIM instruction is executed. In other words a RIM instruction may be executed each time a new bit arrives at the SID input. For example, let a bit ‘1’ arrives at the SID input. RIM instruction is now executed. After the execution of RIM instruction D7 bit of the accumulator will be 1 as shown in figure 7.25. Further to input 8 bit data serially through SID line, RIM instruction is executed 8 times and each time D7 bit may be isolated and saved for the conversion of serial data into parallel data. The SIM instruction sends the D7 bit of the accumulator to the SOD line of 8085. For this transfer, D6 bit (SOE) of the accumulator must be high as shown in figure 7.26.

Fig. 7.26 Suppose we wish to send a ‘0’ bit to the SOD line, this can be done as: MVI A, 40 H SIM Similarly, to send a ‘1’ bit to the SOD line, we use 223

MVI A, C0 H SIM The rotate or other instructions may used to convert 8 bit parallel data to serial data stream at the SOD output. It may be noted from the above discussion that bit D7 is used for SID line and this bit has nothing to do with the interrupt system. Similarly, bits D6 and D7 are used for SOD line and these bits have nothing to do with the interrupt system. So no new instructions are to be used for the serial transfer of data, i.e. interrupt instructions RIM and SIM may be used for this purpose also. Example 7.5. Consider a switch is connected to SID line and an LED to SOD line of 8085. It is required to input the SID line via switch and output the switch status to the LED. In other words when the switch is ON or OFF the LED should glow or not glow. Write an assembly language program to accomplish this. Solution. Program to accomplish the required work of the problem is given as: Label START

Mnemonics RIM

Operand

Comments ; Read Interrupt mask, Bit D7 of A is SID. ORI 40 H ; Enable SOE for SIM. SIM ; Output to LED. JMP START ; Jump to START. Example 7.6. Write an assembly language program to generate a symmetrical square wave of known frequency at the SOD line of 8085 microprocessor. Solution. To generate a square wave of certain frequency, SOD line should remain high for certain time and then low for the same amount of time. This is done by using the program given below. The time for the delay should be as per the frequency of the wave to be generated. MAIN PROGRAM: Label Mnemonics Operand Comments START MVI A, C0 H ; Enable SOE and SOD (D6 and D7) and disables all interrupts for SIM. SIM ; Sends high signal to SOD line. CALL DELAY ; Delay is introduced for SOD to remains high for certain time. MVI A, 40 H ; SOD is made low; and SOE and all interrupts are disabled for SIM. SIM ; Sends low signal to SOD line. CALL DELAY ; Again delay is introduced for SOD to remain low for certain time. JUMP START ; Repeats the process. SUBROUTINE PROGRAM: Label Mnemonics Operand Comments DELAY LXI D, XXX H ; Loads DE register pair with a 16bit number. LOOP DCX D ; Decrements DE register pair by 1.

224

; Moves the contents of E register to accumulator. ORA D ; ORing of the contents of D and E registers are performed to set the zero flag. JNZ LOOP ; If result is not zero than jump to loop. RET ; Go back to main program. The 16-bit number XXX H loaded to DE register pair is as per the delay introduced in the program (discussed in chapter 4). Example 7.7. Write an assembly language program to input an 8 bit data serially through SID line of 8085 microprocessor. Convert it to 8 bit parallel data and store this data to 2500 H memory location. Solution. The program is given as: Label

LOOP

MOV A,

E

Mnemonics MVI B, MVI C, RIM ANI

Operand 00 H 08 H

ORA B RRC MOV B,

80 H

A

DCR C JNZ RLC STA

LOOP 2500 H

Comments ; Clears Register B. ; Preset counter to 8. ; Get the bit through SID line. ; Isolate the bit received through SID line. ; Convert to parallel word. ; Rotate right. ; Save the accumulator contents to B register. ; Decrement the contents of C register. ; Go to LOOP if not zero. ; Rotate left. ; Store the parallel data to 2500 H memory location.

HLT Example 7.8. An 8 bit data (say 32 H) is to be outputted serially through SOD line of 8085. An LED connected to SOD line, should glow or not glow each time a bit (1 or 0) is outputted through SOD line. A delay of 1 sec is to be introduced between each transfer of a bit. Write an assembly language program to implement this. Solution. The program to output 8 bit data serially through SOD line is given below, which is self explanatory. MAIN PROGRAM Label Mnemonics Operand Comments MVI A, 00 H ; Loads the data 32 H to accumulator. MVI C, 08 H ; Preset counter to 8. LOOP RRC ; Rotate LSB to MSB.

225

MOV B,

A

ANI ORI SIM MOV A,

80 H 40 H

CALL DCR C

DELAY

; Save the accumulator contents to B register. ; Isolate SOD bit. ; Enable SOE bit for SIM. ; Sends the bit through SOD line. ; Save the present contents to accumulator. ; Call the delay for 1 sec. ; Decrement the contents of C register. ; Go to LOOP if not zero.

B

JNZ LOOP HLT The delay subroutine program for 1 sec delay may be written as discussed in chapter 4. SUBROUTINE PROGRAM: Label Mnemonics Operand Comments DELAY LXI D, F424 H ; Loads DE register pair with a 16bit number F424 H. LOOP DCX D ; Decrements DE register pair by 1. MOV A, E ; Moves the contents of E register to accumulator. ORA D ; ORing of the contents of D and E registers are performed to set the zero flag. JNZ LOOP ; If result is not zero than jump to loop. RET ; Go back to main program.

Example 7.9. Write an assembly language program that is interrupted by applying a rising pulse at RST7.5 terminal manually. The program copies 256 bytes of data stored at memory locations starting at 3000 H to memory locations starting at 4000 H. The interrupt signal should, however, be able to introduce a delay of 1 sec. After the delay it should then move to main program. The main program for transferring the data is in a loop that repeats the same task again and again. Solution. Here is the program that implements the given task. MAIN PROGRAM Label Mnemonics EI MVI A,

LOOP

Operand 08 H

SIM LXI H,

3000 H

LXI D,

4000 H

Comments ; Enable interrupts ; Enable RST7.5, RST5.5.

RST6.5

and

; Load the H-L pair with the starting source address. ; Load the D-E pair with the starting address of destination address.

226

NXT

MVI B,

FF H

MOV A,

M

; load the B-reg. with the bytes of data. ; Load the accumulator with the contents stored in memory location addressed by H-L register pair. ; Store the accumulator contents to the destination address given by DE register pair. ; Increments the H-L pair for next number. ; Increments the D-E pair ; Decrement B. ; If not zero jump to NXT. ; Jump to start.

STAX D

INX H

INX D DCR B JNZ NXT JMP LOOP HLT When the interrupt signal is enabled, it calls its vector location 003C H. At the vector location say it is stored that JMP FFBD H i.e. monitor transfers the program to the memory location FFBD H. Now the user has to transfer from FFBD H to a memory location from where service subroutine for RST7.5 is written. The user transfers the program from FFBD H to 2000 H with the instructions JMP 2000 H. The location 2000 H indicates the starting address of interrupt service subroutine. The interrupt service subroutine is given as:

Interrupt Service Subroutine (at the starting address 2000 H ) Label Mnemonics Operand Comments PUSH PSW : Save accumulator and flag contents in stack. PUSH B ; Save the contents of B-C register pair in stack. PUSH D ; Save the contents of D-E register pair in stack. DELAY LXI D, F424 H ; Loads DE register pair with a 16bit number F424 H. LOOP DCX D ; Decrements DE register pair by 1. MOV A, E ; Moves the contents of E register to accumulator. ORA D ; ORing of the contents of D and E registers are performed to set the zero flag. JNZ LOOP ; If result is not zero than jump to loop. POP D ; Restore the contents of D-E register pair from the stack. POP B ; Restore the contents of B-C register pair from the stack.

227

POP PSW

; Restore the contents of Accumulator and flag contents form the stack. EI ; Enable interrupts RET ; Go back to main program. Program written in ISS is the program for delay of one second as already discussed.

1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13.

14.

15. 16. 17.

18. 19. 20. 21. 22.

PROBLEMS Discuss the memory Mapped I/O operation for the transfer of data from microprocessor to I/O devices and vice-versa. Discuss the I/O Mapped I/O operation for the data transfer from microprocessor to I/O devices and vice-versa. Give the comparison of memory mapped I/O and isolated I/O scheme fro the data transfer from microprocessor to I/O devices and vice-versa. Why the problems arise when the data is transferred from the microprocessor to I/O devices and vice-versa? Mention various data transfer scheme. Discuss programmed I/O data transfer scheme. Describe Interrupt driven I/O data transfer scheme. What do you mean by handshaking? How is it used in asynchronous data transfer between microprocessor and I/O devices? What is DMA? Using block diagram explain how the data is transferred by a DMA controller. Discuss DMA for 8085. What is an interrupt? How data is transferred between the microprocessor and I/O devices. What is the difference between software and hardware interrupts? Discuss software interrupts of 8085. How is the INTR interrupt used in 8085? Differentiate between (i) Memory mapped I/O and I/O mapped I/O data transfer schemes. (ii) Maskable and Non-maskable Interrupts (iii) Hardware and Software interrupts Explain briefly the following: (i) DMA data transfer scheme (ii) Interrupt driven data transfer scheme What are interrupt terminals available in 8085 microprocessor? How SIM and RIM instructions are used to set and read the interrupts. What are hardware interrupts? What is meant by Vectored interrupts? What are the functions of SID and SOD pins of 8085? How RIM and SIM instructions are used to input a bit through SID line and output a bit through SOD line. Explain RIM and SIM instructions. Discuss EI and DI instructions. Write down the procedure to mask the RST6.5 interrupt. Explain RST n interrupt circuit of 8085. Discuss the bit pattern for RIM instruction.

228

23. 24. 25. 26. 27. 28. 29.

30.

31.

Discuss the bit pattern for SIM instruction. Draw and explain the interrupt control circuit for 8085 microprocessor. Mention interrupt instructions of 8085. Discuss any two of them. How will you enable all the interrupts of 805? How will you enable RST5.5 and disable RST6.5 and RST7.5? Write an assembly program of 8085 to generate asymmetrical square wave at the SOD line of 8085. Write an assembly language program to input 256 bytes of data serially through SID line of 8085 microprocessor. Convert the 256 bytes of data received serially to parallel data and store the data to memory locations starting at 2500 H. Here are some instructions MVI A, 1D H SIM After SIM instruction is executed, which interrupts are masked. (Ans.: RST 5.5 and RST 7.5 are masked.) Here are some instructions MVI A, XX H SIM What should be the value of XX H in MVI instruction so that RST 5.5 and RST 6.5 are masked and all other don’t care bits should be set to zero. (Ans.: XX H = 0B H)

____________

229

8 Programmable Peripheral Interface (PPI) 8255A The various methods of data transfer from the microprocessor to output devices or vice-versa has already been discussed in the preceding chapter. Special interface circuits, known as peripheral interface circuits are to be used for this purpose. The interfacing devices may be classified into two categories namely general purpose peripherals and special purpose peripherals. Basically the I/O devices to be connected to microprocessors are known as peripherals, these are printers, floppy drives, CRT and Cassette recorder etc. The general purpose peripherals are: • Programmable Peripheral Interface (PPI) • Programmable Interval Timer • Programmable Interrupt Controller • Programmable DMA Controller • Programmable Communications Interface. The special purpose peripherals used for interfacing a microprocessor to a specific type of I/O device are: • Programmable Keyboard and Display Interface • Programmable Hard Disk Controller • Programmable Floppy Disk Controller The present chapter will confine to the discussion of Programmable Peripheral Interface (PPI) IC 8255 A and its application. 8.1 DETAILS OF PPI IC 8255A The input/output devices are generally interfaced to the microprocessor through the input/output port as shown in figure 8.1. The input/output port is either nonprogrammable or programmable. A non-programmable port can either be connected in input mode or output mode, i.e. if both input and output devices are to be connected to the microprocessor two separate non-programmable ports are to be used, one for input device and other for the output device. INTEL 8212 is an 8-bit non-programmable I/O port. Figures 8.2 (a) and (b) show the interfacing of 8212 in input and output mode respectively. However, a programmable I/O port can be programmed to act either as an input port or an output port. The INTEL 8255A is a programmable port device. It is most

versatile Programmable Peripheral Interface which may be connected to almost any

Fig. 8.1

(a)

(b)

Fig. 8.2 microprocessor. This IC is widely used and can be programmed to transfer the data to the input/output devices. It is a 40 pin dual in line IC package, whose pin configuration and block diagram are shown in figures 8.3 and 8.4 respectively.

231

Fig. 8.3 The IC 8255 A has three 8-bit ports: Port-A Port-B and Port-C The port-C can be used into two 4-bit ports represented as Port CUpper and Port CLower. Port-A (PA7-PA0) and Port-CUpper (PC7-PC4) together form Group A, whereas Port-B (PB7-PB0) and Port-CLower (PC3-PC0) form Group B as shown in figure 8.5. After deciding the configuration of 3 ports (which port is to be used as input port and which port is to be used as output port), a control word of the command has to be given to the microprocessor. An 8-bit control word is formed for this purpose which may be transferred to the control word register of 8255 through the accumulator. The control register has 6 control lines RD , WR , RESET, A1, A0 and CS whose functions are as given below:

232

Fig. 8.4 (1) RD (Read):

(2) WR (Write):

(3) RESET (Reset):

It is a read signal which is active low. When this signal goes low, it allows the microprocessor to read the data from the selected I/O ports of the 8255 PPI. It is the write signal which is also active low. When this signal goes low, the microprocessor writes (loads) the data into the selected I/O ports or the control register of 8255. This is a reset line which is active high. When a high signal appears on this line, it clears the control register and sets all the ports in the input mode.

233

(4) A0 and A1:

Fig. 8.5 These lines A0 and A1 are used to address the three ports and the control word as shown in table 8.1. If the CS (chip select) terminal of 8255 is low, the lines A0 and A1 decide the ports. The CPU can read or write into these registers by using RD and WR signals. Table 8.1 A1 A0 0 0 Port-A 0 1 Port-B 1 0 Port-C 1 1 Control word register

(5) CS (Chip Select): It is an active low chip select terminal. It is used to select 8255 by applying low signal to CS terminal. When a high signal appears on this line, the 8255 will not be selected, the data bus buffer that connects 8255 to the system data bus remains floated. The 6 bits AD2-AD7 of address data bus (low order address bus) of the microprocessor are decoded to provide CS ; the remaining two bits AD0-AD1 may be used for the selection of control register or any of the three ports as shown in figure 8.6. Since the six bits of address data bus are decoded for CS , so as many as 2 6 (= 64) PPI (8255) can be connected to any system. For the selection of any port of 8255 AD1 and AD0 bits of the address data bus are connected to A1 and A0 terminals of 8255. 234

Fig. 8.6 Figure 8.7 shows the chip-select logic for 8255. From this logic diagram it is clear that if AD7-AD2 are all 0s then it enables CS to select this chip. The port selection will depend on the bits AD1-AD0 as given in table 8.2.

Fig. 8.7 Table 8.2 AD7 AD6 0 0

CS AD5 AD4 AD3 0 0 0

AD2 0

AD1 AD0 0 0

HEX ADDRESS 00 H

PORT NAME Port-A

0

0

0

0

0

0

0

1

01 H

Port-B

0

0

0

0

0

0

1

0

02 H

Port-C

0

0

0

0

0

0

1

1

03 H

Control word Register Generally the microprocessor kits available with the laboratories have two 8255 connected with the system; 8255-I and 8255-II. Figure 8.8 shows the chip select logic for

235

the second 8255. If AD7-AD2 are chosen as per this diagram then the second 8255 (8255II) will be selected. The port selection will depend on the bits AD1-AD0 as given in table 8.3. The M/S Vinytics, New Delhi has adopted this logic in their microprocessor kits.

Fig. 8.8 Table 8.3 AD7 AD6 0 0

CS AD5 AD4 AD3 0 0 1

AD2 0

AD1 AD0 0 0

HEX ADDRESS 08 H

PORT NAME of 8255-II Port-A

0

0

0

0

1

0

0

1

09H

Port-B

0

0

0

0

1

0

1

0

0A H

Port-C

0

0

0

0

1

0

1

1

0B H

Control word Register

It may be mentioned here that if the instruction OUT 03 H is executed then it transfers the contents of accumulator to the control word register of 8255-I. Similarly, if the instruction OUT OB H is executed then the accumulator contents will be transferred to control word register of 8255-II. For the control word, accumulator is loaded with the contents that are necessary to use the ports of 8255 as input port or output port. The procedure for the generation of control word will be discussed in a later section of this chapter. Now if 8255-I is initialized to use Port A as input port and ports B and C as output ports, then the execution of IN 00 H instruction will transfer the data from port A

236

of 8255-I to the accumulator. The execution of OUT 01 H instruction will transfer the accumulator contents to the port B of 8255-I. Similarly, 8255-II may be initialized by giving the proper control word to the control word register by using the instruction OUT 0B H. The IN or OUT instruction having the port address as 08, 09 or 0A may be used for the data transfer through 8255-II. 8.2 OPERATIONAL MODES OF 8255A The operational modes of 8255 A PPI can be classified into two broad groups (fig. 8.9).

Fig. 8.9 1. I/O Mode The input/output mode can further be subdivided into three groups: • Mode 0 – Simple Input/output mode In this mode the 8 bit port A (PA0-PA7) can be configured as input or output port. The port B (PB0-PB7) can also be configured, in the similar fashion, as input or output operation. However there is flexibility for the port C. It can be divided into two 4 bit ports, the port CLower (PC0-PC3) and port CUpper (PC4-PC7). Each of them can be set independently for input or output operation. In this way there are four ports (port-A, port-B, CLower and port CUpper) and each of them can be set either as an input port or an output port. Here these ports are simple input or output ports i.e. these ports can work without handshaking. In this mode the outputs are latched whereas the inputs are not latched. The basic definition of this mode is shown in figure 8.10. • Mode 1 – Strobed Input/output or Handshake mode In this mode of operation handshaking is used for the input or output data transfer. As discussed earlier, there are two groups in 8255 PPI: Group A and Group B. Both these groups have one 8-bit port and one 4-bit port. Port-A and Port CUpper form group A whereas Port-B and Port CLower form group B. The 8-bit port of each group can be programmed for input or output operation with latched input and latched output facilities. The bits of Port C are used for handshaking. Figure 8.11 shows the basic definition of this mode. 237

Fig. 8.10

Fig. 8.11

238

•

Mode 2 – Bidirectional Mode In this mode Port A can be programmed to operate as a bidirectional port. When Port A is programmed in this mode of operation, Port B can be used either in Mode 0 or Mode 1. For mode 2 operation PC3 to PC7 bits are used for handshaking. In this mode too both inputs and outputs are latched. The basic definition of this mode is shown in figure 8.12.

Fig. 8.12 2. Bit Set/Reset Mode The modes of operation of 8255 PPI may be selected by the software. The details of these modes will be discussed in the following sections. 8.3 CONTROL WORD FORMAT FOR 8255A As discussed above, a port can be programmed to act as an input port or an output port. A control word is, therefore, to be formed for programming the ports of 8255A. The format for the control word is shown in figure 8.13. The control word, as per the requirement of the programmer, is written into the control word register of 8255A. No read operation of the control word is allowed. The description of the control bits is given below: Sets Port CLower as input or output port. Bit D0 To make Port CLower as input port this bit is set to 1. To make Port CLower as output port this bit is set to 0. Bit D1 Sets Port B as input or output port. To make Port B as input port this bit is set to 1. To make Port B as output port this bit is set to 0.

239

Bit D2 Bit D3 Bit D4 Bits D5 and D6

Bit D7

Fig. 8.13 This bit is for mode selection for the port B. If this bit is set to 0, the port B will operate in mode 0. If this bit is set to 1, the port B will operate in mode 1. Sets Port CUpper as input or output port. To make Port CUpper as input port this bit is set to 1. To make Port CUpper as output port this bit is set to 0. Sets Port A as input or output port. To make Port A as input port this bit is set to 1. To make Port A as output port this bit is set to 0. These two bits are used to determine the I/O mode of port A. These bits are defined for the various modes of port A as follows: D6 D5 Mode of port A 0 0 Mode 0 0 1 Mode 1 1 0 or 1 Mode 2 This bit specifies either I/O function or bit set/reset function (BSR mode). 240

If this bit is set to 1 then the 8255 will work in I/O mode. If this bit is set to 0 then the 8255 will work in BSR mode. There are 16 combinations of control words for various configurations of the ports of 8255 for Mode 0 operations. These control words are shown in table 8.4.

Control Word Bits D7 D6 D5 D4 D3 D2 D1

Table 8.4 Control Word D0

PORT A PORT CUpper

1

0

0

0

0

0

0

0

80 H

Output

Output Output

Output

1

0

0

0

0

0

0

1

81 H

Output

Output Output

Input

1

0

0

0

0

0

1

0

82 H

Output

Output Input

Output

1

0

0

0

0

0

1

1

83 H

Output

Output Input

Input

1

0

0

0

1

0

0

0

88 H

Output

Input

Output

Output

1

0

0

0

1

0

0

1

89 H

Output

Input

Output

Input

1

0

0

0

1

0

1

0

8A H

Output

Input

Input

Output

1

0

0

0

1

0

1

1

8B H

Output

Input

Input

Input

1

0

0

1

0

0

0

0

90 H

Input

Output Output

Output

1

0

0

1

0

0

0

1

91 H

Input

Output Output

Input

1

0

0

1

0

0

1

0

92 H

Input

Output Input

Output

1

0

0

1

0

0

1

1

93 H

Input

Output Input

Input

1

0

0

1

1

0

0

0

98 H

Input

Input

Output

Output

1

0

0

1

1

0

0

1

99 H

Input

Input

Output

Input

1

0

0

1

1

0

1

0

9A H

Input

Input

Input

Output

1

0

0

1

1

0

1

1

9B H

Input

Input

Input

Input

PORT B PORT CLower

8.4 PROGRAMMING IN MODE 0 As discussed earlier, the Ports A, B, and C can be configured as simple input or output ports by writing the appropriate control word in the control word register. In the control word D7 is set to 1 as 8255A is to be used in simple I/O mode, D6, D5 and D2 are 241

all set to 0 as all the ports are to be used in mode 0. The remaining bits D4, D3, D1 and D0 determine if the corresponding ports are to be used as input port or output port (1 for input port and 0 for output port). Since these are four bits to decide which ports are to be used as input ports and which ports are to be used as output ports, so for this purpose, there will be 16 possible combinations of control words listed in table 8.4. For example, the control word when the ports of 8255A PPI are to be used in mode 0 with Port A as input port, port B as output port, Port CUpper as output port and Port CLower as input port is given as:

Fig. 8.14 The control word 91 H is to be loaded to the control word register (CWR) of 8255A through the OUT instruction. Let the control word 91 H is to be loaded to control word register of 8255-I connected to the system (port address is 03 H discussed earlier). It may be done with the following instructions: MVI A, 91 H OUT 03 H Now with OUT or IN instructions, the data may be transferred to or from the output devices. The proper port address is to be given with these instructions. Example 8.1. Obtain the control word when the ports of 8255A are to be used in mode 0 with port-A as input port and port B and port C as output port. Solution. The control word for this case is given as:

Fig. 8.15 Example 8.2. Obtain the control word when the ports of 8255A are to be used in mode 0 with port-A as output port and port B as input port and port C as output port. Solution. The control word for this case is given as:

Fig. 8.16 Example 8.3. Make control word when the ports of 8255A are to be used in mode 0 with all the ports as output ports. Solution. The control word for this case is given as: 242

Fig. 8.17 Example 8.4. Write an assembly language program to generate a square ware of 1 KHz frequency using 8255A. The wave should be available at PA0 terminal of Port-A. Solution. The Program to perform the task given in the problem is shown below: MAIN PROGRAM: Label Mnemonics MVI A,

LOOP

Operand 80 H

OUT

03 H

MVI A, OUT CALL

00 H 00 H DELAY

MVI A, OUT CALL

01 H 00 H DELAY

JMP SUBROUTINE PROGRAM: Label Mnemonics DELAY LXI D,

LOOP Operand 003FH

Comments ; Initialize 8255-I to work all the ports as output ports. ; Write the control word (80 H) in the control word register of 8255-I. ; Load 00 H to accumulator. ; Send 00H (0V) to PA0. ; Jump to dealy subroutine to introduce a delay of 0.5 msec. ; Load 01H to accumulator. ; Send 01 H (5V) to PA0. ; Jump to dealy subroutine to introduce a delay of 0.5 msec. ; Jump to loop to repeat the process.

Comments ; Loads DE register pair with a 16bit number (6310). LOOP1 DCX D ; Decrements DE register pair by 1. MOV A, E ; Moves the contents of E register to accumulator. ORA D ; ORing of the contents of D and E registers are performed to set the zero flag. JNZ LOOP1 ; If result is not zero than jump to LOOP1. RET ; Go back to main program. The subroutine program introduces a delay of approximately 0.5 msec (discussed in section 4.3). The PA0 terminal will be low for 0.5 msec and high for 0.5 msec. The total time will be 1 msec and thus a signal of 1 KHz will be generated at PA0 of port-A. A CRO may be connected to this terminal to observe the wave. Example 8.5. Write an assembly language program to glow 8-LEDs sequentially with a delay of one second. The LEDs are connected to 8 bits of port-B of 8255-II attached with the system. Solution. The program to perform the task of the problem is given below:

243

MAIN PROGRAM: Label Mnemonics MVI A,

REPEAT

Operand 80 H

OUT

0B H

MVI A, OUT

01 H 09 H

CALL

DELAY

RLC JMP SUBROUTINE PROGRAM: Label Mnemonics DELAY PUSH PSW

REPEAT

Operand

Comments ; Initialize 8255-II to work all the ports as output ports. ; Write the control word in the control word register of 8255-II. ; Load 01 H to accumulator. ; Send 01H (5V) to PB0 for the glow of LED ; Jump to delay subroutine - to introduce a delay of 1 sec. ; Rotate the contents of accumulator left for sequential glow of LEDs. ; Jump to Repeat for the next LED to glow.

Comments ; Send the contents of Acc and flag register to stack. MVI C, 02 H ; Load C register with 02 H data. LOOP LXI D, F424 H ; Loads DE register pair with a 16bit number (6310). LOOP1 DCX D ; Decrements DE register pair by 1. MOV A, E ; Moves the contents of E register to accumulator. ORA D ; ORing of the contents of D and E registers are performed to set the zero flag. JNZ LOOP1 ; If result is not zero than jump to LOOP1. DCR C ; Decrement the contents of C register. JNZ LOOP ; If the result is not zero Jump to LOOP. POP PSW ; Acc and flag contents are popped from the stack. RET ; Go back to main program. The subroutine program given here is already discussed in section 4.3. In place of RLC in the main program RRC may be written, which will allow the LEDs to glow in the opposite sequence. Example 8.6. Write a program in assembly language of 8085, to switch on an a.c. bulb after a delay of 1 Min. A relay circuit may be connected to PA0 of 8255-I to switch on the bulb. Solution. The relay circuit may be connected to PA0 of 8255A as shown in figure 8.18. When PA0 is made high (through software), the transistor T1 goes into saturation and thus energizes the relay. The normally open (N/O) terminals of the relay get connected

244

together and the bulb may be switched on. To provide high (logic 1) to PA0, the program in assembly language of 8085 is written as:

Fig. 8.18 MAIN PROGRAM: Label Mnemonics MVI A,

Operand 80 H

OUT

03 H

MVI A, OUT

00 H 00 H

CALL

DELAY

MVI A, OUT

01 H 00 H

HLT SUBROUTINE PROGRAM: Label Mnemonics DELAY MVI C,

operand 78 H

LOOP

LXI D,

F424 H

LOOP1

DCX D MOV A,

E

Comments ; Load C register with 78 H (12010)data so that the delay of 0.5sec is run 120 times (60sec). ; Loads DE register pair with a 16bit number (6310). ; Decrements DE register pair by 1. ; Moves the contents of E register to accumulator. ; ORing of the contents of D and E registers are performed to set the zero flag. ; If result is not zero than jump to LOOP1.

ORA D

JNZ

Comments ; Initialize 8255-I to work all the ports as output ports. ; Write the control word in the control word register of 8255-I. ; Load 00 H to accumulator. ; Send 00H (0V) to PA0 for the bulb to remain OFF. ; Jump to delay subroutine - to introduce a delay of 1 Min. ; Load 01 to accumulator. ; Send 01 (5V) to PA0 for the bulb to ON.

LOOP1

245

DCR C

; Decrement the contents of C register. JNZ LOOP ; If the result is not zero Jump to LOOP. RET ; Go back to main program. Example 8.7. Eight switches are connected to 8 bits of 8255 A (assume that the switches are debouncer switches) and 8 LEDs are connected to the 8 bits of Port B of 8255 A. Write an assembly language program that whenever any of the switch is depressed the corresponding LED glows. For example, if the switch number 3 is switched on, the LED connected to bit 3 should glow; similarly for the other. Solution. The program to perform the task of the problem is given below: MAIN PROGRAM: Label Mnemonics Operand Comments MVI A, 99 H ; Initialize 8255-I to make port A and port C as input ports and port B as output port. OUT 03 H ; Write the control word in the control word register of 8255-I. REPEAT IN 00 H ; Send 01H (5V) to PB0 for the glow of LED OUT 01 H ; Output the input data to glow the LED corresponding to depressed switch. JMP REPEAT ; Jump to Repeat. 8.5 PROGRAMMING IN MODE 1 (STROBED INPUT/OUTPUT) As already discussed, in Mode 1 handshake (Strobes) signals are used for the data transfer between the microprocessor and I/O devices. The handshake signals are exchanged between the microprocessor and peripherals. Both group A and group B of 8255 can be made to operate in Mode 1. The two ports (Port A and Port B) can be configured either as input port or output port. Each port (Port A and Port B) uses three lines of port C as handshake signals (i.e. total 6 lines of port C are used for handshake signals). The remaining two lines of port C can be used for simple I/O operation. Bits PC0, PC1 and PC2 of port C are used as handshake signals for port B in input and output modes. Bits PC3, PC4 and PC5 of port C are used as handshake signals for port-A in input mode only. The remaining bits of port C (PC5 and PC6) are used as simple I/O operation as programmed by bit D3 of the control word. Bits PC3, PC6 and PC7 of port C are used as control (handshake) signals for port A in output mode. In this case bits PC4 and PC5 of port C are used as simple I/O operation as programmed by bit D3 of the control word. The remaining bits PC0, PC1 and PC2 of port C are used for handshake signals for port B. The combination of Mode 1 and Mode 0 operation is also possible. For example, when port A is programmed to operate in mode 1, the port B can be operated in mode 0. 8.5.1 Input Control Signals in Mode 1 Figure 8.19(a) shows the input configuration of both Port A and Port B to be used in mode 1. The control signals used for handshaking are also shown in this figure. Bits

246

PC3, PC4 and PC5 of port C are used for handshaking when port A is used as input port; and bits PC0, PC1 and PC2 are used for handshaking when port B is also used for input port. Bits PC6 and PC7 are used for simple input/output operation. The control word for using Port A and Port B as input ports in mode 1 is shown in figure 8.19(b). The functions of three control signals used for handshaking are given as: STB (Strobe Input) This is an active low signal generated by the peripheral device to indicate that it has transmitted a byte of data. In response to this signal, 8255 generates IBF (Input Buffer Full) and INTR (Interrupt Request) signals. IBF (Input Buffer Full) This is an acknowledge signal sent by 8255. A high to this signal indicates that the input latch has received the data byte. INTR (Interrupt Request) This is an output signal sent by 8255 which may be used to interrupt the microprocessor. This signal is generated when STB , IBF and INTE (Interrupt Enable) are all low (logic 0). At the falling edge of the RD signal, this is reset.

(a)

(b)

247

(c)

(d) Fig. 8.19 This is an internal flip-flop which is used to enable or disable the generation of INTR signal. The two flip-flops INTEA and INTEB are set/reset using the BSR mode. The bit PC4 enables or disables INTEA; and PC2 enables or disables INTEB. Figure 8.19(c) shows the status word (i.e. the status of the signals INTR, INTE and IBF signals etc.) which will be placed in the accumulator if the port C is read. As shown in figure 8.19(d), the peripheral first loads data into the input port A or B by making STB input low. This low STB signal is generated by the peripheral device to indicate that it has transmitted a byte of data. The 8255A generates IBF and INTR in response to the active low STB signal. 8.5.2 Output Control Signals in Mode 1 As already discussed Bits PC3, PC6 and PC7 of port C are used as control (handshake) signals for port A in output mode. In this case bits PC4 and PC5 of port C are used as simple I/O operation as programmed by bit D3 of the control word. The remaining bits PC0, PC1 and PC2 of port C are used for handshake signals for port B. Figure 8.20(a) shows the input configuration of both Port A and Port B to be used in mode 1. The control signals used for handshaking are also shown in this figure. Bits PC3, PC6 and PC7 of port C are used for handshaking when port A is used as output port; and bits PC0, PC1 and PC2 are used for handshaking when port B is also used for output port. Bits PC4 and PC5 are used for simple input/output operation. The control word for using Port A and Port B as input ports in mode 1 is shown in figure 8.20(b). The functions of three control signals used for handshaking are given as: OBF (Output Buffer Full) This is an active low signal; it activates when the microprocessor writes data into output latch of 8255. This

INTE (Interrupt Enable)

248

indicates to an output peripheral that a new data is ready to be read. It goes high again after the 8255 receives a ACK signal from peripheral. This is an input signal from a peripheral. It becomes active ACK (Acknowledge) (low) when peripheral receives the data from 8255 ports. INTR (Interrupt Request) This is an output signal which is set at the rising edge of the ACK signal. This signal can be used to interrupt the microprocessor. It requests for the next data byte for output. This signal is generated when OBF , ACK and INTE (Interrupt Enable) are all high (logic 1). At the falling edge of the WR signal this is reset. INTE (Interrupt Enable) This is an internal flip-flop to a port and required to be set to generate the INTR signal. The two flip-flops INTEA and INTEB are set/reset using the BSR mode. Figure 8.20(c) shows the status word (i.e. the status of the signals INTR, INTE and OBF signals etc.) which will be placed in the accumulator if the port C is read.

Figure 8.20(d) shows the timing diagram for strobed Output.

(a)

(b)

249

(c)

(d) Fig. 8.20 Example 8.8. Obtain the control word for the following configuration of the ports of 8255 A for mode 1 operation: Port A – as input port, Mode for Port A – mode 1 Port B – input port Mode for Port B – mode 1, The remaining pins of port CUpper are to be used output pins. Solution. The 8255 A is to be used in mode 1, and port A as input port so PC3, PC4 and PC5 pins of port C will be used as the handshake signals. For port B as input port the PC0, PC1 and PC2 pins of port C will be used as the handshake signals. The remaining pins of port CUpper will be used as simple input output mode. In the present example PC6 and PC7 are to be used as output pins. The control word for the same may be given as (fig. 8.21):

Fig. 8.21

250

Example 8.9. Obtain the control word for the following configuration of the ports of 8255 A for mode 1 operation: Port A – as output port, Mode for Port A – mode 1 Port B – output port, Mode for Port B – mode 1, The remaining pins PC4 and PC5 of port C are to be used input pins. Solution. The 8255 A is to used in mode 1, and port A as output port so PC3, PC6 and PC7 pins of port C will be used as the handshake signals. For port B as output port the PC0, PC1 and PC2 pins of port C will be used as the handshake signals. The remaining pins of port C will be used as simple input output mode. In the present example PC4 and PC5 are to be used as input pins. The control word for the same may be given as (fig. 8.22):

Fig. 8.22 Example 8.10. Obtain the control word for the following configuration of the ports of 8255 A: Port A – as input port, Mode for Port A – mode 1 Port B – input port, Mode for Port B – mode 0, Port CLower – output port The remaining pins PC6 and PC7 of port C are to be used input pins. Solution. The 8255 A is to used in mode 1 and mode 0, and port A as input port in mode 1 so PC3, PC6 and PC7 pins of port C will be used as the handshake signals. The port B is to be used as input port in mode 0. The Port CLower is used as output port and remaining bits of port C (PC6, PC1) as input pins. The control word for the same may be given as (fig. 8.23):

Fig. 8.23

251

8.6 PROGRAMMING IN MODE 2 (STROBED BIDRECTIONAL BUS I/O) In mode 2 operation of 8255A, port A can be used as bidirectional 8 bit I/O bus. The port B can operate in mode 0 or mode 1. When port A is programmed to operate in mode 2 (bidirectional I/O bus), the five bits of port C (PC3-PC7) are used as control (handshake) signals for port A. This is illustrated in figure 8.24. In this case port B can be programmed in mode 0 or mode 1. If port B is used in mode 0, the remaining bits of port C (PC0-PC2) are used as input or output. However, if port B is used in mode 1, PC0-PC2 bits are used as handshake signals for port B.

Fig. 8.24 The functions of five control signals used for handshaking of port A are given as: This is an active low signal generated by the peripheral STB (Strobe Input) device to indicate that it has transmitted a byte of data. In response to this signal, 8255 generates IBF (Input Buffer Full) and INTR (Interrupt Request) signals. IBF (Input Buffer Full) This is an acknowledge signal sent by 8255. A high to this signal indicates that the input latch has received the data byte. INTR (Interrupt Request) This is an output signal which is set at the rising edge of the ACK signal. This signal can be used to interrupt the microprocessor. It requests for the next data byte for output. This signal is generated when OBF , ACK and INTE (Interrupt Enable) are all high (logic 1). At the falling edge of the WR signal this is reset. INTE (Interrupt Enable) This is an internal flip-flop to a flip-flop to a port and required to be set to generate the INTR signal. The two flip-flops INTE1 and INTE2 are set/reset using the BSR mode.

252

OBF (Output Buffer Full) This is an active low signal; it activates when the microprocessor writes data into output latch of 8255. This indicates to an output peripheral that a new data is ready to be read. It goes high again after the 8255 receives a ACK signal from peripheral. If all the possible combinations are considered, then there will be four configurations of the 8255A in mode 2. These combinations with their corresponding control words are shown in figures 8.25 to 8.28. The status word in mode 2 is shown in figure 8.29, which will be placed in the accumulator if the port C is read.

Fig. 8.25

Fig. 8.26

253

Fig. 8.27

Fig. 8.28

Fig. 8.29 Example 8.11. Obtain the control word for the following configuration of the ports of 8255 A:

254

Port A – as bidirectional, Mode for Port A – mode 2 Port B – input port, Mode for Port B – mode 0, Port CLower – input port Solution. . It may be remembered that the 8255 A is used in mode 2 only for port A. When port A is used to operate in mode 2; port B can be used either in mode 0 or mode 1. The pins of port C (PC3 to PC7) are used for the control signals for port A. For port B to operate in mode 0, Port CLower can be used as input or output pins as per the D0 bit of the control word. On the other hand for the port B to operate in mode 1, PC0, PC1 and PC2 bits will be used for control signals. The control word for this case is given as (fig. 8.30):

Fig. 8.30 Example 8.12. Obtain the control word for the following configuration of the ports of 8255 A: Port A – as bidirectional, Mode for Port A – mode 2 Port B – input port, Mode for Port B – mode 1, Solution. The control word for this case is given as (fig. 8.31):

Fig. 8.31 8.7 BIT SET/RESET (BSR) MODE As discussed in the earlier sections of this chapter that 8255A PPI can be used in bit set/reset (BSR) mode. To use the PPI in BSR mode D7 bit of the control word should be set to zero. However, for other mode of operations this bit should be set to 1. In BSR mode eight bits of Port C can be set or reset by writing the control word in the control word register. If a control word with bit D7 as 0 is recognized as a BSR mode then it does not alter any previously transmitted control word with D7 as 1; thus I/O operations are not affected by a BSR control word. In this mode of operation individual bit of port C can be set or reset or in other words a BSR control word affects only one bit of port C. The control word format for this mode of operation is shown in figure 8.32.

255

Fig. 8.32 The bits of the control word are defined as: Bit D7 This bit should be zero, to use 8255A in bit set/reset mode. Bits D4-D6 These bits are don’t care bits, which may be kept 0s or 1s but generally kept 0. The bits D3, D2 and D1 are known as bit select pins. Table 8.5 Bits D1-D3 shows which bit of port C will be affected by the D3, D2 and D1 bits of bit select pins. Table 8.5 D3 D2 D1 Bit of port C 0 0 0 PC0 0 0 1 PC1 0 1 0 PC2 0 1 1 PC3 1 0 0 PC4 1 0 1 PC5 1 1 0 PC6 1 1 1 PC7 Bit D0

This is known as Set reset bit. To set a bit of port C, D0 bit of the control word should be 1; and to reset a bit of port C, D0 of the control word should be 0. For example to reset PC3 (bit 3 of port C), the control word format will be given as: D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 1 1 0 = 06 H Bit 3 (PC3) Similarly, to set PC3, the control word format is given as: D6 D5 D4 D3 D2 D1 D0 D7 0 0 0 0 0 1 1 1 = 07 H Bit 3 (PC3) Example 8.13. A relay circuit, to switch on or off an a.c. mains bulb, is connected to PC4 (4th bit of port C). The 8255A is connected microprocessor whose address for control 256

word is 03 H. Using BSR mode it is desired to switch on and off the bulb after a regular interval of time. W rite a program in assembly language of 8085, to implement the above. Solution. The relay circuit may be connected to PC4 of 8255A as shown in figure 8.33. To switch on and off the bulb regularly using BSR, the program in assembly language of 8085 is written as:

Fig. 8.33 The control word in BSR mode to reset PC4 bit is: D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 1 0 0 0

= 08 H

The control word in BSR mode to set PC4 bit is: D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 1 0 0 1 = 09 H MAIN PROGRAM: Label Mnemonics Operand Comments LXI SP, XXXX H ; Initialize stack pointer. START MVI A, 08 H ; Load byte in accumulator to reset PC4. OUT 03 H ; Reset PC4 (the bulb will be off). MVI A, 08 H ; Load 08 H to accumulator. OUT 03 H ; Reset PC4 (the bulb will be off). CALL DELAY ; Jump to delay subroutine - to introduce a regular delay of constant time. MVI A, 09 H ; Load 09 to accumulator to set PC4. OUT 03 H ; Set PC4 (the bulb will be on). CALL DELAY ; Jump to delay subroutine - to introduce a regular delay of constant time. JMP START ; Jump to repeat the process. SUBROUTINE PROGRAM: Label Mnemonics Operand Comments

257

DELAY

LXI D,

XXXX H

Mnemonics LXI SP, MVI A,

Operand XXXX H 80 H

OUT

03 H

MVI A, MVI B, INR A OUT CALL

00 H FF H

; Loads DE register pair with a 16bit number. LOOP DCX D ; Decrements DE register pair by 1. MOV A, E ; Moves the contents of E register to accumulator. ORA D ; ORing of the contents of D and E registers are performed to set the zero flag. JNZ LOOP ; If result is not zero than jump to LOOP1. RET ; Go back to main program. XXXX H may be taken any hexadecimal number for introducing any desired delay. Example 8.14. Write a program in assembly language of 8085 to send 01H, 02H, 03H . . . . . . FFH data to port A of 8255A PPI with a time delay of 1msec to each output. Solution. The program to implement the above is given as: Label

LOOP

DCR B JNZ HLT SUBROUTINE PROGRAM: Label Mnemonics DELAY PUSH PSW

00 H DELAY

LOOP

Operand

PUSH B

LOOP

LXI D,

XXXX H

DCX D MOV A,

E

ORA D

258

Comments ; Initialize stack pointer. ; Initialize 8255-I to work all the ports as output ports. ; Write the control word in the control word register of 8255-I. ; Load 00 H to accumulator. ; Load FF H to B-reg (last data). ; Increment acc. ; Send the number to port A. ; Jump to delay subroutine - to introduce a delay of 1 msec. ; Decrement B. ; If B is not zero jump to LOOP.

Comments ; Push the program status word to stack. ; Push the contents of B-C reg pair to stack. ; Loads DE register pair with a 16bit number to introduce a delay of 1msec. ; Decrements DE register pair by 1. ; Moves the contents of E register to accumulator. ; ORing of the contents of D and E registers are performed to set the zero flag.

; If result is not zero than jump to LOOP1. POP B ; Pop the contents from stack to B-C reg pair back. POP PSW ; Pop program status word from stack. RET ; Go back to main program. Example 8.15. Write a program in assembly language of 8085 that inputs 256 bytes of data from port B of 8255A PPI with a time delay of 1msec to each input and store these bytes of data at memory locations starting at 2500 H. Solution. The program to implement the above is given as: Label

LOOP

JNZ

LOOP

Mnemonics LXI SP, MVI A,

Operand XXXX H 82 H

OUT

03 H

LXI H,

2500 H

MVI C, IN MOV M,

FF H 01 H A

CALL

DELAY

Comments ; Initialize stack pointer. ; Initialize 8255-I to work port B as input port and ports A and C as as output ports. ; Write the control word in the control word register of 8255-I. ; Initialize H-L reg pair with first address of destination location. ; Load FF H to C reg. as pointer. ; Input from port B. ; Load the accumulator content to memory location. ; Jump to delay subroutine - to introduce a delay of 1 msec. ; Increment H-L pair. ; Decrement C. ; If C is not zero jump to LOOP.

INX H DCR C JNZ LOOP HLT SUBROUTINE PROGRAM: The delay subroutine program is the same as given in the previous example.

Example 8.16. Suppose 4096 bytes of data are stored in 2000 H to 2FFF H memory locations. Write a program in assembly language of 8085 that outputs these bytes of data to port A of 8255A PPI with a time delay of 1msec to each output. Solution. The program to implement the above is given as: Label

Mnemonics LXI SP, MVI A,

Operand XXXX H 80 H

OUT

03 H

LXI H,

19FF H

259

Comments ; Initialize stack pointer. ; Initialize 8255-I to work all the ports as output ports. ; Write the control word in the control word register of 8255-I. ; Initialize H-L reg pair as pointer.

LOOP

INX H MOV A, OUT CALL

M 00 H DELAY

; ; ; ;

CPI

2F H

;

Increment H-L reg. pair. Load the data to accumulator. Output the data to port A. Jump to delay subroutine - to introduce a delay of 1 msec. Compare accumulator contents to 2F H. If not zero jump to LOOP. Load L-reg data to accumulator. Compare with FF H. If not zero jump to LOOP.

JNZ LOOP ; MOV A, L ; CPI FF H ; JNZ LOOP ; HLT SUBROUTINE PROGRAM: The delay subroutine program is the same as given in example 8.14. Example 8.17. A peripheral device is sending serial data to D7 bit of port B of 8255A at an interval of 1msec. Write a program in assembly language of 8085 that converts 8 bit serial data stream to 8 bit parallel word, which is then sent to port A of 8255A. Solution. The program to implement the above is given as: Label

Mnemonics LXI SP, MVI A,

Operand XXXX H 82 H

OUT

03 H

MVI B, MVI C, IN ORA RAR MOV B, CALL

00 H 07 H 01 H B A DELAY

Comments ; Initialize stack pointer. ; Initialize 8255-I to work port B as input port and ports A and C as output ports. ; Write the control word in the control word register of 8255-I. ; Store 00 H in register B. ; Store 07 H in register C as counter. ; Inputs a byte through port B. ; ORing for taking 7th bit. ; Change the position. ; Store to B register. ; Jump to delay subroutine - to introduce a delay of 1 msec. ; Decrement C. ; If not zero jump to LOOP. ; Outputs the data to port A.

DCR C JNZ LOOP OUT 00 H HLT SUBROUTINE PROGRAM: The delay subroutine program is the same as given in example 8.14. Example 8.18. Suppose 256 bytes of data are stored in the memory locations 2000 H to 20FF H. Write a program in assembly language of 8085 that converts each of these bytes into serial data stream. The serial data stream is sent (bit by bit) through D0 bit of port A of 8255A at the rate of approximately 1000 Bits/sec. (i.e. 1msec time interval between two bits). Solution. The program to implement the above is given as:

260

Label

LOOP

AGAIN

Mnemonics LXI SP, MVI A,

Operand XXXX H 80 H

OUT

03 H

LXI H, INX H MOV A, MVI B, OUT

1FFF H M 00 H 00 H

CALL

DELAY

RAR DCR B JNZ MOV A,

AGAIN L

Comments ; Initialize stack pointer. ; Initialize 8255-I to work all the ports as output ports. ; Write the control word in the control word register of 8255-I. ; Initialize the H-L register pair. ; Increment the H-L register pair. ; Store the byte in accumulator. ; Store 00 H in register B. ; Outputs the bit through D0 bit of port A. ; Jump to delay subroutine - to introduce a delay of 1 msec. ; Rotate right for the next bit. ; Decrement B. ; If not zero jump to AGAIN. ; Move the contents of L reg. to accumulator. ; Compare with FF H ; If not equal jump to LOOP.

CPI FF H JNZ LOOP HLT SUBROUTINE PROGRAM: The delay subroutine program is the same as given in example 8.14. Example 8.19. Write a program in assembly language of 8085 that inputs a byte from port A of 8255A and determines if the decimal equivalent of the byte is even or odd. If byte is even, then send ASCII E (45 H) to port B and send ASCII O (4F H) to port B if the byte is odd. Solution. The program to implement the above is given as: Label

ODD

Mnemonics MVI A,

Operand 90 H

OUT

03 H

IN ANI

00 H 01 H

JNZ

ODD

MVI A, JMP MVI A,

45 H END 4F H

261

Comments ; Initialize 8255-I to work port A as input port and ports B and C as output ports. ; Write the control word in the control word register of 8255-I. ; Inputs the byte through port A. ; ANDed with 01 H to check D0 bit of the Byte. ; If not zero (odd byte) jump to ODD. ; Load accumulator for ASCII E. ; Jump to END. ; Load accumulator for ASCII O.

END

OUT

01 H

; Output ASCII E or ASCII O to port B.

HLT Example 8.20. Write a program in assembly language of 8085 that inputs a byte from port A of 8255A and determines if the decimal equivalent of the byte is even or odd. If byte is even, then send ASCII E (45 H) to D0 bit of port B in serial fashion; if odd send ASCII O (4F H) to D0 bit of port B in serial fashion. The time interval between two consecutive bits should be 1msec. Solution. The program to implement the above is given as: Label

Mnemonics MVI A,

Operand 90 H

OUT

03 H

IN ANI

00 H 01 H

JNZ

ODD

MVI A, JMP ODD MVI A, END MVI C, REPEAT OUT CALL

45 H END 4F H 08 H 01 H DELAY

Comments ; Initialize 8255-I to work port A as input port and ports B and C as output ports. ; Write the control word in the control word register of 8255-I. ; Inputs the byte through port A. ; ANDed with 01 H to check D0 bit of the Byte. ; If not zero (odd byte) jump to ODD. ; Load accumulator for ASCII E. ; Jump to END. ; Load accumulator for ASCII O. ; Store 08 H to C register. ; Output ASCII E or ASCII O to D0 bit of port B. ; Call Delay subroutine to introduce a time delay of 1msec. ; Rotate right. ; Decrement C. ; If not zero jump to REPEAT.

RAR DCR C JNZ REPEAT HLT SUBROUTINE PROGRAM: The delay subroutine program is the same as given in example 8.14.

1. 2. 3. 4.

PROBLEMS Using the functional block diagram of 8255A PPI, explain its detail. Mention various modes of operations of 8255A PPI; explain its working in simple I/O mode. Draw the schematic block diagram of 8255A and explain the function of each block. Mention various modes of operations of 8255A and explain it working in BSR mode. Explain also its control word format.

262

5.

6. 7. 8. 9. 10. 11.

12.

13.

14.

15.

15.

16.

Draw and explain the control word format of 8255A. What will be control word if 8255 is used in simple I/O mode with port A as input port, port B as output port and port CLower as input port and Port CUpper as output port? Discuss the mode 1 output configuration of 8255. Discuss also its control word, control signals, timing diagram and status word. Discuss the mode 1 Input configuration of 8255. Discuss also its control word, control signals, timing diagram and status word. Explain how 8255 can be used in mode 2. Give the format of the control word when port A is used to operate in mode 2 and port B is operated in mode 1. Give the format of the control word when port A is used to operate in mode 2 and port B is operated in mode 0. Port CLower is used as simple input or output. Write an assembly language program of 8085A to output the contents of B-register to port A of 8255 A PPI. Eight LEDs are connected to port B of 8255 A. write an assembly language program of 8085 to glow LEDs 0, 2, 4, 6 for 1 sec and then glow LEDs 1, 3, 5, 7 for the same time and repeat. Obtain the control word when the ports of 8255A are to be used in mode 0 with port A as input port, port B as output port, and port CLower as output port and port Cupper as input port. (Ans. 98 H) Make a control word when the ports of 8255 A are to be used in mode 0 with all the ports as input ports. (Ans. 9B H) Obtain the control word for the following configuration of the ports of 8255 A for Mode 0 operation: Port A and port B as output ports and port CLower as output port; and port Cupper as input port. (Ans. 88 H) Obtain the control word for the following configuration of the ports of 8255 A for mode 1 operation: Port A – as input port, Mode for Port A – mode 1 Port B – input port Mode for Port B – mode 1, The remaining pins of port CUpper are to be used input pins. (Ans. BE H or BF H) Obtain the control word for the following configuration of the ports of 8255 A for mode 1 operation: Port A – output port in mode 1, Port B – output port in mode 1, The remaining pins PC4 and PC5 of port C are to be used output pins. (Ans. A4 H or A5 H) Obtain the control word for the following configuration of the ports of 8255 A: Port A – as bidirectional, Mode for Port A – mode 2 Port B – input port,

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Mode for Port B – mode 0, Port CLower –output port. 17.

18. 19. 20.

(Ans. C2 H) Write an assembly language program of 8085A to generate square wave of 100 Hz frequency using 8255A PPI. The wave should be available at PB0 terminal of port B. Give the program of delay subroutine also. Generate square wave of 100 Hz using BSR mode of 8255A. The wave should be available at PC4 terminal (D4 bit of port C). Write a program in 8085 assembly language to blink an LED at a regular interval of time. Assume LED is connected to PA0 (D0 bit of port A of 8255A PPI). Write a program in 8085 assembly language to blink an LED at a regular interval of time using Bit Set/Reset (BSR) mode. Assume LED is connected to PC0 (D0 bit of port C of 8255A PPI).

_________

264

9 Programmable Interval Timer/Counter: 8253 In many industrial applications precise time delays are needed. In discrete systems the time delays are generated using electronic timer based on logic gates and circuits or mechanical timers. However, in microprocessor based systems the time delays can be generated using software. The generation of accurate time delays by software control is very commonly used method as discussed in the earlier chapters of this book. In this method the processor has to wait for some time to generate a time delay, as microprocessor becomes unnecessarily busy in looping. The programmable interval timer/counter chip 8253 solves this problem. It is one of the most supporting chips for 8085 microprocessor. It is used for teal time applications. It can generate accurate time delays and wave forms using the software control. This chip includes three identical 16bit pre-settable down counters that can operate independently, as each counter has a clock input, gate input and one output. The counters can count in binary or BCD. In this chapter a detailed discussion on this chip and its applications will be carried out. 9.1 INTEL PROGRAMMABLE INTERVAL TIMER 8253 Intel 8253 Programmable Interval Timer/Counter is an NMOS 24 pin plastic dual in line package (DIP). It operates at +5 volt d.c. source. It can generate accurate time delays and wave forms using the software control. This chip includes three identical 16bit pre-settable down counters that can operate independently; namely counter 0, counter 1 and counter 2. The counters can count in binary or BCD. Each counter has a clock input, gate input and one output. The gate input enables the counting process. The counting may be started by applying the gate signal. The 8253 works at maximum clock frequency of 2 MHz. There is another programmable interval time which is upgraded version of 8253. It has pin compatible and software compatible with 8253. The 8254 can operate with high clock frequency up to about 8 MHz. This chip 8254 is compatible to 8086, 8088 and other microprocessors. However, 8253 is compatible to 8085microprocessor. We shall discuss the details of the chip 8253. The 8253 can operate on the following six modes: Mode 0: Interrupt on Terminal Count Mode 1: Programmable one shot Mode 2: Rate Generator Mode 3: Square Wave Generator Mode 4: Software Triggered Mode Mode 5: Hardware Triggered Mode

The three counters of this chip can operate independently in any of the six modes. 9.2 BLOCK DIAGRAM OF 8253 Figures 9.1 and 9.2 show the pin diagram and functional block diagram of 8253. It has a data bus to be connected to the data bus of the microprocessor, a control word register, five control signals and three 16-bit presettable down counters namely: Counter 0 Counter 1 Counter 2. Control word Register: The control word register of 8253 is accessed when A0 and A1 terminals are at logic 1. It is used to write a command word which specifies the counter to be used, its mode, and either Read or Write operation,

Fig. 9.1 The description of pins of 8253 Programmable Interval Timer (PIT) is given as follows: Pin Nos. 1-8:

form the bidirectional data bus buffer (D7 to D0) to be connected to the control bus of the microprocessor.

Pin Nos. 9-11:

are provided for counter 0. Pin 9 is CLK 0 (Clock input terminal for counter 0), Pin 10 is OUT 0 (Output terminal for counter 0) and Pin 11 is GATE 0 (Gate input terminal for counter 0).

Pin No. 12:

is the ground terminal.

Pin Nos. 13-15

are allotted to counter 1. Pin 13 is OUT 1 (Output terminal for counter 1), Pin 14 is GATE 1 (Gate input terminal for counter 1) and pin 15 is CLK1 (Clock input for counter 1).

266

Fig. 9.2 Pin Nos. 16-18

are for counter 2. Pin 16 is GATE 2 (Gate input terminal for counter 2), Pin 17 is OUT 2 (Output terminal for counter 2) and pin 18 is CLK 2 (Clock input for counter 2).

Pin Nos. 19-20

are A0 and A1 terminals respectively. These terminals are used to select any one of the three counters and the control word register of 8253. These lines are to be connected to the address bus. The counters and control word register are selected as given in table 9.1.

267

Table 9.1

Pin No. 21 Pin No. 22

Pin No. 23

A0

A1

Selection for Counters

0 0 1 1

0 1 0 1

Counter 0 is selected. Counter 1 is selected. Counter 2 is selected. Counter 3 is selected.

is CS (Chip select terminal). It is an active low signal which allows enabling the device. is RD (Read terminal). It is also an active low signal. A low to this pin informs the 8253; that the CPU is ready to receive the data in the form of count value. is WR (Write terminal). When this pin is low, the microprocessor outputs data in the form of mode operation or loading of counter.

Pin No. 24 is + VCC (+5 V) terminal. 9.3 LOGICS FOR COUNTERS As already discussed, the 8253 has five control signals CS , RD , WR , A1 and A0 . The table 9.2 shows the action of different combination of these control signals. Table 9.2 A1 A0 Actions CS RD WR 0 1 0 0 0 Load counter 0 0 1 0 0 1 Load counter 1 0 1 0 1 0 Load counter 2 0 1 0 1 1 Write Mode Word 0 0 1 0 0 Read counter 0 0 0 1 0 1 Read counter 1 0 0 1 1 0 Read counter 2 0 0 1 1 1 No operation 3 state 0 1 1 X X No operation 3-state 1 X X X X Disable 3-state Note: X indicates undefined state, i.e. it does not matter whether it is 0 or 1. From this table it is clear that when CS = WR = 0 and RD = 1 with different combination of A1 and A0; any counter can be selected and loaded with 16 counter values. Once the gate is enabled by applying a high signal (logic 1) to it, counter values starts decrementing at each of the trailing edge of the clock pulse. However, if CS = RD = 0 and WR = 1 , the counter read operation is performed by the different counters.

268

The clock pulse is to be applied to CLK terminal of each counter of 8253. Though the clock signal of 3 MHz frequency is available with 8085 microprocessor but it can not directly be applied to the CLK terminal of each counter. Since 8253 can work with a maximum of 2 MHz clock frequency. So the clock frequency available with 8085 microprocessor is divided by a factor of 2 using an edge triggered D-flip flop (7474) as shown in figure 9.3. So 1.5 MHz clock frequency available at the output of D-flip flop can be used as CLK input of the counters of 8253. In some microprocessor kits available in the market for use in laboratories, the CLK terminals of the counters are left open so that any clock signal of desired frequency may be connected to these terminals.

Fig. 9.3 9.4 CONTROL WORD FORMAT OF 8253 As already discussed, any of the three counters can be programmed to operate in any of the 6 modes. The control word decides the selection of counter, its mode of operation, loading, sequence of the count and selection of binary or BCD counting. The format for the control word of 8253 is shown in figure 9.4. The control word is written into the control word register of 8253, as per the requirement.

269

Fig. 9.4 The description of the bits of control word format is given as: Bit D0 Sets the counting of the counter in binary or BCD. To make the counting in BCD this bit is set to 1, and to make the counting in binary this bit is set to 0. Bits D1-D3 These three bits are called mode selection bits M0, M1 and M2 respectively; and are used for mode selection of the counters which are given in table 9.3.

D3 (M2) 0 0 X X 1 1

Table 9.3 D2 D1 (M1) (M0) 0 0 0 1 1 0 1 1 0 0 0 1

270

Mode Mode 0 Mode 1 Mode 2 Mode 3 Mode 4 Mode 5

Bits D4-D5

Bits D6-D7

These bits are known as Read/Load bits (RL0 and RL1) and are used for read/load of the count values in the counters. Their operations are given in table 9.4. Table 9.4 D5 D4 Mode (RL1) (RL0) 0 0 Counter latching operation 0 1 Read/Load LSB only 1 0 Read /Load MSB only 1 1 Read/Load LSB first then MSB These bits (SC0 and SC1) are used for counter selection as given in table 9.5. Table 9.5 D7 (SC1) 0 0 1 1

D6 (SC0) 0 1 0 1

Select counter Counter 0 Counter 1 Counter 2 Illegal

9.5 INTERFACING AND PROGRAMMING OF 8253 Figure 9.5 shows interfacing of 8253 with the 8085 system bus. The eight data lines D0 to D7 of 8253 are connected to the data bus (Address data bus AD0-AD7) of the microprocessor. The chip is selected with CS terminal. So higher order address bus of the system is used for decoder circuit to select the chip. The A8 and A9 (two LSBs of the address bus) terminals of the microprocessor address bus are connected to A0 and A1 terminals of 8253 to select the proper counter. i.e.

271

Fig. 9.5 Figure 9.6 shows the chip-select logic for 8253. From this logic diagram it is clear that if A2 – A3, A5 – A7 are all at logic 0 and A3 is at logic 1, then it enables CS to select this chip. The counter selection will depend on the bits A1 – A0 as shown in table 9.6. Table 9. 6

CS

A0 0

HEX ADDRESS 10 H

Counter Selection Counter 0

A7 0

A6 0

A5 0

A4 1

A3 0

A2 0

A1 0

0

0

0

1

0

0

0

1

11 H

Counter 1

0

0

0

1

0

0

1

0

12 H

Counter 2

0

0

0

1

0

0

1

1

13 H

Control word Register

272

Fig. 9.6 As usual with IN and OUT instructions, the 8085 duplicates the port address on the address bus and data bus. The OUT instruction loads the control word in the control word register. As discussed above we may choose the hexadecimal address as 10 H for counter 0 11 H for counter 1 12 H for counter 2 13 H for control word register (CWR). The OUT 13 H will load the accumulator content to the control word register. The accumulator is therefore, to be loaded to the proper control word (as decided by the control word format) before OUT 13 H instruction. This way 8253 is initialized. To load the count values to the counter number initialized by the OUT 13 instruction, again OUT instruction is used having the proper control word. The IN instruction with proper port address will read the count values of the counter without stopping the counting. The 8253 can thus be programmed through write operations to generate various types of wave forms (which will be discussed in the succeeding section of this chapter) by loading the proper count values to any of the counters used in different modes. So for programming the 8253 we proceed as given in the flow chart (figure 9.7).

273

Fig. 9.7 For example to load counter 0 in mode 0 for the count value 1639 H in binary, we follow the program given below. The control word, to initialize the 8253 to load the given count value, first LS byte and then MS byte to the counter 0 in mode 0, is shown in figure 9.8.

Fig. 9.8 Program: Label

Mnemonics MVI A,

Operand 30 H

274

Comments ; Accumulator is loaded with the control word 30 H to Initialize 8253.

OUT

13 H

MVI A,

39 H

OUT

10 H

MVI A,

16 H

OUT

10 H

; Write the control word in the control word register of 8253. ; Load accumulator with LS byte (39) of the count value. ; First LS byte of the count value is loaded to the counter 0 of 8253. ; Load accumulator with MS byte (16) of the count value. ; MS byte of the count value is then loaded to the counter 0 of 8253.

......... ........ . ....... .. The count value of any counter of 8253 can also be read without stopping the counting. The bit pattern for the control word (figure 9.9) for latching operation is as follows:

Fig. 9.9 The control word for latching operation for counter 0 is 00 H as shown in figure 9.10.

Fig. 9.10 So the following program can be used to read the count value of counter 0 while counting is in program. Program: Label Mnemonics Operand Comments MVI A, 00 H ; Control word 00 H to read the count value of the counter 0 is loaded to accumulator. OUT 13 H ; The control word is loaded in the control word register of 8253.

275

IN

10 H

MOV B, IN

A 10 H

MOV C, MVI A,

A 16 H

; First read the LS byte of the count value. ; Load this value to B-register. ; Read the MS byte of the count value. ; Load this value in C-register. ; Load accumulator with MS byte of the count value.

......... ........ . Example 9.1. Initialize 8253 to load counter 1 in mode 0 with 8bit binary number 06 H. Solution. To initialize 8253 we have the control word as (Figure 9.11):

Fig. 9.11 The program for the same is written as: Program: Label Mnemonics Operand Comments MVI A, 50 H ; Accumulator is loaded with the control word 50 H to Initialize 8253. OUT 13 H ; Write the control word in the control word register of 8253. MVI A, 06 H ; Load accumulator with LS byte (06 H) only of the count value. OUT 11 H ; 06 H of the count value is loaded to the counter 1 of 8253. HLT ; Stop processing. Example 9.2. Initialize 8253 to load counter 0 in mode 1 with 1632 H BCD number. Solution. To initialize 8253 we have the control word as (Figure 9.12): The program for the same is written as: Program: Label Mnemonics Operand Comments MVI A, 33 H ; Accumulator is loaded with the control word 33 H to Initialize 8253. OUT 13 H ; Write the control word in the control word register of 8253.

276

MVI A,

32 H

OUT

10 H

MVI A,

16 H

OUT

10 H

; Load accumulator first with LS byte (32 H) of the count value 1632 H. ; 32 H of the count value is loaded to the counter 0 of 8253. ; Load accumulator then with MS byte (16 H) of the count value. ; 16 H of the count value is loaded to the counter 0 of 8253. ; Stop processing.

HLT

Fig. 9.12 Example 9.3. Initialize 8253 to load counter 2 in mode 1 with a count value 500010 in mode 0. Read the count value on the fly. Solution. To initialize 8253 we have the control word as (Figure 9.13):

Fig. 9.13 The control word for latching operation for counter 2 is 80 H as shown in figure 9.14.

Fig. 9.14 The program for the same is written as:

277

The hexadecimal equivalent of 500010 is 1388 H. Program: Label Mnemonics Operand Comments MVI A, B2 H ; Accumulator is loaded with the control word B2 H to Initialize 8253. OUT 13 H ; Write the control word in the control word register of 8253. MVI A, 88 H ; Load accumulator first with LS byte (88 H) of the count value 1632 H. OUT 12 H ; 88 H of the count value is loaded to the counter 2 of 8253. MVI A, 13 H ; Load accumulator then with MS byte (13 H) of the count value. OUT 12 H ; 16 H of the count value is loaded to the counter 2 of 8253. MVI D, 00 H ; Store 00 H to D-register. LOOP MVI A, 80 H ; Control word 80 H to read the count value of the counter 2 is loaded to accumulator. OUT 13 H ; The control word is loaded in the control word register of 8253. IN 12 H ; First read the LS byte of the count value. MOV B, A ; Load this value to B-register. IN 12 H ; Read the MS byte of the count value. ORA B ; Logical OR the LS and MS byte to set zero flag. JNZ LOOP ; If not zero jump to LOOP. HLT ; Stop processing. 9.6 PROGRAMMING OF 8253 IN MODE 0: INTERRUPT ON TERMINAL COUNT The MODE 0 is interrupt on terminal count. The output of the desired counter goes low on setting the mode, and goes high after the loaded counts are complete. It is used for the generation of precise time delay under software control. After the selection of desired counter, a suitable count value is loaded in the counter. The GATE terminal of the selected counter is made high from low. The down counting of the counter will be started. At the beginning of the counter, OUT terminal becomes low and remains low till the counting is stopped at the zero count value. On reaching the terminal count (i.e. count value becomes zero), the OUT terminal becomes high (logic 1) and remains high until and unless the selected counter is reloaded or a new count value is loaded or the mode of operation is changed. Further, if the count value is reloaded in count register while the counting is in progress, then after LS byte of the count value is written, the current counting is stopped; and after MS byte of the count value is written, the counting restarts

278

with the new count value. The timing diagram for mode 0 operation is shown in figure 9.15.

Fig. 9.15 If during the counting operation, GATE terminal is made low from high, the counting will be suspended. If the GATE terminal is again made high the counting may be resumed at the trailing edge of the clock pulse from the value where the counting was suspended. This is depicted in figure 9.16. The OUT terminal can be used to interrupt the microprocessor.

Fig. 9.16 9.7 PROGRAMMING OF 8253 IN MODE 1: PROGRAMMABLE ONE SHOT The MODE 1 is Programmable or retriggerable one shot. In this mode the OUT terminal of the counter goes low on the triggering of corresponding GATE input (low to high transition); which (OUT terminal) goes high on terminal count. The OUT terminal remains low for the count value loaded to the counter.

279

Initially control word and count values are loaded to the device register. A leading edge trigger signal is applied to the GATE input of the selected counter. At the next trailing edge of the clock the OUT terminal goes low. The down counting of the counter will now start and at the terminal count (i.e. count value becomes zero) the OUT terminal becomes high. In other word we can say that the OUT terminal remains low for the number of counts loaded in the selected counter. In this mode the counter thus be used as a triggered mono (or one) shot of desired width. This width can be varied by the count value loaded for the selected counter. It is illustrated in figure 9.17. The changing signal from high to low to GATE terminal does not affect the signal of OUT terminal, once the counting is started.

Fig. 9.17

Fig. 9.18 If the signal at the GATE terminal is changed from low to high when the counting is in progress, then the counting will be stopped for exactly one clock pulse. After one 280

clock pulse, the recounting will be started from the beginning i.e. the counter will be reloaded with the same count value and the down counting will be started again and the OUT terminal goes low for the same count value. Thus it is also called retriggerable one shot. This situation is shown in figure 9.18. A new count may be loaded to the counter while OUT terminal is low; it will not affect the width of the low OUT signal until the next trigger is applied to the GATE. 9.8 PROGRAMMING OF 8253 IN MODE 2: RATE GENERATOR Any counter of 8253 may be programmed to operate in mode 2 as rate generator which is also called as divide by N counter. Initially control word for mode 2 and count value N are loaded into the selected counter. The down counting of the counter will be started as soon as a high signal to the GATE terminal of the counter is applied. The OUT terminal stays high for (N-1) clock pulses and becomes low for exactly one clock pulse. After this OUT signal goes high again for (N-1) clock pulses and low for one pulse as the count value N is reloaded into the selected counter. This process continues as long as the GATE terminal is high. It, therefore, works as divide by N counter. Further, if the counter is working in this mode and a new count value is loaded, the present period will not be affected but the subsequent period will be as per the new count value. The timing diagram is shown in figure 9.19.

Fig. 9.19 The GATE input when low, will force the OUT terminal to high. When the GATE input goes high, the counter will start from the initial count. Thus the GATE can be used to synchronize the counter. 9.9 PROGRAMMING OF 8253 IN MODE 3: SQUARE WAVE GENERATOR When 8253 operate in mode 3, the counter acts as a square wave generator. This is similar to mode 2 with the difference that the OUT terminal of the selected counter in mode 3 remains high for half the count value and is low for the other half, if the count value is an even number. However, if the count value is an odd value, OUT terminal  N +1  N −1 remains high for   clock pulses and is low for   clock pulses.  2   2 

281

When control word for mode 3 and count value N are loaded into the selected counter, a high signal at the GATE terminal starts the down counting. The OUT terminal N N remains high for   counts and is low for the next   counts, if the count value N is 2 2  N +1 even; and for odd value of N, the OUT signal is high for   pulses and is low for  2   N −1   pulses as mentioned above. The count value is reloaded with full count and the  2  process is repeated till the GATE is high. Figure 9.20 shows the timing diagram for this mode of operation for both even and odd count value.

Fig. 9.20 The mode of operation of 8253 generates a square wave of period specified by the count value loaded to the counter. Any change in count value becomes effective, after the present counts are over. 9.10 PROGRAMMING OF 8253 IN MODE 4: SOFTWARE TRIGGERED STROBE In this mode of operation software controlled delayed negative pulse of one clock period duration is generated with and without synchronization. After the mode of operation of 8253 is set, the OUT terminal will be high, and the down counting of the counter will start as soon as the count value is loaded into the counter. On terminal count,

282

the OUT terminal goes low for one clock pulse then will go high again as shown in figure 9.21.

Fig.9.21 If the count register is reloaded between the output pulses, the present period will not be affected, but the subsequent period will reflect the new count value. The counter will be inhibited when the GATE terminal goes low. The GATE input can, therefore, be used for synchronization. The generation of strobe signal at OUT terminal is triggered by loading the count value in the counter that is why this mode is called software triggered mode. 9.11 PROGRAMMING OF 8253 IN MODE 5: HARDWARE TRIGGERED STROBE In this mode of operation a delayed negative pulse of one clock period duration is generated if a positive going trigger input is applied at the GATE terminal. After the mode of operation of 8253 is set, and the count value is loaded into the counter OUT

Fig. 9.22

283

terminal will be initially high. As the rising edge signal is applied to GATE terminal, the down counting of the counter will be started at the first trailing edge of the clock pulse after the rising edge of the GATE input. On terminal count, the OUT terminal goes low for one clock pulse then will go high again. The timing diagram for this mode of operation is shown in figure 9.22. As the low to high transition of the GATE terminal causes triggering hence this mode is referred to as hardware triggered strobe. If the GATE input is made low to high again the counter is reloaded by the same count value. The down counting of the count value once again started and on the terminal count the OUT terminal goes low for one clock period. Example 9.4. An LED is connected to PA0 of 8255 PPI. It should show ON and OFF regularly with a delay of one second. The delay should be introduced with 8253 used in mode 0 of counter 1. Assume the clock frequency applied to the counter of 8253 is 2 MHz. Solution. The control word to initialize 8253 is (Figure 9.23):

Fig. 9.23 The control word for latching operation for counter 2 is 80 H as shown in figure 9.24.

Fig. 9.24 Since the frequency of the clock signal connected to CLK terminal is 2 MHz, so the time of one clock pulse is 0.5 µ sec. If a count value of 5000010 (C350 H) is loaded to the counter, then a delay of 25 msec may be introduced when the counter is used in mode 0. Further to introduce a total time delay of 1 sec, then the subroutine program used for 25 msec may be executed 40 (28 H) times. Thus the program having the subroutine is given below: Main Program: Label Mnemonics Operand Comments LXI SP, XXXX H ; Initialize stack pointer. MVI A, 80 H ; Initialize 8255 PPI with all the ports as output ports. OUT 03 H ; The control word is loaded to the control word register of 8255. MVI B, 00 H ; Load the register B with 00 H.

284

LOOP1

LOOP

MOV A, OUT

B 00 H

MVI C,

28 H

CALL

DELAY

DCR C JNZ

LOOP

MOV A,

B

; 00 H is stored in accumulator. ; 00 is send to port A of 8255 so that LED is OFF. ; C register is used as counter so that the delay subroutine is executed 40 times. ; Delay program for the delay of 25 msec is called. ; Decrement C. ; If the content in C becomes zero, jump to LOOP. ; Move the content of B in accumulator. ; Complement the accumulator contents. ; Complemented content of accumulator is stored in B register. ; Jump to LOOP1 to change the state of LED.

CMA MOV B,

A

JMP

LOOP1

Subroutine Program: DELAY MVI A,

AGAIN

70 H

OUT

13 H

MVI A,

50 H

OUT

11 H

MVI A,

C3 H

OUT

11 H

MVI A,

40 H

OUT

13 H

IN

11 H

MOV D, IN

A 11 H

; Accumulator is loaded with the control word 70 H to Initialize counter 1 of 8253. ; Write the control word in the control word register of 8253. ; Load accumulator first with LS byte (50 H) of the count value C350 H. ; 50 H of the count value is loaded to the counter 1 of 8253. ; Load accumulator then with MS byte (C3 H) of the count value. ; C3 H of the count value is loaded to the counter 1 of 8253. ; Control word 40 H is loaded to accumulator to read on fly the count value of the counter 1. ; The control word is loaded in the control word register of 8253. ; First read the LS byte of the count value. ; Load this value to D-register. ; Read the MS byte of the count value. ; Logical OR the LS and MS byte to set zero flag.

ORA D

285

JNZ AGAIN ; If not zero jump to AGAIN. RET ; Return to main program. Example 9.5. The OUT terminal of counter 0 of 8253 is connected to RST 7.5, which is used to interrupt the microprocessor to clear the memory locations 2100 H to 21FF H. Use counter 0 of 8253 in mode 0 to enable RST 7.5 after a delay of 32.5 msec. Assume the clock frequency applied to the counter 0 of 8253 is 2 MHz. Solution. The control word to initialize counter 0 of 8253 is: D7 D6 D5 D4 D3 D2 D1 D0 0 0 1 1 0 0 0 0 = 30 H The accumulator contents for SIM to enable RST 7.5, RST 6.5 and RST 5.5 are given by: D7 D6 D5 D4 D3 D2 D1 D0 SOD SOE X R7.5 MSE M7.5 M6.5 M5.5 0 0 0 0 1 0 0 0 = 08 H The clock frequency used for counter 0 is 2 MHz, so time for one clock pulse is 0.5 µ sec . To introduce a delay of 32.5 msec, count value of 65000 (65000 x 0.5 µ sec = 32.5 msec) is to be loaded to the counter 0. The hexadecimal equivalent of 6500010 is FDE8 H. Main Program: Label Mnemonics Operand Comments EI ; Enable interrupts. MVI A, 08 H ; Bit pattern is loaded to accumulator to enable interrupts. SIM ; Enable interrupts. MVI A, 30 H ; Accumulator is loaded with the control word 30 H to Initialize counter 0 of 8253 in mode 0. OUT 13 H ; Write the control word in the control word register of 8253. MVI A, E8 H ; Load accumulator first with LS byte (E8 H) of the count value FDE8 H. OUT 10 H ; E8 H of the count value is loaded to the counter 0 of 8253. MVI A, FD H ; Load accumulator then with MS byte (FD H) of the count value. OUT 10 H ; FD H of the count value is loaded to the counter 0 of 8253. HERE JMP HERE ; Wait for interrupt. As soon as the counting is over, the OUT terminal of counter 0 becomes high which enables RST 7.5. The RST 7.5 interrupts the microprocessor and the program jumps to its vector location 003C H. At this vector location say it is stored JMP FFBD H. So the monitor will transfer the program from FFBD H. Now the user transfers the program from FFBD H to a memory location where service subroutine program for RST 7.5 is

286

stored. The program in service subroutine will be stored to clear the memory location 2100 H to 21FF H. Interrupt Service Subroutine: Label Mnemonics Operand Comments LXI H, 2100 H ; H-L pair is loaded with 2100 H, starting address of the memory location. MVI C, FF H ; Load FF H to C-register which is used as counter. XRA A ; Clear the accumulator. LOOP MOV M, A ; Clear the memory location. INX H ; Increment the H-L register pair. DCR C ; Decrement the content of Cregister for next byte. JNZ LOOP ; If the contents of C-register are not zero then jump to LOOP for next byte. EI ; Enable interrupts. RET ; Return. Example 9.6. A positive going pulse is applied (figure 9.25) to the GATE terminal of counter 1 of 8253 used in mode 0. The RST 7.5 is used to interrupt the microprocessor. Write a program to measure the width of this pulse which is of approximately 1 second. The clock signal applied to CLK terminal of counter 1 is 10 KHz. The width should be stored in terms of counts in memory locations 2100 H and 2101 H.

Fig. 9.25 Solution. The control word to initialize counter 1 of 8253 is: D7 0

D6 1

D5 1

D4 1

D3 0

D2 0 287

D1 0

D0 0

= 70 H

The accumulator contents for SIM to enable RST 7.5, RST 6.5 and RST 5.5 are given by: D7 D6 D5 D4 D3 D2 D1 D0 SOD SOE X R 7.5 MSE M 7.5 M 6.5 M 5.5 0 0 0 0 1 0 0 0 = 08 H The clock frequency used for counter 1 is 10 KMHz, so time for one clock pulse is 0.1 msec. This will also be measurement accuracy. Let us initialize the counter 1 with the count value corresponding to 2 second (1 sec for high and 1 sec for low). The count value will be 2000010, (as 20000x0.1 msec = 2 sec). The hexadecimal equivalent of 2000010 is 4E20 H. So 4E20 H will be loaded as count value in counter 1. To measure the pulse width the counter 1 is initialized in mode 0 in which signal (High pulse) on GATE terminal enables the counter; and RST 7. 5 is disabled. As soon as the pulse ends, the counting will be stopped and RST 7.5 will interrupt the microprocessor. The interrupt service subroutine will store the required number of counts in 2100 H and 2101 H memory locations. The required number of counts will be obtained by subtracting the remaining counts from the initial counts. The program is therefore given by: Main Program: Label Mnemonics Operand Comments EI ; Enable interrupts. MVI A, 08 H ; Bit pattern is loaded to accumulator to enable interrupts. SIM ; Enable interrupts. MVI A, 70 H ; Accumulator is loaded with the control word 70 H to Initialize counter 1 of 8253 in mode 0. OUT 13 H ; Write the control word in the control word register of 8253. MVI A, 20 H ; Load accumulator first with LS byte (20 H) of the count value 4E20 H. OUT 11 H ; 20 H of the count value is loaded to the counter 1 of 8253. MVI A, 4E H ; Load accumulator then with MS byte (4E H) of the count value. OUT 11 H ; 24E H of the count value is loaded to the counter 1 of 8253. HERE JMP HERE ; Wait for interrupt. Interrupt Service Subroutine: Label Mnemonics Operand Comments LXI H, 2100 H ; H-L pair is loaded with 2100 H, starting address of the memory location. IN 11 H ; Read the LS byte of the remaining counts.

288

MOV D, IN

A 11 H

MOV E,

A

MVI A,

20 H

; Store it to D-register. ; Read the MS byte of the remaining counts. ; Store it to E-register. So the remaining counts are stored in D-E register pair. ; Initial maximum LS byte (20 H) is stored in accumulator. ; Subtract the remaining LS byte from maximum LS byte. ; Store the counts in 2100 H. ; Increment the H-L register pair. ; Initial maximum MS byte is stored in accumulator. ; Subtract with borrow the remaining MS byte from the maximum MS byte. ; Store the counts in 2101 H.

SUB D MOV M, INX H MVI A,

A 4E H

SBB E

MOV M,

A

EI ; Enable interrupts. RET ; Return. Example 9.7. The D0 bit of 8255 A PPI is connected trigger input (GATE terminal) of counter 2 of 8253 as shown in figure 9.26. The counter 2 is used in mode 1. The count to be loaded to the counter 2 is 0A H. Write a program so that a wave, having low for 10 pulse duration and repeats, is generated. The CRO may be connected to the OUT terminal of counter 2 to see the wave shape.

Fig. 9.26 Solution. The control word to initialize counter 0 of 8253 is: D7 1

D6 0

D5 0

D4 1

D3 0

D2 0

289

D1 1

D0 0

= A2 H

Main Program: Label Mnemonics MVI A,

OUT

13 H

MVI A,

0A H

OUT

12 H

MVI A,

80 H

OUT

03 H

MVI A, OUT MVI A,

00 H 00 H 01

OUT CALL

00 H DELAY

JMP

LOOP

DELAY SUBROUTINE: Label Mnemonics DELAY MVI C, LOOP

Operand 30 H

DCR C JNZ RET

Operand FF H

LOOP

Comments ; Accumulator is loaded with the control word 30 H to Initialize counter 2 of 8253 in mode 1. ; Write the control word in the control word register of 8253. ; Load accumulator 0A H as count value. ; 0A H of the count value is loaded to the counter 2 of 8253. ; Initialize 8255 A PPI with all the ports to use as output ports. ; 80 H is loaded to control word register of 8255. ; Store 00 H to accumulator. ; PA0 is zero. ; Store 01 H to accumulator to make PA0 as 1. ; PA0 is 1. ; Call a delay program to introduce a small delay. ; Jump to LOOP for repetition.

Comments ; Store FF H to C register to use it as counter. ; Decrement counter. ; If count is not zero jump to LOOP. ; Return to main program.

Example 9.8. Write a program that will count the approximate number of T-states in a program given below. The SOD line of 8085 is connected to the GATE terminal of counter 1 of 8253. The 8253 is used in mode 1. The crystal of 8085 is of 2 MHZ which is directly connected to CLK input of the counter. The number of T-states used is to be stored in memory locations 2200 H and 2201 H. Label Mnemonics Operand LHLD 2101 H XCHG LHLD 2103 H MVI C, 00 H DAD D JNC NXT INR C NXT SHLD 2105 H

290

MOV A, C STA 2107 H HLT Solution. The control word to initialize counter 1 of 8253 in mode 1 is: D7 D6 D5 D4 D3 D2 D1 D0 0 1 1 1 0 0 1 0 = 72 H Let us load FFFF H as count value in counter 2. Main Program: Label Mnemonics Operand Comments MVI A, 72 H ; Accumulator is loaded with the control word 72 H to Initialize counter 1 of 8253 in mode 1. OUT 13 H ; Write the control word in the control word register of 8253. MVI A, FF H ; Load accumulator with low byte of count value. OUT 11 H ; Low byte FF H of the count value is loaded to the counter 1 of 8253. MVI A, FF H ; Load accumulator with High byte of count value. OUT 11 H ; High byte FF H of the count value is loaded to the counter 1 of 8253. CALL MODPRG ; Call the modified program. LXI H, 2200 H ; H-L pair is loaded with 2200 H, starting address of the memory location. IN 11 H ; Read the LS byte of the remaining counts. MOV D, A ; Store it to D-register. IN 11 H ; Read the MS byte of the remaining counts. MOV E, A ; Store it to E-register. So the remaining counts are stored in D-E register pair. MVI A, FF H ; Initial maximum LS byte (FF H) is stored in accumulator. SUB D ; Subtract the remaining LS byte from maximum LS byte. MOV M, A ; Store the counts in 2100 H. INX H ; Increment the H-L register pair. MVI A, FF H ; Initial maximum MS byte is stored in accumulator. SBB E ; Subtract with borrow the remaining MS byte from the maximum MS byte.

291

Label MODPRG

NXT

MOV M, EI HLT

A

; Store the counts in 2101 H. ; Enable interrupts. ; Stop processing.

Mnemonics MVI A,

Operand C0 H

SIM IN

11 H

Comments ; Control word for enabling SOE and SOD. ; Set SOD line. ; Read the LS byte of the remaining counts. ; Store it to D-register. ; ; ; ; Given program ; ; ; ; ; ; ; Control word for enabling SOE and resetting SOD. ; Reset SOD line. ; Return to main program.

MOV D, LHLD XCHG LHLD MVI C, DAD D JNC INR C SHLD MOV A, STA MVI A,

A 2101 H 2103 H 00 H NXT 2105 H C 2107 H 40 H

SIM RET

Example 9.9. Write a program to generate a negative pulse of approximately one T state after every 4 msec using 8253. Consider 1 MHz clock signal is applied to CLK terminal of the counter 1 of 8253. Solution. A negative pulse of approximately one T state is to be generated. This is the problem of rate generator, so 8253 may be used in mode 2. The counter 1 is to be initialized for this purpose. The GATE terminal is kept high. Further, clock frequency is 1 MHz so the time for one T state is 1 µsec. The number of counts to be loaded for 2 msec delay is given by: 4m sec = =400010. 1µ sec The number 4000 may be counted in BCD. The control word to initialize counter 1 of 8253 in mode 2 is:

D7 D6 D5 D4 D3 D2 0 1 1 1 0 1 The program is, therefore, written as: Main Program: Label Mnemonics Operand

292

D1 0

D0 1

Comments

= 7A H

MVI A,

7A H

; Accumulator is loaded with the control word 7A H to Initialize counter 1 of 8253 in mode 2. OUT 13 H ; Write the control word in the control word register of 8253. MVI A, 00 H ; Load accumulator with low byte of count value. OUT 11 H ; Low byte 00 H of the count value is loaded to the counter 1 of 8253. MVI A, 40 H ; Load accumulator with High byte of count value. OUT 11 H ; High byte 40 H of the count value is loaded to the counter 1 of 8253. HLT ; Stop processing. Example 9.10. Use counter 1 of 8253 in mode 2 as divide-by-8 counter. Solution. The GATE terminal is kept high. The control word to initialize counter 1 of 8253 in mode 2 is: D7 D6 D5 D4 D3 D2 0 1 0 1 0 1 The program is written as: Main Program: Label Mnemonics Operand MVI A, 54 H

OUT

13 H

MVI A,

08 H

OUT

11 H

HLT

D1 0

D0 0

= 54 H

Comments ; Accumulator is loaded with the control word 54 H to Initialize counter 1 of 8253 in mode 2. ; Write the control word in the control word register of 8253. ; Load accumulator with count value 08 H. ; Count Value is loaded to the counter 1 of 8253. ; Stop processing.

Example 9.11. Write a program to generate a square wave of 3 KHz frequency using counter 1 of 8253. Consider 1.5 MHz clock signal is applied to CLK terminal of the counter. Solution. To generate square wave, we use the 8253 in mode 3. The count value to be loaded to the counter 1 is given by: 1.5MHz =50010. = 3KHz So load 0500 H in BCD to counter 1. The GATE terminal of counter 1 kept high. The control word to initialize counter 1 of 8253 in mode 2 is: D7 0

D6 1

D5 1

D4 1

D3 0

D2 1

293

D1 1

D0 1

= 77 H

The program is, therefore, written as: Main Program: Label Mnemonics Operand MVI A, 77 H

OUT

13 H

MVI A,

00 H

OUT

11 H

MVI A,

50 H

OUT

11 H

HLT

1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14.

15. 16.

17.

Comments ; Accumulator is loaded with the control word 77 H to Initialize counter 1 of 8253 in mode 3. ; Write the control word in the control word register of 8253. ; Load accumulator with low byte of count value. ; Low byte 00 H of the count value is loaded to the counter 1 of 8253. ; Load accumulator with High byte of count value. ; High byte 50 H of the count value is loaded to the counter 1 of 8253. ; Stop processing.

PROBLEMS Draw the schematic block diagram of programmable interval timer (PIT) 8253 and explain its detail.. Discuss the control word format for 8253. Describe Read/Write control logic for 8253. Explain the different modes of 8253. Discuss different applications of 8253. Discuss how 8253 can be used as rate generator. Discuss how 8253 can be used as programmable mono shot. Discuss how 8253 can be used as square wave generator. Discuss how 8253 can be used as software triggered strobe. Discuss how 8253 can be used as hardware triggered strobe. Explain how to generate a delay using 8253 in mode 0. Explain how the count value loaded to a counter of 8253 is read while the counting is in progress. Write a program to generate a square wave of 1 KHz using 8253 in mode 3. The CLK terminal of the counter used is connected to a clock frequency of 1 MHz. Assume that CLK terminal of the counter 0 of 8253 is connected to clock frequency of 1 KHz. It is desired to generate square wave of 1 Hz frequency using this counter. Write a program to implement this. Set up 8253 as a square wave generator of 1 msec time period, if the input frequency connected to CLK terminal of counter 0 is 1 MHz. Write a program to generate a negative pulse of approximately one T-state after every 1 msec. Consider 2 MHz clock frequency is applied to the CLK terminal of the counter 1. Connect PC0 of 8255 A PPI to the trigger input (GATE 0) of counter 0 of 8253 used in mode 1. Load the count 0024 H (binary). Write a program to generate a wave having low for 36 pulses and repeat.

294

18.

19.

20 21.

22. 23.

The OUT terminal of counter 0 of 8253 is connected to RST 7.5. It is used to interrupt the microprocessor to set SOD line of 8085 after a delay of 40 msec. Use counter 0 in mode 0 and clock frequency connected to the CLK terminal is 2 MHz. An LED is connected to SOD line of 8085. The should glow ON/OFF regularly with an interval of 1 sec. The delay should be introduced by counter 2 of 8253 used in mode 0. Consider clock frequency connected to the CLK terminal is 10 KHz. Use 8253 in mode 3 as a square wave generator. Use count value as 10 H (BCD). The counter 1 is to be used for this purpose. Use counter 0 of 8253 to generate a square wave of 10 KHz and simultaneously counter 1 as divide by N counter. (N = 10 H BCD). The clock frequency connected to the CLK terminals is 1 MHz. Use counter 0 of 8253 as a simple counter in mode 0. After certain delay, read the counts when the counting is in progress. The 8253 is interfaced with 8085 microprocessor as shown in figure 9.27. Specify the port addresses of the three counters and control word register.

Fig. 9.27 (Ans.: 00 H for counter 0 01 H for counter 1 02 H for counter 2 03 H for CWR ) 24.

25.

Specify the control words for 8253: (i) to program counter 1 in mode 5 having a 16-bit count value in BCD; (ii) to count the counts on fly for the counter 1. (Ans.: (i) 7B H, (ii) 40 H) Write a program to use counter 0 of 8253 in mode 0 for BCD operation with an initial count value 364810, and counter 2 in mode 3 for binary operation with an initial count value FF H.

295

26.

(Ans.: Program MVI A, 31 H OUT 13 H MVI A, 96 H OUT 13 H MVI A, 48 H OUT 10 H MVI A, 36 H OUT 10 H MVI A, FF H OUT 12 H HLT) Explain what will be the meaning of the following program for 8253; (i) MVI A, 94 H OUT 13 H MVI A, FF H OUT 12 H HLT (ii)

27. 28.

MVI A, 38 H OUT 13 H MVI A, 04 H OUT 10 H MVI A, 02 H OUT 10 H HLT

(Ans.: (i) Counter 1 in mode 2 with binary counting, (ii) Counter 0 in mode 4 with binary counting) Write a program to use counter 0 of 8253 in mode 4 for BCD operation with an initial count value 022410. Write a program to use counter 1 of 8253 in mode 5 for Binary operation with an initial count value 2AB610. _________

296

10 Programmable Keyboard and Display Interface: 8279 The entering of program or data in the microprocessor base systems is most commonly done by a keyboard. Hence, keyboard is the most versatile input device. The keyboards with hexadecimal or ASCII characters are basically a combination of switches placed in a matrix with rows and columns. Similarly, display devices are to be connected to the system to output the data or the result, and the most common output device is seven segment display. The keyboard has to be constantly scanned to detect a key-press. The display, however, has to be supplied with the data to hold it ready. If the CPU is required to do all these operations itself, it will be heavily burdened and will have lesser time for other processes. These operations are, therefore, carried out by another device so that CPU is relieved from all these burdens. For this purpose, Intel 8279 keyboard/display interface is designed to directly connect to 8085 microprocessor. It performs both keyboard scan and output display operations repetitively and very short time of CPU is utilized for the data transfer between the device and CPU. This chapter will entirely deal with the details of this programmable keyboard and display device 8279. 10.1 INTEL PROGRAMMABLE KEYBOARD/DISPLAY INTERFACE 8279 Intel 8279 Programmable Key Board/Display Interface is available in the form of 40 pin IC in plastic dual in line package (DIP). It has been designed to interface the key board (an input device) and display device (an output device) with microprocessor. The 8279 constantly scans to detect a key press and transmit the information of characteristics of the key press to the CPU. It also displays or outputs the data received from CPU to the display devices. These two operations keyboard scan and display are performed repetitively and independently without utilizing the time of CPU except for relatively short time when the data is actually transferred to and from the burden of scanning the keyboard or refreshing the display repetitively. There are three input modes: Scanned keyboard mode Scanned Sensor matrix mode Strobed input mode. The keyboard can provide a scanned interface to 64 contact key matrix or array of sensors or a srobed interface keyboard. Key depressions can be 2 key lock out or N-key rollover. Keyboard entries are debounced and strobed in an 8-character FIFO (First In First Out) and set the interrupt lines. If more than 8 characters are entered, overrun

interrupt status is set. The display provides a scanned display interface for LED, incandescent or other popular display technologies. 10.2 BLOCK DIAGRAM OF 8279 The pin diagram, logic diagram and functional block diagram of this 40 pin 8279 IC are depicted in figures 10.1, 10.2 and 10.3 respectively.

Fig. 10.1 The description of pins of 8279 Programmable keyboard/display interface is given as follows: DB0-DB7:

These pins form the bidirectional 8-bit data bus. The commands are also transmitted on this data bus.

CLK:

It is a clock terminal to be connected to the external clock terminal of the system clock. It is used to generate internal timing. Maximum frequency to be used is 3 MHz.

CS :

This is a chip select terminal. A low signal to this terminal enables the chip for programming, reading the keyboard, etc.

298

A0:

It is buffer address pin. A low signal on this pin indicates data and a high on this pin indicates the command.

Fig. 10.2 IRQ:

It is an interrupt request output terminal. Interrupt request, becomes 1 when a key is pressed, data is available.

SL0-SL3 :

These four scan lines are used to scan the key switch or sensor matrix and the display digits. Scan line outputs scan both the keyboard and displays.

RL0-RL7:

These are 8 Return line inputs which are connected to the scan lines through the key or sensor switches. These lines have internal pull-ups to keep high until a switch closure pulls one of the lines low.

SHIFT:

This is an input terminal used in the scanned matrix keyboard modes. The SHIFT input status is stored along with the key position on key closure. SHIFT connects to shift key on keyboard. This is control and strobe line, connected to the control key on the keyboard. It is high until a switch closure pulls it low.

CNTL/STB:

299

Fig. 10.3

300

SHIFT:

RD : WR :

This is an input terminal used in the scanned matrix keyboard modes. The SHIFT input status is stored along with the key position on key closure. It is read input terminal and is connected to microprocessor's RD signal. It reads data/status registers. It is write input terminal and is connected to microprocessor’s write terminal.

OUT A0 –OUT A3 & These are two 4-bit ports. The display output is through two 4-bit OUT B0-OUT B3: ports (OUT A0 –OUT A3 and OUT B0-OUT B3). These two ports can be combined to form an 8 bit port. This is a blanking display terminal, used to blank the display BD : during the digit switching or by a display blanking command. 10.3 FUNCTIONAL DESCRIPTION OF 8279 The functional description of programmable keyboard and display interface 8279 will now be discussed with reference to figures 10.2 and 10.3. The 8279 has mainly been divided into four sections: Keyboard Section Scan Section Display Section Microprocessor Interface Section Keyboard Section The keyboard section includes Return buffer, keyboard debounce and control. Return buffers are to buffer the 8-input lines (RL0-RL7). In the keyboard mode, these lines are scanned, looking for the key closure in that row. If the debounce circuit detects a closed switch, it waits about 10 msec to check whether the switch remains closed. If it does, the address of the switch in the matrix in addition to other information is transferred to the FIFO. The block FIFO/Sensor RAM and Status contains dual function 8 x 8 RAM. It will act as a FIFO in keyboard or strobed input modes. Each new entry is written into successive RAM positions and each is then read in the order of entry. FIFO status keeps track of the number of characters in the FIFO and whether it is full or empty. Too many reads or writes will be recognized as an error. The status can be read by RD and CS low and A0 high. The status logic also provides an IRQ signal when the FIFO is not empty. Scan Section The scan section has a scan counter and four scan lines SL0-SL7 which are used o scan the key switch or sensor matrix and display digits. This counter can be operated in two ways: Encoded mode and Decoded mode. In the encoded mode, the counter provides a binary count which can be decoded to provide the scan lines for the keyboard or display. However, in case of decoded mode, the scan counter itself is a decoder providing 1 of 4 scan. Display Section This section contains the display address registers and display RAM. The display address registers hold the address of the word currently being written or read by the CPU and the two nibbles being displayed. The read/write addresses are programmed by CPU 301

command. They can also be set to auto increment after each read or write. The display RAM can be directly read by the CPU after the correct mode and address is set. These are two 4-bit ports. The display output is through two 4-bit ports (OUT A0-OUT A3 and OUT B0-OUT B3). These two ports can be combined to form an 8 bit port. The data from these lines are synchronized to the scan lines (SL0-SL3) for the multiplexed digit displays. The two ports may be blanked independently by the blanking display terminal BD . This section also includes 16 x 8 display RAM and the processor can read from or write into any of these registers. Microprocessor Interface Section The microprocessor interface sections contains 8-bit bidirectional data lines (DB0DB7), one interrupt request line (IRQ), one address buffer line A0, and five lines ( RD , WR , CS , RESET, CLK) for interfacing. When a high signal appears on A0 terminal, the command or status registers inside the 8279 can be accessed i.e. it works as command word or status. A low, however, on this line indicates that the data register, e.g. display RAM or the FIFO/Sensor RAM can be accessed. The interrupt request line IRQ becomes high whenever data entries are stored in the FIFO. This signal is used to interrupt the microprocessor to indicate the availability of the data. The data and commands are communicated between the microprocessor and the 8279 through the data bus (DB0-DB7). The RESET pin resets the 8279, when a high signal appears on this pin. The two signals RD and WR enable the data bus to either send data to external bus or receive it from the external bus. 10.4 KEYBOARD SCAN As already discussed, the 8279 provides 4 scan lines (SL0-SL3) and 8 return lines (RL0-RL7). The scan lines can be operated either in encoded mode or in decoded mode. Encoded Mode: In this encoded mode, four scan lines (SL0-SL3) can be used to generate 16 lines with the help of external decoder. Usually 3 to 8 line decoder is used with the scan lines. The most significant scan line SL3 is not recommended to use in keyboard decoder. So with three scan lines (SL0-SL2) and a 3 to 8 line decoder, 8 decoded scan lines are generated. These 8 decoded scan lines in conjunction with the 8 return lines can form an 8 x 8 keyboard matrix as shown in figure 10.4. Two more extra lines SHIFT and CNTL (control) can also provide four more different combinations as shown in table 10.1. Table 10.1 SHIFT

CNTL

0

0

0

1

1

0

1

1

302

Fig. 10.4 With these four combinations and 8 x 8 matrix 4 x 8 x 8 = 256 character definitions are possible. Decoded Mode: In the decoded mode, an internal decoder is used to provide all the four scan lines (SL0-SL3) as the decoded lines as shown in table 10.2. Table 10.2 SL3

SL2

SL1

SL0

0

0

0

1

0

0

1

0

0

1

0

0

1

0

0

0

These four decoded lines with 8 return lines form the keyboard matrix as shown in figure 10.5. The SHIFT and CNTL lines in combination with the keyboard matrix can provide 4 x 4 x 8 128 character definitions. 303

Fig. 10.5 The disadvantage of the decoded scan is that the number of combinations of the scan lines as given in table is only four. Hence, only four rows can be used in case of keyboard and only four digits can be used for the display. 10.5 SCANNED KEYBOARD In this mode, when a key is pressed, a unique 6 bit data is generated characteristic of the key position. An 8-bit word is formed, with the 6-bit position data for the key pressed and two bits for control (CNTL) and SHIFT lines. The format for the scanned keyboard mode is shown in figure 10.6. The scan counter has three scan bits (D5-D3) as

Fig. 10.6 000 to 111 for the row on which the pressed key is located. The column counter also has three bits (D2-D0) as 000 to 111 for column on which the pressed key is located. Figure

304

10.7 shows the 8 x 8 keyboard matrix that has the 8 return lines and 8 scan lines. It has 64 key positions (0 to 63) which generate 8 bit data word for the key pressed. The 8 bit data word generated for a key pressed may be understood if we consider CNTL and SHIFT lines are 00. Suppose a key number 15 is pressed. The row line corresponding to the key number 15 is 1 (three bit binary is 001) and the column line for this pressed key is 7 (three bit binary is 111) so the 8 bit data formed for this pressed key becomes: 00 001 111 which is the binary equivalent of 15 (0F H). Similarly, the 8 bit data word for the key pressed 32 is 00 10 000 (20 H).

Fig. 10.7 The 8-bit data thus formed corresponding to the key pressed is stored in FIFO (first in first out) RAM inside the 8279. As soon as the 8-bit word is stored in FIFO RAM, IRQ terminal of 8279 goes high. This terminal is connected to one of the hardware interrupt line of CPU. With the high IRQ, the interrupt line of the CPU will be activated and the service subroutine program of the hardware interrupt will read the data from the FIFO RAM. As the data is read from the FIFO RAM, the IRQ terminal goes low; and it becomes high again if FIFO RAM contains further data. The scanned keyboard mode has further two alternative ways of operation: •

Two-key lockout

•

N-key rollover

10.5.1 Two-key Lockout

305

The mechanical keys used in the keyboard have a problem. When a key is pressed the contacts bounce back and forth and finally settle down after a small time. Due to this contact bounce problem multiple entries may be made for the same key. This can be avoided either by using the debouncing circuit using flip-flops etc. or by making the device to wait for few milliseconds after the key is pressed. In the 8279, second method is used for debouncing which is the built in feature of this IC. In the two-key lockout operation, if two keys are depressed within the bounce cycle, it is called a simultaneous depression and neither key will be recognized until one of the keys is released. The last key released will be recognized and its corresponding 8bit code will be entered in FIFO RAM. If after the first key is depressed, and no other key is found to be depressed within next two scans, then it is taken as a single key depression and the code for the depressed key will be entered in FIFO RAM. If after the first key depression, one or more additional key depression is detected within the next two scans, then there will be following two possibilities: If all keys are released before the first pressed key, then the first key data will be entered in FIFO RAM. If first key pressed is released before others, then the press key will be entirely ignored. 10.5.2 N-key Rollover In this mode, each key depression is treated independent. If simultaneous key depression occurs then keys are recognized and entered in FIFO RAM according to the order of the key pressed. In fact when a key is pressed the debounce circuit inside the 8279 waits for two scans then checks if this key is still pressed. If this key is still pressed, the code for the key depressed is entered into FIFO RAM. 10.6 SCANNED SENSOR MATRIX As discussed earlier, the keyboard matrix size is 8 x 8 in encoded scan lines and 4 x 8 in decoded scan lines. In this mode, the keys are placed in the form of matrix either in 8 x 8 encoded scan lines or 4 x 8 decoded scan lines, the scan lines form the columns and return lines form the rows of the keyboard matrix. The key status (open or closed) is stored in RAM which can be addressed by the CPU. The data on each of the eight lines enter directly in eight columns of sensor RAM; and each switch position maps to specific sensor RAM positions. The SHIFT and CNTL lines are not considered as inputs. The format for each row of the sensor RAM is shown in figure 10.8. The logic circuits can also be connected to the return lines which will be triggered by the scan lines. The debouncing circuit is not provided in this mode. It therefore has the advantage that the CPU knows how long the sensor was closed. The IRQ line goes high if a sensor value is found to have changed at the end of sensor matrix scan. The IRQ line is cleared by the first data read operation if the auto increment flag is set to zero or by the End Interrupt Command if the auto increment flag is set to one.

Fig. 10.8

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10.7 STROBED INPUT In this mode, the data is accepted from the return lines and go to FIFO RAM and entered at the rising edge of CNTL/STB line pulse. The data placed on the return lines can come from any source. The data is stored in the same format as shown in figure 10.8. Each scan line would lead to an 8-bit word. 10.8 DISPLAY INTERFACE The interfacing of keyboard with the 8279 has been discussed in the preceding sections. The interfacing of display devices with the 8279 will now be discussed. Generally seven segment display devices are connected with 8279 using the multiplexing technique. In the multiplexing technique the seven segment code is sent to all the displays simultaneously, but the particular segment to be illuminated is only grounded (in case of common cathode displays).

Fig. 10.9 In the 8279, eight output terminals, OUT A0-A3 and OUT B0-B3 are provided for the purpose of interfacing the seven segment displays. If a 4-to-16 line decoder is used with the scan lines (SL0-SL3), then a maximum of 16 display devices may be connected to the 8279. The internal FIFO RAM of 8279 can hold 8-bit data for 16 digits. If a 3-to-8

307

line decoder is used with three scan lines (SL0-SL2), then a maximum of 8 displays may be connected to this IC. All the segments of display devices are connected in parallel (i.e. a’s segment of all the displays are tight together, similarly for b’s to g’s and dp’s segments). These segments are then connected to the output terminals OUT A0-A3 and OUT B0-B3, as shown in figure 10.9. The OUT A0, OUT A1, OUT A2 and OUT A3 lines of the 8279 are connected to segments a, b, c and d respectively. The OUT B0, OUT B1, OUT B2 and OUT B3 lines of the 8279 are connected to segments e, f, g and dp respectively. The decoded outputs of scan lines provide 0 to 7 outputs in a periodic fashion, to select one digit of the display devices at a time. The BD line is used to blank all display digits. When a given bit is 1, the corresponding segment is switched ON. For example the key code for the alphabet ‘C’ is obtained if the segments a, d, e and f are high. The data code for the alphabet ‘C’ is 93 as shown in figure 9.10.

Fig. 10.10 10.9 DISPLAY MODES The interfacing of display devices with 8279 has been discussed in the earlier section. Further there are following two options for the display formats in the display modes of 8279: • Left Entry Mode (Type Writer Mode) •

Right Entry Mode (Calculator Mode)

10.9.1 Left Entry Mode (Type Writer Mode) In the left entry mode, the first location of the display RAM data is treated as the segment for the left most digit and second location of the display is treated as the segment data for the second digit from the left and so on. This is similar to typing the paper with

308

the type writer. In this mode there is auto-increment facility as in the type writer; the

Fig. 10.11 carriage advances one step during typing. The left entry mode with auto increment facility is illustrated in figure 10.11 for 16 digits to be displayed on the display devices. From this figure it is clear that the first entry goes to the address 0 (first one of sixteen) for one word RAM and to the left most display position. The second entry goes to address 1 and the second display position and so on. The 16th entry goes to the address 15 of the display RAM and position 16 of the display. The 17th entry fill the left most position again. There is a command (the details of which will be discussed in the next section) which allows entering data at an arbitrary address location of the display RAM. Figure 10.12 illustrates the result of a command that is used to display the next data to the 6th position using 8-digit display. The command word given here is 10010110 which contains 8 bits, the three most significant bits 100 represents the “write display RAM”: the next bit 1 is for auto increment and the next four bits 0110 (6th) are for the position at which it should start filling. This command does not lead to any undesirable result.

309

Fig. 10.12 10.9.2 Right Entry Mode (Calculator Mode) The right entry mode is also known as calculator mode. In this mode the first location of the display RAM indicates the display data for the right most digit. Therefore, on the display, the data appears to start from the right and shift towards left as the digits move left in the calculator when the data is entered in to it. Figure 10.13 shows how the data are entered in this mode for 16 digits display with auto increment. The first character appears at the right display position. When a second character enters, the first character shifts towards the left by one place on the display. Similarly at the third entry, both the characters move by one place left each and the third character again takes the original right most position. It has been observed that a given character entered at a certain display position continues to remain there; but in case of right entry mode at every new entry each existing character moves one place to the left and finally the left most character shifts off the end, and is lost.

310

Fig. 10.13 Figure 10.14 shows the entering of the data in right entry mode with auto increment for 8 digit display using the command word for entering data at an arbitrary address location of the display RAM. The results obtained for entering data at an arbitrary address location in this mode are unexpected. Therefore, a starting display RAM address 0 and sequential entry are recommended in this right entry mode.

311

Fig. 10.14 10.10 PROGRAMMING OF 8279 The 8279 is a programmable keyboard and display interface device so it may be programmed for the desired operation. There are following 8 commands that can be used in the 8279: Keyboard/Display Mode Set Program Clock Read FIFO/Sensor RAM Read Display RAM Write Display RAM Display Write Inhibit/Blanking Clear End Interrupt/Error Mode Set The command word, whose format is shown in figure 10.15, is sent on the data bus with CS low and A0 high. The word is loaded to the 8279 using the write operation.

312

Fig.10.15 In this command word format, the three most significant bits selects the various operations which are given as: D7

D6

D5

Function

0

0

0

Keyboard/Display Mode Set

0

0

1

Program Clock

0

1

0

Read FIFO/Sensor RAM

0

1

1

Read Display RAM

1

0

0

Write Display RAM

1

0

1

Display Write Inhibit/Blanking

1

1

0

Clear

1

1

1

End Interrupt/Error Mode Set

10.10.1 Keybaord/Display Mode Set This command sets up the operation of keyboard and display mode. The command bit pattern for the same is given as (figure 10.16):

Fig. 10.16 D D represents the display mode and K K K represents the keyboard mode. D D in D4 D3 bit positions has the following four display mode options: D4

D3

Display Option

0

0

Eight 8-bit character display with left entry

0

1

Sixteen 8-bit character display with left entry

1

0

Eight 8-bit character display with right entry

1

1

Sixteen 8-bit character display with right entry

313

K K K in D2 D1 D0 bit positions has the following four display mode options: D2

D1

D0

Keyboard Option

0

0

0

Encoded Scan Keyboard with 2-key lockout

0

0

1

Decoded Scan Keyboard with 2-key lockout

0

1

0

Encoded Scan Keyboard with N-key roll over

0

1

1

Decoded Scan Keyboard with N-key roll over

1

0

0

Encoded Scan Sensor Matrix

1

0

1

Decoded Scan Sensor Matrix

1

1

0

Strobed Input Encoded Display Scan

1

1

1

Strobed Input Decoded Display Scan

The command word to set decoded scan keyboard with 2-key lockout and to have eight 8-bit characters with right entry in the display mode can be shown as:

Fig. 10.17 If the address of the command port for 8279 is FF H, then by executing the following instructions, keyboard and display mode will be set as per the requirement discussed above: MVI A, 11 H OUT FF H 10.10.2 Program Clock The different keys of the keyboard are scanned one by one in a sequence to detect a key press by the 8279; and also key debouncing is implemented by this device. All these functions require the timing signal. The 8279, therefore, needs an internal clock. The frequency of this clock should be around 100 KHz. But the clock of the system (i.e. the frequency of the external clock terminal of 8085) is 3 MHz. This system clock or any other external clock signal of known frequency may be applied to the CLK terminal (pin no. 3) of 8279. The 8279 internally provides an arrangement so that the clock applied at the pin no. 3 may be divided by a known factor to get the clock frequency of about 100 KHz. The frequency division is possible by the software.

Fig. 10.18 314

A command word is generated to get the required clock frequency after division of the system clock or external clock connected to pin no. 3 of 8279. The command word format is given in figure 10.18. The five bits (D0 to D4) of the command word define the scale factor. These five bits P P P P P may be set 0 0 0 0 0 to 1 1 1 1 1 whose decimal equivalents are 0 to 31. So the scale factor may be chosen up to 31. The scale factor will be given by: System− frequency Scale Factor = 100 KHz If the external clock frequency applied to pin 3 of 8279 is 2 MHz, then the scale factor will be: 2 MHz Scale Factor = 100 KHz = 20 The binary equivalent of 20 in five bits is 1 0 1 0 0 (represent P P P P P) and the command word will be given by (figure 10.19):

Fig. 10.19 Similarly, if the system clock frequency of 3 MHz is applied to 8279, then the scale factor is given by: 3 MHz Scale Factor = 100 KHz = 30 The binary equivalent of 30 is 1 1 1 1 0 and the command word will be given by (figure 10.20):

Fig. 10.20 The following instructions after execution will set the program clock to 100 KHz, if the system clock frequency of 3 MHz is applied to 8279. The command for this is 3E H as discussed above. MVI A, 3E H OUT FF H The address of the command port for 8279 is assumed as FF H. 10.10.3 Read FIFO/Sensor RAM

The command word for setting up the 8279 to read FIFO/sensor RAM is shown in figure 10.21.

315

Fig. 10.21 The bits D7 D6 D5

represent for command word 2 (0 1 0).

AI

represents Auto Increment.

X

is don’t care.

A A A (D2 D1 D0)

represent RAM address bits.

In the sensor matrix mode, the address bits A A A represent on the 8 rows of the sensor RAM. If AI is set to 1, the successive Read operation is performed from the subsequent row of the sensor RAM. In the keyboard mode, auto increment bit AI and address bits A A A are irrelevant and the 8279 will automatically drive the data for each subsequent read (A0 = 0) in the same sequence in which the data first entered in FIFO RAM. If the data is to be read from the 3rd row of the sensor RAM, then the command word will be as:

Fig. 10.22 10.10.4 Read Display RAM The command word for setting up the 8279 to read display RAM is shown in figure 10.23.

Fig. 10.23 The bits D7 D6 D5

represent for command word 3 (0 1 1).

AI

represents Auto Increment.

A A A A (D3 D2 D1 D0)

select one of the 16 rows of display RAM that is to be read.

If the auto increment bit AI is set to 1, then the row address will automatically be incremented after each of the Read to display RAM. The command word 0 1 1 1 0 0 0 0 (= 70 H) represents a read from the display RAM. 10.10.5 Write Display RAM

316

To display information, the seven segment data is to be written in the internal display buffer. To enable writing seven segment data into display buffer, the write display RAM command has to be written into the command word register. The command word for the same is shown in figure 10.24.

Fig. 10.24 The bits D7 D6 D5

represent for command word 4 (1 0 0).

AI

represents Auto Increment.

A A A A (D3 D2 D1 D0)

is the address of the digit that the CPU writes into the buffer. Four bit address is provided to select any one of the digits.

After the write command with A0 = 1, all the subsequent writes with A0 = 0 will be to the display RAM For example, to write the segment codes 63 H and B5 H in the first and second locations of the display RAM, the command will be given as:

Fig. 10.25 The following instructions will write the segment codes 63 H and B5 H in the first and second locations of the display RAM: MVI A, 90 H OUT FF H MVI A, 63 H OUT FE H MVI A, B5 H OUT FE H The first two instructions MVI A, 90 H and OUT FF H writes the command word in the command word register (FF H is the address of the command word register with A0 is 1). The next two instructions MVI A, 63 H and OUT FE H writes the segment code 63 H in the first location of the display RAM (OUT FE H is the address for the same with A0 = 0); and the last two instructions MVI A, B5 H and OUT FE H writes the segment data B5 H in the next location of display RAM as the in the command word auto increment AI bit is set to 1.

317

10.10.6 Display Write Inhibit/Blanking The control word for Display Write Inhibit/Blanking is shown in figure 10.26.

Fig. 10.26 The bits D7 D6 D5

represent for command word 5 (1 0 1).

X

represents don’t care may be taken as 0.

IW

Inhibit Write Flag.

BL

Blank Display Flag.

The display write inhibit control word inhibits writing to either left most 4 bits of the display or right most 4 bits. By setting D3 (IW) bit to 1, the left most significant 4 bits of the display will be masked or inhibited and similarly, by setting D2 (IW) bit to 1, the right most significant 4 bits will be masked or inhibited. Similarly, the blank flag (BL) blanks half of the output pins. By setting D1 (BL) bit to 1, the left most significant 4 bits will be blanked (or turned off); and by setting D0 (BL) bit to w, the right most significant 4 bits will be blanked. 10.10.7 Clear The command word to clear the display, FIFO or both is shown in figure 10.27.

Fig. 10.27 The bits D7 D6 D5 represent for command word 6 (1 1 0). CA Clears All (it clears both display RAM and FIFO). CF Clears FIFO Status and resets the IRQ line. CD CD CD Clears all rows of the display RAM to a selectable blanking code. The selectable blanking code CD CD CD is defined as follows: CD CD CD 0 X All display RAM locations become 00000000 (all zeros). 0 0 AB becomes 00100000 (20 H). 1 1 All ones 11111111 (FF H). Enables clear display when 1.

318

If CF bit is set to 1, it clears FIFO and the display RAM status, and sets address pointer to 000; it also resets the IRQ lne. The bit CA has the combined effect of CD and CF; if it is set to 1 it clears the display RAM and also clears FIFO status. 10.10.8 End Interrupt/Error Mode Set The command word to end interrupt/error mode set is shown in figure 10.28.

Fig. 10.28 The bits D7 D6 D5

represent for command word 6 (1 1 0).

The bit D4

represents Error (E) which may be programmed to set the error mode or clear the IRQ line.

are represented by X, means don’t care and these may be considered as 0s. For the sensor matrix mode this command lowers the IRQ line and enables writing into RAM. For the N-key rollover if the bit E is programmed to 1 the chip will be operated in the special error mode. 10.11 STATUS REGISTER (IN OPERATION) The bits D3 - D0

The status word gives the information about how many characters are in the FIFO RAM and whether an error has occurred. The status word can be read by the CPU when A0 = 1 or in other words we can say that the status word can be read by the command register (IN FF H in the present case if FF H is the address of the command register).

Fig. 10.29 The bit D7

represents DU - Display Unavailable.

The bit D6

represents S/E - Sensor Closure/Error Flag for multiple closure.

The bit D5 represents O- Over-run error. The bit D4 represents U- Under-run error. The bit D3 represents F- FIFO Full. The bits D2 to D0 represent NNN as the number of key codes in FIFO RAM. In this status word the first three bits D2 to D0 labeled as NNN identify the number of key codes or characters that are currently present in the FIFO.

319

The next bit F (D3) indicates whether FIFO is Full or Empty. If F = 1, then it means FIFO is full. The FIFO is empty is F = 0. The next two bits U and O (D4 and D5) are related to the under-run or over-run errors. Over-run error indicates that an attempt was made to enter the key code or character in FIFO RAM when it was already full. The other error under-run means the processor attempted to read the FIFO when it was empty. In the special error mode, the bit S/E (D6) is showing that an error flag gives an indication whether a simultaneous multiple closure error has occurred. The most significant bit DU (D7) of the status word stands for display unavailable. When the clear display command is send, the 8279 clears the display and clearing requires some very small time. In this duration the display is unavailable and the data can not be read or written in display RAM. The bit DU is 1 when clearing is going on and it is automatically reset when display RAM becomes available again for writing. Read Operation To read FIFO RAM for the keyboard data following steps are carried out: Step I

Send Keyboard/display command word to command register. Say: D7 0

D6 0

D5 0

D4 0

D3 0

Eight 8-bit Character display - left entry. Step II

D2 0

D1 0

D0 0

= 00 H

Encoded scan keyboard - 2 Key lockout.

A read FIFO RAM command is written into the command register as: D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 AI X A A A 0 1 0 0 0 0 0 0 (AI and A A A are irrelevant in sensor matrix mode).

= 40 H

Step III

Read the status word by using IN instruction and port address is for A0= 0. Further, status word is checked, if D0 bit is 1. If it is 1, which indicates one character or key code is available in the first location of FIFO RAM.

Step IV

Read FIFO RAM command word is entered into the command register.

Step V

Now the key data can be read from the data register with A0 = 0. Using these steps program may be written as given below:

Program: Label

LOOP

Mnemonics MVI A, OUT

Operand 00 H FF H

IN ANI

FF H 01 H

320

Comments ; Encoded scan, 2 key lockout mode. ; Keyboard display code is written in command register. ; Read the status word. ; Check if D0 is 1.

JZ

LOOP

MVI A, OUT IN

40 H FF H FE H

; If D0 = 0 then read the status word again till D0 is 1. ; Load FIFO RAM command word ; in command word register. ; Read the data register to take the key code.

10.12 INTERFACING OF 8279 WITH 8085 Since the 8279 is an I/O device, so it can be used as memory mapped I/O device or I/O mapped I/O device. The interfacing of this IC with 8085 microprocessor is shown in figure 10.29.

Fig. 10.29 The description of the connections of this IC with 8085 microprocessor is given below: •

The 8 data lines (DB0-DB7) are connected to the data bus of the microprocessor.

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•

The RESET signal of 8279 is connected to the RESET OUT terminal of the CPU.

•

The active low terminals RD and WR of 8279 are connected to active low terminals IOR and IOW of the CPU.

•

The CLK signal of this IC may be connected to either an external clock signal or the CLK OUT terminal of the processor.

•

The buffer address terminal A0 of 8279 is connected to the A8 terminal of the address bus of the microprocessor. A low signal on this pin indicates data word and a high on this pin indicates the command word.

•

The output of the address decoder circuit is connected to active low terminal CS of the IC 8279. The A9-A15 terminals of the address bus of the microprocessor are connected to the inputs of the decoder circuit. These connections show that FF H is the address of the command register and FE H is the address of the data register.

•

The Scan lines SL0-SL2 of the 8279 are connected to a 3 to 8 line decoder, the outputs of which are connected to the 8 x 8 keyboard matrix. The eight return lines RL0-RL7 along with the CNTL (control) and SHIFT terminals are also connected with the keyboard matrix.

•

The sixteen 7-segment LED displays are also connected to this IC 8279 through the OUT A0-A3 and OUT B0-B3 terminals. The common terminals of the digit display are connected to the Scan lines SL0-SL3 through 4-to-16 line decoder.

Example 10.1. A 4 x 4 keyboard matrix is to be interfaced with 8085 microprocessor using 8279. Give the necessary hardware for the same. Also give the software to enter the hex code of the key pressed and store this code to memory location 2500 H. Given frequency of the clock connected to the CLK terminal of 8279 is 2.5 MHz. Assume Decoded scan mode with N-key-roll over. Let control port address is 81 H and data port address is 80 H. Solution. The hardware needed to interface 4 x 4 keyboard matrix with 8085 microprocessor is given in figure 10.30. The initialization steps for providing the software are given below: 1.

Send Keyboard/display command word to command register. Say: D7 0

D6 0

D5 0

D4 0

D3 0

Eight 8-bit Character display - left entry.

322

D2 0

D1 1

D0 1

= 03 H

decoded scan keyboard - N Key rollover.

2.

3.

Fig. 10.30 The frequency of the clock is to be set around 100 KHz from 2.5 MHz. This frequency is to be divided by 25 generating the program clock word as: D7 D6 D5 D4 0 0 1 P 0 0 1 1 11001 for PPPPP is 25. Generate clear command word as: D7 D6 D5 D4 1 1 0 0

D3 P 1

D2 P 0

D1 P 0

D0 P 1

= 39 H

D3 0

D2 0

D1 1

D0 1

= C3 H

323

It will clear all. 4.

A read FIFO RAM command is written into the command register as: D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 AI X A A A 0 1 0 0 0 0 0 0 (AI and A A A are irrelevant in sensor matrix mode).

5.

= 40 H

Check the status word if the key is pressed.

The program for the same is written as: Program: Label Mnemonics 0perand MVI A, 03 H

LOOP

OUT

81 H

MVI A, OUT MVI A, OUT

39 H 81 H C3 H 81 H

IN ANI JZ

81 H 07 H LOOP

MVI A, OUT IN

40 H 81 H 80 H

STA

2500 H

HLT

Comments ; Decoded scan, N key roll-over mode. ; Keyboard display code is written in command register. ; Program clock ; is set to 100 KHz. ; Clear FIFO. ; Clear command word is loaded to command register. ; Read the status word. ; Check if key pressed. ; If not then read the status word again till the key is pressed. ; Load FIFO RAM command word ; in command word register. ; Read the data register to take the key code. ; Store the Hex code for the key pressed in memory location 2500 H. ; Stop processing.

Example 10.2. An 8279 is to be initialized with the following requirements: Keyboard encoded scan mode with N key rollover. External clock frequency is 2 MHz. Control port address is FF H and Data port address is FE H. The IRQ line of the 8279 is connected to the RST 7.5 interrupt of 8085A. Write an interrupt service routine to store the hex code of the key pressed in 2501 memory location. Solution. The initialization steps for providing the software are given below: 1.

Send Keyboard/display command word to command register. Say:

324

D7 0

2.

4.

4.

D6 0

D5 0

D4 0

D3 0

D2 0

D1 1

D0 0

Eight 8-bit encoded scan keyboard Character - N Key rollover. display - left entry. The frequency of the clock is to be set around 100 KHz from 2 MHz. This frequency is to be divided by 20 generating the program clock word as: D7 D6 D5 D4 0 0 1 P 0 0 1 1 10100 for PPPPP is 20. Generate clear command word as: D6 D5 D4 D7 1 1 0 0 It will clear all.

D3 P 0

D2 P 1

D1 P 0

D0 P 0

= 34 H

D3 0

D2 0

D1 1

D0 1

= C3 H

A read FIFO RAM command is written into the command register as: D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 AI X A A A 0 1 0 0 0 0 0 0 (AI and A A A are irrelevant in sensor matrix mode).

5.

= 02 H

= 40 H

Check the status word if the key is pressed.

Program: Label

Mnemonics MVI A,

Operand 02 H

Comments ; Encoded scan, N key roll-over mode. OUT FF H ; Keyboard display code is written in command register. MVI A, 34 H ; Program clock OUT FF H ; is set to 100 KHz. MVI A, C3 H ; Clear FIFO. OUT FF H ; Clear command word is loaded to command register. EI ; Enable interrupts. MVI A, 0B H ; Enable RST 7.5. SIM ; Set interrupt mask. In this case when key code is available in FIFO RAM the IRQ line becomes high and enables RST 7.5 interrupt. The program will jump to the vector location 003C H of this interrupt, from where it jump to the service routine. 003C H JMP ISR ; Jump to service routine.

325

ISR

; Load FIFO RAM command word ; in command word register. ; Read the data register to take the key code. STA 2501 H ; Store the Hex code for the key pressed in memory location 2500 H. RET ; Return Example 10.3. An 8279 keyboard/display interface is used to drive eight 7-segmnet display in multiplexed mode. Write a program to initialize 8279 to display a message ‘HELLO 07’. External clock frequency is 1.5 MHz. Control port address is 19 H and Data port address is 18 H. Solution. The initialization steps for providing the software are given below: 1.

MVI A, OUT IN

Send Keyboard/display command word to command register. Say: D7 0

2.

3.

4.

40 H FF H FE H

D6 0

D5 0

D4 0

D3 0

D2 0

D1 0

D0 0

= 00 H

Eight 8-bit Character display - left entry. The frequency of the clock is to be set around 100 KHz from 1.5 MHz. This frequency is to be divided by 15 generating the program clock word as: D7 D6 D5 D4 0 0 1 P 0 0 1 0 01111 for PPPPP is 15. Generate clear command word as: D7 D6 D5 D4 1 1 0 1 It will clear all.

D3 P 1

D2 P 1

D1 P 1

D0 P 1

= 2F H

D3 0

D2 0

D1 1

D0 1

= D3 H

Display RAM command is written into the command register as: D7 D6 D5 D4 D3 D2 D1 D0 1 0 0 AI A A A A 1 0 0 1 0 0 0 0 = 90 H (AI =1 for auto increment and 0000 for A A A A as address bits).

Program: Label

Mnemonics MVI A, OUT

Operand 00 H 19 H

326

Comments ; 8 bit character display mode. ; Keyboard display code is written in command register.

UP

REP

MVI A, OUT MVI A, OUT

2F H 19 H D3 H 19 H

; ; ; ;

IN ANI JNZ LXI H,

19 H 80 H UP 2100 H

; ; ; ;

MVI C,

08

;

MVI A, OUT

90 H 19 H

; ;

MOV A, OUT INX H

M 18 H

; ; ;

DCR C JNZ HLT

; ; ;

REP

Program clock is set to 100 KHz. Clear FIFO. Clear command word is loaded to command register. Read the status word. Check if display available. If not available, read again. Point to the data in address location. C is used counter for eight characters of ‘HELLO 07’. Write display command The command word is loaded in command register. Write the segment code in display RAM. Increment H-L pair to point the next code. Decrement C. If C is not zero jump to REP. Stop processing.

Enter hex codes for HELLO 07 in the memory locations starting at 2100 H. Location Hex code for 2100 H H 2101 H E 2102 H L 2103 H L 2104 H O 2105 H - (Blank) 2106 H 0 2107 H 7 Example 10.4. An 8 X 8 keyboard matrix (64 keys) and 8 common cathode seven segment displays are interfaced with 8085 through 8279. Write a program to initialize 8279 to display a message ‘DISPLAY’ on pressing key “0”. External clock frequency is 2.0 MHz. Control port address is 05 H and Data port address is 04 H. Solution. The initialization steps for providing the software are given below: 1.

Send Keyboard/display command word to command register. Say:

327

D7 0

2.

3.

4.

D6 0

D5 0

D4 0

D3 0

D2 0

D1 0

D0 0

= 00 H

Eight 8-bit Character display - left entry. The frequency of the clock is to be set around 100 KHz from 2.0 MHz. This frequency is to be divided by 20 generating the program clock word as: D7 D6 D5 D4 0 0 1 P 0 0 1 1 10100 for PPPPP is 20. Generate clear command word as: D6 D5 D4 D7 1 1 0 1 It will clear all.

D3 P 0

D2 P 1

D1 P 0

D0 P 0

= 34 H

D3 0

D2 0

D1 1

D0 1

= D3 H

Display RAM command is written into the command register as: D7 D6 D5 D4 D3 D2 D1 D0 1 0 0 AI A A A A 1 0 0 1 0 0 0 0 = 90 H (AI =1 for auto increment and 0000 for A A A A as address bits).

Program: Label

UP

UP1

REP

Mnemonics MVI A, OUT

Operand 00 H 05 H

MVI A, OUT MVI A, OUT

34 H 05 H D3 H 05 H

IN ANI JNZ IN

05 H 80 H UP 05

ANI JZ

07 H UP1

MVI A, OUT IN

40 H 05 H 04 H

328

Comments ; 8 bit character display mode. ; Keyboard display code is written in command register. ; Program clock ; is set to 100 KHz. ; Clear FIFO. ; Clear command word is loaded to command register. ; Read the status word. ; Check if display available. ; If not available, read again. ; Read the status word again if the “0” is pressed. ; Check for 0. ; If zero, key “0” is not pressed repeat. ; Load FIFO command word ; in command word register. ; Read the data register to take the key code.

LOOP

CPI JNZ LXI H,

00 H REP 2100 H

MVI C,

07

MVI A, OUT

90 H 05 H

MOV A, OUT INX H

M 04 H

DCR C JNZ HLT

; Key “0” is pressed or not. ; If not repeat. ; Point to the data in address location. ; C is used counter for eight characters of ‘DISPLAY’. ; Write display command ; The command word is loaded in command register. ; Write the segment code in ; display RAM. ; Increment H-L pair to point the next code. ; Decrement C. ; If C is not zero jump to REP. ; Stop processing.

LOOP

Enter hex codes for DISPLAY in the memory locations starting at 2100 H. Location Hex code for 2100 H D 2101 H I 2102 H S 2103 H P 2104 H L 2105 H A 2106 H Y Example 10.5. An 8279 keyboard/display interface is used to drive sixteen 7-segmnet display in multiplexed mode. Write a program to initialize 8279 to display a blinking message “CONGRATULATIONS”. External clock frequency is 1.5 MHz. Control port address is 19 H and Data port address is 18 H. Solution. The initialization steps for providing the software are given below: 1.

Send Keyboard/display command word to command register. Say: D7 0

2.

D6 0

D5 0

D4 0

D3 1

D2 0

D1 0

D0 0

= 08 H

Sixteen 8-bit Character display - left entry. The frequency of the clock is to be set around 100 KHz from 1.5 MHz. This frequency is to be divided by 15 generating the program clock word as:

329

3.

4.

D7 D6 D5 D4 0 0 1 P 0 0 1 0 01111 for PPPPP is 15. Generate clear command word as: D7 D6 D5 D4 1 1 0 1 It will clear all.

D3 P 1

D2 P 1

D1 P 1

D0 P 1

= 2F H

D3 0

D2 0

D1 1

D0 1

= D3 H

Display RAM command is written into the command register as: D7 D6 D5 D4 D3 D2 D1 D0 1 0 0 AI A A A A 1 0 0 1 0 0 0 0 = 90 H (AI =1 for auto increment and 0000 for A A A A as address bits).

Program: Label

UP

LOOP

REP

Mnemonics MVI A, OUT

Operand 08 H 19 H

MVI A, OUT MVI A, OUT

2F H 19 H D3 H 19 H

IN ANI JNZ LXI H,

19 H 80 H UP 2100 H

MVI C,

0F

MVI A, OUT

90 H 19 H

MOV A, OUT INX H

M 18 H

DCR C JNZ CALL

REP DELAY

CALL

CLEAR

CALL

DELAY

JUMP

LOOP 330

Comments ; 8 bit character display mode. ; Keyboard display code is written in command register. ; Program clock ; is set to 100 KHz. ; Clear FIFO. ; Clear command word is loaded to command register. ; Read the status word. ; Check if display available. ; If not available, read again. ; Point to the data in address location. ; C is used counter for 15 characters of ‘CONGRATULATIONS’. ; Write display command ; The command word is loaded in command register. ; Write the segment code in ; display RAM. ; Increment H-L pair to point the next code. ; Decrement C. ; If C is not zero jump to REP. ; Introduce some delay using a Delay subroutine. ; A subroutine to clear the display is used. ; Delay is introduce so that display is clear for some time. ; Jump to repeat the display.

HLT

; Stop processing.

Enter hex codes for “CONGRATULATIONS” in the memory locations starting at 2100 H. Location Hex code for 2100 H C 2101 H O 2102 H N 2103 H G 2104 H R 2105 H A 2106 H T 2107 H U 2108 H L 2109 H A 210A H T 210B H I 210C H O 210D H N 210E H S

1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16.

PROBLEMS Draw the function block diagram of Programmable Keyboard/Display interface 8279 and also discuss the function of each block. Discuss three input modes of Keyboard scan of 8279. Describe Scanned keyboard mode of 8279 with 2-key lockout and N-key rollover. Discuss Scanned sensor matrix mode for 8279. Discuss encoded mode of Keyboard scan of 8279. Discuss decoded mode of Keyboard scan of 8279. Describe left entry mode for display of 8279. Name 8 command words of 8279 and discuss the command word format for the program clock. Discuss the command word format for Read display RAM. Discuss the command word format for keyboard/display mode set. Discuss the command word format for Read FIFO/Sensor RAM. Discuss the command word format for Display write Inhibit/blanking. Discuss the command word format for End Interrupt/Error mode set. Explain status register of 8279. How the status word can be read. Discuss how 8279 can be interfaced with 8085A. Mention various steps to be carried out for the initialization of 8279 with following specifications: Keyboard encoded scan mode with N key rollover. External clock frequency is 2 MHz. Control port address is 11 H and Data port address is 10 H.

331

17.

18.

19.

20.

An 8279 keyboard/display interface is used to drive sixteen 7-segmnet display in multiplexed mode. Write a program to initialize 8279 to display a blinking message “HAPPY BIRTH DAY”. External clock frequency is 2.0 MHz. Control port address is 05 H and Data port address is 04 H. An 8 x 8 keyboard matrix (64 keys) and 8 common cathode seven segment displays are interfaced with 8085 through 8279. Write a program to initialize 8279 to display a message ‘PLEASE” on pressing key “0”. External clock frequency is 2.5 MHz. Control port address is FF H and Data port address is FE H. An 8279 keyboard/display interface is used to drive sixteen 7-segmnet display in multiplexed mode. Write a program to initialize 8279 to display a message ‘BEST WISHES’. External clock frequency is 2.5 MHz. Control port address is 01 H and Data port address is 00 H. An 8 x 8 keyboard matrix is to be interfaced with 8085 microprocessor using 8279. Give the necessary hardware for the same. Also give the software to enter the hex code of the key pressed and store this code to memory location 2500 H. Given frequency of the clock connected to the CLK terminal of 8279 is 2.5 MHz. Assume Decoded scan mode with N-key-roll over. Let control port address is 19 H and data port address is 18 H.

________

332

11 Programmable Interrupt Controller: 8259 This chapter will confine to the detailed discussion on Programmable Interrupt Controller (PIC) – 8259. This device is also called priority interrupt controller. It is designed to work with Intel 8080A, 8085A, 8086 and 8088 microprocessors. It works as an overall manager in an interrupt driven system environment. This device can handle 8 external interrupts and the starting address of the interrupts service routine can be vectored to any location in the memory map unlike the software and hardware interrupts which point to the predetermined starting address. The 8259 can be set to accept level triggered or edge triggered interrupts. The interrupt can be expanded to 64 interrupt inputs by cascading many 8259 device. 11.1 PROGRAMMABLE INTERRUPT CONTROLLER 8259 It n an earlier chapter it has been discussed that the 8085A has four hardware interrupt terminals namely TRAP, RST 5.5, RST 6.5 and RST 7.5. When the I/O device sends an interrupt signal to the CPU, the CPU completes the current instruction and branches to the service routine of the interrupt. After the execution of the ISR, it returns to the main program. In addition to these inputs, the CPU can also be interrupted through its INTR input. When an interrupt input signal INTR is send to the microprocessor, the CPU then send an interrupt acknowledge signal INTA to the external device. In response to this acknowledge signal the op code of the CALL instruction is placed on the data bus. The CPU reads the op code and sends another INTA signal. This signal is used to place the low order eight bits address of the CALL instruction on to the data bus. After reading the low order address the CPU sends another INTA signal. It then places the high order eight bit address on to the data bus. The CPU then reads and executes the interrupt service routine available in that CALL address. The number of I/O devices that may be used in an interrupt driven environment may be made greater than four if an external device is used. The external device should be capable of accepting interrupt requests and generating unique CALL instructions for the different interrupt inputs. This device will be used to interrupt the microprocessor on the INTR line. A programmable interrupt controller (PIC) is such a device (ref. figure 11.1) which accepts interrupt requests from a number of I/O devices, resolves the priority of servicing the requests, and issues an interrupt on the INTR input of the 8085A as discussed above.

Fig. 11.1 11.2 BLOCK DIAGRAM OF 8259 The 8259 is a programmable interrupt controller which uses NMOS technology. It is available in 28 pin plastic dual in line package (DIP). It requires one power supply of +5 V but does not require any internal or external clock. A single PIC can accept interrupt requests from eight I/O devices, resolve priority among them and communicate to the microprocessor. Interrupt requests from all the I/O devices can individually be masked and a suitable priority mode can be selected by programming. Built in expandability has also been provided to cascade 9 such Programmable Interrupt Controller devices (8259s) to serve up to 64 I/O devices. Figure 11.2 shows the pin diagram of this IC. The description of the pins of 8259 programmable interrupt controller is given as: Pin No. 1:

This pin is chip select terminal ( CS ). It is active low. When a low signal is applied to this terminal, the device is chosen to work.

334

Pin No. 2:

This is write input terminal ( WR ), which is also active low. A low to this input enables the CPU to write Initialization Control Word (ICW) and Operation Command Word (OCW) to the 8259A.

Fig. 11.2 Pin No. 3:

This is read input terminal ( RD ). A low to this pin enables the 8259A to send the status of the Interrupt Request Register (IRR), In Service Register (ISR), the Interrupt Mask Register (IMR) or the BCD of the interrupt level on the data bus.

Pin Nos. 4-11:

These pins (D0 to D7) form the bidirectional data bus to be connected to the data bus of the system.

Pin Nos. 12, 13 &15:

These pins (CS0 to CS2) are known as cascade lines. These lines are used to cascade a number of 8259A.

Pin No. 14:

This is a common ground terminal to be connected to the common terminal of the system or the supply.

Pin No. 16:

This is slave program/enable buffer ( SP / EN ). As already discussed more than one 8259A can be used with the system to expand the priority interrupt schemes up to 64 levels. In such cases one 8259A acts as the master and the others act as slaves. A high on this pin designates the 8259A as the master and a low to this pin designates as slave.

335

Pin No. 17:

This is an interrupt output terminal (INT) to be directly connected to the interrupt terminal (INTR) of the CPU. When an interrupt signals is applied to the any of the interrupt request terminals of the 8259, an INT signal is generated for the CPU.

Pin Nos. 18 to 25:

These are 8 interrupt request inputs (IR0 to IR7).

Pin No. 26:

This is an interrupt acknowledge input signal ( INTA ), connected to the INTA terminal of the CPU. A low acknowledgement signal is sent by the CPU to the 8259, whenever CPU receives an interrupt signal.

Pin No.27:

This pin A0 is the input signal used in conjunction with the signals WR and RD to write the commands into the various status registers of the device. This terminal can directly be connected to one of the address lines.

Pin No. 28:

This is supply pin (+VCC) connected to the positive 5 volts.

Fig. 11.3 336

Figure 11.3 shows the internal block diagram of the 8259A. The 8259A contains the following four sections: 1. Interrupt and Control Logic Section 2. Data Bus Buffer 3. Read/Write Control Logic Section 4. Cascade Buffer/Comparator Section 1. Interrupt and Control Logic Section This section contains the following five sections: •

Interrupt Request Register (IRR)

•

In-Service Register (ISR)

•

Priority Resolver

•

Interrupt Mask Register (IMR)

•

Control Logic Section

Interrupt Request Register (IRR) The interrupt request register (IRR) is used to store all the interrupt levels which are requesting services. It has 8-interrupt lines (IR0 to IR7). When any of these lines become high, the corresponding mask bit is checked and if it enabled, then the corresponding bit in the interrupt request register (IRR) is set. In-Service Register (ISR) The in-service register (ISR) is used to store information of all the interrupt levels which are currently being serviced. Priority Resolver This block of Interrupt and Control Logic Section determines the priorities of the bits set in the IRR. This block determines the priorities as dictated by the priority mode set by the Operation Command Words (OCWs). The bit corresponding to the highest priority interrupt is set in the ISR during the INTA input. It is a priority interrupt controller, this means, even while executing an interrupt, it will accept and service a higher priority; but it will reject a lower priority interrupt. The priority resolver does the job of judging whether to allow another interrupt to be executed in the middle of executing one interrupt service routine. Interrupt Mask Register (IMR) The interrupt mask register (IMR) stores the bits of the interrupt lines to be masked. The IMR operates on the ISR. In fact this register can be programmed by an operation command word (OCW) to store the bits of the interrupt lines to be masked. An interrupt which is masked by software will not be recognized and serviced even if it sets the corresponding bit in the IRR. Control Logic Section

337

After the interrupt request priorities are resolved by the priority resolver, this block control logic sends an interrupt signal through its INT signal to the CPU. This terminal INT is connected to the INTR terminal of the microprocessor. The microprocessor responds to this request by putting an interrupt acknowledge signal INTA to the input terminal INTA of the 8259A. The PIC then places the op code of CALL instruction on the data bus. This is read by CPU, it places two additional INTA signals on the data bus. When the CPU receives the INTA signal out of these two additional INTA signals, it places the low order byte of the CALL address on the data bus. After receiving the last INTA signal, it places the high order byte of the CALL address on the data bus. The CALL address is the vector memory location for t he interrupt; this address is placed in the control register during the initialization of 8259. 2. Data Bus Buffer This is a three state bidirectional 8-bit data bus buffer is used to interface the 8259A to the system data bus. The control words and status information are transferred through this data bus buffer. 3. Read/Write Control Logic Section The function of this Read/Write Control Logic section is to accept the commands from the CPU. It contains the initialization command word (ICW) registers and the operation command word (OCW) registers which store the various control formats for device operation. This section also accepts Read commands from the CPU to allow the CPU to read status words. The four pins are connected to this block whose functions are given below: CS (Chip Select) This pin is chip select terminal, which is active low. A low signal to this terminal selects this device to work. WR (Write) This is write input terminal, which is also active low. A low to this input enables the CPU to write Initialization Control Word (ICW) and Operation Command Word (OCW) to the 8259A.

RD (Read) A low to this pin enables the 8259A to send the status of the Interrupt Request Register (IRR), In Service Register (ISR), the Interrupt Mask Register (IMR) or the BCD of the interrupt level on the data bus. A0 This is the input signal used in conjunction with the signals WR and RD to write the commands into the various status registers of the device. This terminal can directly be connected to one of the address lines. 4. Cascade Buffer/Comparator Section It is well known that more than one 8259A can be used with the system to expand the priority interrupt schemes up to 64 levels. In such cases one 8259A acts as the master and the others act as slaves. The necessary control signals for cascade operations are generated with this block. A high on the Slave Program/Enable Buffer ( SP / EN ) pin designates the 8259A as the master and a low to this pin designates as slave. The 8259A

338

can be set as master or a slave by the SP / EN pin in the non-buffer mode, or by software in buffer mode of operation. In the non-buffer mode SP / EN pin is used as an output to enable the data bus buffer of the system. In addition to SP / EN pin, there are three more pins (CAS0 – CAS2) associated with the cascade buffer/comparator section, whose functions are described below: For a master, these pins (CAS0 – CAS2) are outputs, and for slave these are input pins. When 8259 is a master, the CALL op code is generated by the master in response to first INTA signal. The address for vector locations will be released by the slave 8259. Every 8259 has the identification code of three bits to CAS0 – CAS2 lines so that one out of eight possible slave may be selected by the master. Basically, the slave 8259s accept the identification signals as inputs and compare the code put out by the master with code assigned to them during initialization. The slave thus selected then puts out the address of the interrupt service routine during the two additional INTA signals sent by CPU. 11.3 INTERFACING OF 8259A WITH 8085A Figure 11.4 shows the interfacing connection of 8259A with 8085A microprocessor in I/O mapped I/O mode. The output of address decoder is connected to

Fig. 11.4

339

Fig.11.5

340

the CS input of the 8259A. The A0 line of the IC is directly connected to the address lines of the system. The RD and WR signals of the IC are connected to I / OR and I / OW terminals respectively. Further, INT terminal of the 8259 is connected to the INTR terminal of the processor. The INTA output of the processor is connected to the INTA terminal of the processor. The terminal SP / EN is connected to +5 V supply since only one 8259 is used in the system. If many 8259s are cascaded, then this terminal is connected to the ground terminal. The cascaded pins (CAS0 – CAS2) are left open. The eight interrupt request pins IR0-IR7 are available for the I/O devices to send the interrupt signals. If any of these interrupt request pins are not used, they may be connected to the ground so that the noise pulse can not create any interrupt.

The cascading of many 8259s with the system is shown in figure 11.5. The SP / EN terminal of the master PIC is connected to + VCC, whereas SP / EN terminals of all the slave PICs are connected to ground. The INT output of each slave PICs are connected to one of the interrupt lines (IR0-IR7) of the master 8259 i.e. 8 INT terminals of 8 slave 8259s are connected to 8 interrupt request lines (IR0-IR7). When interrupt request line of a slave is activated, the slave PIC in turn activates one of the interrupt request lines of the master 8259, which in turn interrupts the microprocessor. After the INTA is received from the microprocessor, the master enables the corresponding CAS0 – CAS2 lines to release the vector address on the data bus in the next two INTA signals. The output of the address decoder is connected to the CS of the 8259 PIC as shown in figure 11.4. It communicates with the CPU with the bidirectional bus. From this figure 11.4, it is clear that two I/O port addresses F0 H and F1 H are chosen for the 8259 with A0 = 0 and A0 = 1. It may be noted here that each 8259A (interfaced with 8085A) has its own I/O address which is defined by the address decoder. 11.4 VECTORING DATA FORMATS FOR 8259 The eight interrupt levels generate CALLs to eight equally spaced locations in the memory. Through the programming, these locations can be spaced at an interval of 4 or 8 locations. The format of a byte released in response to the first INTA for any IR levels is shown in figure 11.6.

Fig. 11.6 It is the op code for the CALL instruction (CD H). The format of the byte in response to the second INTA for different IR level is shown in figure 11.7, the details of which are given in table 11.1(a) and (b). These tables show for both 4 and 8 interval spacing. For spacing interval of four, the 8259 automatically inserts the bits D0 – D4 and D5 – D7 as specified while programming the 8259 through ICW 1 (first initialization command word, which will be discussed in the next section). For this interval bits D4-D2 specify the interrupt’s number and the rest two bits D1-D0 have been set to 00. However, 341

for spacing interval of eight, the 8259 automatically inserts the bits D0 – D5 and D6 – D7 as specified while programming the 8259 through ICW 1. For the interval of 8, the bits D5-D3 specify the interrupt’s number and the rest two bits D2-D0 have been set to 000.

Fig. 11.7

7

D7 A7

D6 A6

Table 11.1(a) INTERVAL = 4 D5 D4 D3 A5 1 1

6

A7

A6

A5

1

1

0

0

0

5

A7

A6

A5

1

0

1

0

0

4

A7

A6

A5

1

0

0

0

0

3

A7

A6

A5

0

1

1

0

0

2

A7

A6

A5

0

1

0

0

0

1

A7

A6

A5

0

0

1

0

0

0

A7

A6

A5

0

0

0

0

0

D2 0

D1 0

D0 0

IR

D2 1

D1 0

D0 0

7

D7 A7

D6 A6

Table 11.1(b) INTERVAL = 8 D5 D4 D3 1 1 1

6

A7

A6

1

1

0

0

0

0

5

A7

A6

1

0

1

0

0

0

IR

342

4

A7

A6

1

0

0

0

0

0

3

A7

A6

0

1

1

0

0

0

2

A7

A6

0

1

0

0

0

0

1

A7

A6

0

0

1

0

0

0

0

A7

A6

0

0

0

0

0

0

From this table it is clear that the interrupt requests IR2 and IR4 for an interval of eight is given by: D4 D3 D2 D1 D0 D5 IR2 for an interval of 8 is 0 1 0 0 0 0 IR 4 for an interval of 8 is 1 0 0 0 0 0 Similarly these interrupt requests for an interval of 4 is: D5 IR2 for an interval of 4 is IR 4 for an interval of 4 is

D4 0 1

D3 1 0

D2 0 0

D1 0 0

D0 0 0

Figure 11.8 shows the format of the byte released by the 8259A in response to the third INTA . The bits D7-D0 represent the high order byte of the interrupt vector address (A8-A15 ) of all the interrupts; which are specified in ICW 2.

Fig. 11.8 It may be noted here that the 8259A does not allow each interrupt input to have its own independent address. Instead, a base address can be programmed with four or eight interval spacing as discussed above. For example, if the base address is 0100 H and the interval spacing is four, then eight restart locations will exist as shown in table 11.2. Normally, instructions to jump to the appropriate interrupt service routine would be stored in these locations and the 32 bytes of memory from 0100 H to 011F H referred to as jump table.

343

Table 11.2 Interrupt request Restart address IR0 IR1 IR2 IR3 IR4 IR5 IR6 IR7

0100 H 0104 H 0108 H 010C H 0110 H 0114 H 0118 H 011C H

Example 11.1. For initialization of 8259 the address space available is from E010 H to E040 H. What should be the jump table, if interval spacing between each restart interrupt is four? Solution. The address space available for the restart instruction is from E010 H to E040 H, so the restart address for the first interrupt request will start from E020 H, as the five bits of the starting address must be 00000 (ref. Table 11.1a). The jump table is therefore given in table 11.3. Table 11.3 Interrupt Restart request address IR0 E020 H IR1 E024 H IR2 E028 H IR3 E02C H IR4 E030 H IR5 E034 H IR6 E038 H IR7 E03C H 11.5 INITIALIZATION OF 8259 There are two types of command words in 8259A. These are: •

Initialization Command Words (ICWs)

•

Operation Command Words (OCWs)

11.6 INITIALIZATION COMMAND WORDS (ICWs) There are four command words ICW 1, ICW 2, ICW 3 and ICW 4. The ICW 1 and ICW 2 commands are essential for any 8259A system. However, ICW 3 and ICW 4 commands are optional. The ICW 3 is used if the system has any slave 8259A. The ICW 4 command is used for special operations like special fully nested mode. The microprocessor programs the 8259A by loading the initialization command word (ICWs) and operation command words (OCWs). Each 8259A in the system is first initialized by loading a set of these ICWs in a sequence. The OCWs can be loaded any time after initialization. Initialization Command Word -1 (ICW 1) 344

The format for first initialization command word (ICW 1) is shown in figure 11.9. When a byte is sent to the 8259A with A0 = 0, and D4 = 1, it is interpreted as initialization

Fig. 11.9 command word-1 (ICW 1). The interpretations of the bits of ICW 1 command word are given below: Bit D0

This bit gives the information if the command word ICW 4 is needed. If D0 = 1, ICW 4 is needed. If D0 = 0, ICW 4 is not needed i.e. all functions selected by ICW 4 are cleared. This sets the 8259A in the 8085A mode without AEOI (automatic End of Interrupt) and non-buffered operation; and no ICW 4 would be sent with the initialization.

Bit D1

This bit gives the information if the 8259A is to be used in single or cascaded mode. If D1 = 1, single 8259A is used and no slave 8259A is used. If D1 = 0, 8259A is used in cascaded mode.

Bit D2

This bit gives the information about vector address.

345

If D2 = 1, Interval for vector address is 4. If D2 = 0, Interval for vector address is 8. Bit D3

The bit D3 gives the information about interrupt request inputs whether it is edge triggered or level triggered. If D3 = 1, Interrupt request input is level triggered. If D3 = 0, Interrupt request input is edge triggered.

Bit D4

This bit is 1 for ICW 1, as discussed earlier.

Bits D5 to D7 These bits give the interrupt vector address (for 8085A only) i.e. these are address bits of the CALL instruction. Initialization Command Word -2 (ICW 2) A write command following ICW 1, with A0 = 0, is interpreted as ICW 2. The format for this command word is shown in figure 11.10. This gives information regarding Interrupt Vector Address. The bits D7-D0 represent the high order byte of the interrupt vector address (A8-A15) for 8085 microprocessor. However, T7-T3 represent the vector address for 8086/8088 microprocessors.

Fig. 11.10 Initialization Sequence of 8259A Once ICW1 is loaded, the following initialization procedure is carried out internally: •

The edge sense circuit is reset. Since 8259A interrupts are edge sensitive, they are reset.

•

IMR is cleared.

•

IR7 input is assigned the lowest priority.

•

Slave mode address is set to 7.

•

Special mask mode is cleared and status read is set to IRR.

•

If IC4 = 0, all functions of ICW4 are set to zero. Master/slave bit is ICW 4 is used in the buffered mode only.

346

Example 11.2. Initialize 8259A to interface eight level triggered inputs. The restart address of first interrupt request is E020 H. There is a spacing interval of four byte between each interrupt request. No cascading of 8259A is made. Let the port address is F0 H and F1 H for A0 = 0 and A0 = 1 respectively. Solution. The single 8259A is to be initialized, so initialization command words ICW 1 and ICW 2 are to be written as given below: ICW 1 D7 D6 D5 D4 D3 D2 D1 D0 A7 A6 A5 1 LTM ADI SNGL IC4 0 0 1 1 1 1 1 0 = 3E H In ICW 1, D0 = 0 as no ICW 4 is required; D1 = 1 as single 8259 is used, D2 = 1 as spacing interval of 4 is required, D3 = 1 as these are level triggered inputs, D7 D6 D5 are 001 as 20 H is the address of the first interrupt request (0010 0000). ICW 2 D7 D6 D5 D4 D3 D2 D1 D0 A15 A14 A13 A12 A11 A10 A9 A8 1 1 1 0 0 0 0 0 = E0 H ICW 2 gives the address E0 H (base address) 1110 0000. Program: MVI A, 3E H ; ICW 1 code is loaded to acc. OUT F0 H ; F0 H is the port address for A0 = 0. MVI A, E0 H ; Base address is given by ICW 2. OUT F1 H ; ICW 2 port address for A0 = 1. Initialization Command Word -3 (ICW 3) As already discussed, ICW 1 and ICW 2 are compulsory command words in initialized sequence of 8259A where as ICW 3 and ICW 4 are optional. The command word ICW 3 is read only when cascading of 8259s is used, which is denoted by SNGL (Bit D1) of ICW 1. The ICW 3 is further classified into following two modes: Master Mode ICW 3 Slave Mode ICW 3.

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Fig. 11.11 The ICW 3 in Master and Slave modes are shown in figure 11.11 and 11.12 respectively. Each bit in ICW 3 of master mode is used to specify whether it has a slave 8259 attached to its corresponding interrupt request (IRQ) inputs. Suppose S0 bit is 1. It indicates that 8259 is connected to interrupt request lines IR0. The command word will be loaded to the 8 bit register and the functions of this register are: •

In the master mode (either when SP / EN is high, or in buffered mode when M/S = 1 in ICW 4) a 1 set for each slave in the system. The master then will release byte 1 of the CALL sequence and will enable the corresponding slave to release byte 2 and byte 3 through the cascaded lines.

•

In the slave mode (either when SP / EN is low or if BUF = 1 and M/S = 0 in ICW 4) bits D2-D0 identify the slave. The slave compares its cascade inputs with these bits and if they are equal, bytes 2 and 3 of the CALL sequence are released by it on the data bus.

Fig. 11.12 Initialization Command Word -4 (ICW 4)

This command word is loaded only if IC4 bit of the command word ICW 1 is 1. That is if IC4 = 1 (of ICW 1) then command word -4 (ICW 4) is used otherwise it is 348

neglected. The format of this command word is shown in figure 11.13. The bits of this command word identify the following operations: µPM

This specifies if 8080/8085A or 8086/8088 operation environment is used. If µPM = 1, 8086/8088 microprocessor operation is selected. If µPM = 0, then the 8080/8085A operation is selected.

AEOI

If this bit is 1, then the automatic end of interrupt mode is selected, otherwise normal end of interrupt mode.

M/S

If M/S = 1, then 8259A is master. If M/s = 0, then 8259A is slave. If BUF = 0, then M/S bit is neglected.

Fig. 11.13 BUF

If BUF = 1, then buffered mode is selected. In buffered mode SP / EN acts as enable output and Master/Slave is determined by M/S bit of ISW 4.

SFNM

If SFNM = 1, then fully nested mode is selected. If SFNM = 0, then fully nested mode is not selected.

Figure 11.14 shows the flow chart for the initialization of 8259A.

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Fig. 11.14 11.7 OPERATION COMMAND WORDS (OCWs) Once 8259A is initialized using initialization command words (ICWs), the 8259 is ready to accept interrupt requests. For this purpose, different operation command words (OCWs) are loaded in to operation command word registers. There are three operation command words (OCWs) namely: OCW 1, OCW 2 and OCW 3. Now the discussion will made of the operation command words. Operation Command Word-1 (OCW 1) This operation command word is written to mask or unmask an interrupt request input. The format for OCW 1 is shown in figure 11.15. For this word A0 must be high. In this format it is clear if M = 0, then the particular interrupt request is to be unmasked or enabled, however, if M = 1, it is masked or inhibited.

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Fig. 11.15 For example, in order to enable the interrupts IR6, IR4 and IR1 then the bit pattern of this operation command word will be: D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 1 0 0 1 0 Operation Command Word-2 (OCW 2) A write command with A0 = 0 and D4 D3 = 0 0 is interpreted as OCW 2, which is used to control the Rotate and End of interrupt mode. This is also called End of Interrupt Command. The OCW 2 is mainly used to reset a bit in the in service register (ISR). The format for this operation command word is shown in figure 11.16. R, SL and EOI – bits control the Rotate, End of interrupt modes and the combination of two. The bits L2, L1 and L0 determine the interrupt level acted upon when the SL bit is active. When an interrupt request is acknowledged, the 8259A determines the interrupt of highest priority and sets its corresponding bit in the ISR (in service register). The vector address corresponding to this interrupt is then put out. The bit in ISR remains set until an End of Interrupt (EOI) command through OCW 2 is issued by the CPU. At the end of the service routine, the corresponding bit in ISR is to be reset; otherwise other priority interrupts will not interrupt. The 8259A can respond to the interrupt signal of lower priority once the bit of the current IR bit in ISR is reset. The operation command word-2 (OCW 2) can issue the End of Interrupt (EOI) in the following three forms:

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Fig. 11.16 Non Specific EOI Command In fully nested mode, the highest level in the ISR would necessarily correspond to the last interrupt acknowledged and services. In such a case, a non-specific end of interrupt command (EOI) may be issued by the CPU by the OUT instruction to the 8259A with A0 = 0. For this bit pattern in the format of OCW 2 is given by: D7 D6 D5 D4 D3 D2 D1 D0 0 0 1 0 0 0 0 0 The EOI bit (D5) of the operation command word-2 (OCW 2) is set to 1. This resets the highest priority in service bit of ISR. Specific EOI Command If the fully nested mode is not used, the 8259 may not be able to determine the last interrupt acknowledged. In such case, a specific EOI command will have to be issued by the CPU by the OUT instruction to the 8259A with A0 = 0. For this bit pattern in the format of OCW 2 is given by: D7 D6 D5 D4 D3 D2 D1 D0 0 1 1 0 0 L2 L1 L0 In this bit pattern SL and EOI bits must be set to 1 and the encoded three bit value of the specific bit is written for L2, L1, L0.

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For example, in order to reset the bit 3 of the in service register corresponding to IR3, then the bit pattern of the OCW 2 will be given by: D7 D6 D5 D4 D3 D2 D1 D0 0 1 1 0 1 0 0 0 = 68 H This operation command OCW 2 must be issued twice in case of cascaded mode; one for master and the other for slave. Automatic End of Interrupt (AEOI) If this mode is set, no command is necessary to reset the highest priority in service bit in the ISR. The bit in ISR will be reset automatically at the trailing edge of the third INTA signal sent by the CPU. This AEOI mode can only be used for a master 8259A and not for a slave. The AEOI is actuated by writing ICW 4 with D1 bit to 1. At the time of writing the ICW 4, the A0 line should be 1. Operation Command Word-3 (OCW 3) The format for OCW 3 is shown in figure 11.17. This word is used to read the status of the In Service Register (ISR) and Interrupt Request Register (IRR); and to set or reset the special mask and polled modes.

Fig. 11.17 11.8 INTERRUPT MODES OF 8259A There are following modes of operations of 8259A: Fully Nested Mode Rotating Priority Mode Special Mask Mode Polled Mode 11.8.1 Fully Nested Mode (FNM) The fully nested mode is the general purpose mode in which all interrupt requests are arranged from the highest to lowest priority level. In general, IR0 has the highest

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priority and IR7 has the lowest priority. This is the default mode setting after initialization. The 8259 continues to operate in FNM until the mode is changed by OCWs. As discussed above, when an interrupt request is acknowledged, the 8259 determines the highest priority interrupt and set its corresponding bit in in-service register (ISR). The vector address corresponding to this interrupt is then put out. The bit in ISR remains set until an End of Interrupt (EOI) command through OCW 2 is issued by the CPU. At the end of the service routine, the corresponding bit in ISR is reset using OCW2. 11.8.2 Rotating Priority Mode Though by default the priorities of the inputs are assigned as IR0 as the highest priority and IR7 as the lowest priority. But the priorities may be changed using either by automatic rotation or by specific rotation. Automatic Rotation This mode is used when all the interrupts are assigned equal priority. In this mode, currently executing interrupt is given the lowest priority after completing its service routine. The next interrupt level is assigned the highest priority. For example, the interrupt request IR4 and IR6 are being serviced as it can be read from the status of ISR (figure 11.18). As usual IR4 is assigned highest priority and will be executed first. When the interrupt service routine for IR4 is executed, this bit will be reset after EOI command as discussed earlier. Now in this mode of automatic rotation the interrupt IR4 will have the lowest property and the next interrupt will have the highest priority as shown in figure 11.19.

Fig. 11.18

Fig. 1.19

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Automatic rotation mode on an AEOI is set by loading an OCW 2 with R = 1, SL = 0 and EOI = 0 and is reset by loading an OCW 2 with R = 0, SL = 0, and EOI = 0. Specific Rotation In this, the programmer can change the priority by programming the lowest priority. This mode is set by CPU by issuing an OUT instruction with A0 = 0 and other bit pattern as given below: D7 D6 D5 D4 D3 D2 D1 D0 L1 L0 1 1 0 0 0 L2 The bits D2-Do specify the interrupt level that is to be assigned lowest priority. The specific rotation can be accomplished by using the Rotation of specific EOI in OCW2 as R = 1, SL = 1 and EOI = 1. 11.8.3 Special Mask Mode It may sometimes be desirable to selectively enable lower priority interrupts. Usually, if an EOI command is not given to the 8259A, the in service bit of the last serviced interrupt is not reset. As a result all lower priority interrupts are kept disabled. This special mask mode can be set by making ESMM and SMM bits as 1 in OCW 3. When a mask bit is set in OCW 1, all further interrupts at that level are inhibited; while interrupts on all other levels that are not masked are enabled. It is thus possible to selectively enable interrupts by programming the mask register. This mode can be cleared by loading an OCW 3 with ESSM = 1 and SMM = 0. 11.8.4 Polled Mode In this mode the INT output of 8259A is not used. It is either not connected to the INTR input of 8085A or the system interrupts are disabled by software. The 8259A assign the priorities IR0 through IR7 inputs and provides a status port that can be polled. The status byte has the form as shown in figure 11.20.

Fig. 11.20 11.9 STATUS READ OPERATION OF 8259 The status of the Interrupt Request Register (IRR), the In-Service Register (ISR) and the Interrupt Mask Register (IMR) of the 8259 may be read by using appropriate read command. These read commands are described below: Reading IRR Status Just before reading the IRR (interrupt request register), OCW 3 must be written by making RR (read request) as 1 and RIS (read ISR) as 0. At the time of writing this operation command word, address line A0 and read signal must be 0. Internally OCW 2 and OCW 3 are recognized by sensing the D4 and D3 bits as: D4 D3 0 0 for OCW 2 355

1 0 for OCW 3. After writing the OCW 3, the interrupt request status can be read by using the IN instruction. IN F0 H if F0 H is the port address with A0 = 0. Reading ISR Status For reading ISR status, OCW 3 is initially written with RR = 1 and RIS = 1. The In-service register content can be read using the IN instruction with A0 = 0. IN F0 H if F0 H is the port address with A0 = 0. Reading IMR Status The contents of Interrupt Mask Register (IMR) can be read just by making the A0 = 1. The OCW 3 is not written just before reading. IN F1 H if F1 H is the port address with A0 = 1. Example 11.3. Assume that initialization command words have been written to 8259A (single) having the port address 20 H and 21 H for A0 = 0 and A0 = 1 respectively. Now write proper operation control words for a fully nested priority structure. Mask IR1, IR4 and IR6; enable ISR for a read. What code should be used at the end of interrupt service routine? Solution. The initialization commands have already been written. The operation command words are written as: OCW 1

A0 =1 D6 D5 D4 D3 D2 D1 D0 D7 M7 M6 M5 M4 M3 M2 M1 M0 0 1 0 1 0 0 1 0 = 52 H In this OCW 1, M1, M4 and M6 are 1 as IR1, IR4 and IR6 are masked. For reading ISR status, OCW 3 is initially written with RR = 1 and RIS = 1. OCW 3 D7 D6 D5 D4 D3 D2 D1 D0 0 0 ESMM SMM 1 P RR RIS 0 0 0 0 1 0 1 1 = 0B H In fully nested mode, the highest level in the ISR would necessarily correspond to the last interrupt acknowledged and services. In such a case, a non-specific end of interrupt command (EOI) may be issued by the CPU by the OUT instruction to the 8259A with A0 = 0. For this bit pattern in the format of OCW 2 is given by: D7 D6 D5 D4 D3 D2 D1 D0 0 0 1 0 0 0 0 0 = 20 H The EOI bit (D5) of the operation command word-2 (OCW 2) is set to 1. This resets the highest priority in service bit of ISR. PROGRAM: MVI A, 52 H ; OCW 1 is loaded to accumulator. OUT 21 H ; 21 H is the port address for A0 = 1. MVI A, 0B H ; OCW 3 is loaded to accumulator to enable the ISR for read. OUT 20 H ; 20 H is the port address for A0 = 0, IN 20 H ; Read ISR

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Each interrupt service routine must end by giving the non-specific EOI command which resets in service bit (ISR bit). MVI A, 20 H OUT 20 H RET Example 11.4. Write Initializing command word to program 8259A (single) with port addresses C0 H and C1 H for A0 = 0 and A0 = 1 respectively. Let the starting address of the interrupt request is 7000 H with interval spacing of 4. The interrupts are edge triggered. Interrupts 1 and 3 are masked. Solution. The single 8259A is to be initialized, so initialization command words ICW 1 and ICW 2 are to be written as given below: ICW 1 D7 D6 D5 D4 D3 D2 D1 D0 A7 A6 A5 1 LTM ADI SNGL IC4 0 0 0 1 0 1 1 0 = 16 H In ICW 1, D0 = 0 as no ICW 4 is required; D1 = 1 as single 8259 is used, D2 = 1 as spacing interval of 4 is required, D3 = 0 as these are edge triggered inputs, D7 D6 D5 are 000 as 00 H is the address of the first interrupt request (0000 0000). ICW 2 D7 D6 D5 D4 D3 D2 D1 D0 A15 A14 A13 A12 A11 A10 A9 A8 1 1 1 0 0 0 0 0 = E0 H ICW 2 gives the address 70 H (base address) 0111 0000. The operation command word is written as: OCW 1

A0 =1 D7 D6 D5 D4 D3 D2 D1 D0 M7 M6 M5 M4 M3 M2 M1 M0 0 0 0 0 1 0 1 0 = 0A H In this OCW 1, M1and M3 are 1 as IR1 and IR3 are masked. Program: MVI A, 16 H ; ICW 1 code is loaded to acc. OUT C0 H ; C0 H is the port address for A0 = 0. MVI A, 70 H ; Base address is given by ICW 2. OUT C1 H ; ICW 2 port address for A0 = 1. MVI A, 0A H ; OCW 1 for masking. OUT C1 H ; Port address for A0 = 1.

Example 11.5. After initializing 8259A with port addresses C0 H and C1 H for A0 = 0 and A0 = 1 respectively. Give the instruction sequence to read ISR status and IMR status. Solution. After initialization of 8259A , OCW 3 is written with RR = 1 and RIS = 1, to enable reading of ISR status (this is necessary for reading the status of ISR). So OCW 3 is given as: OCW 3 357

D7 D6 D5 D4 D3 D2 D1 D0 0 0 ESMM SMM 1 P RR RIS 0 0 0 0 1 0 1 1 = 0B H The instruction sequence is then given for the reading the status of ISR and IMR as: Program: MVI

; OCW 3 code is loaded to acc. to enable the reading of ISR status. OUT C0 H ; C0 H is the port address for A0 = 0. IN C0 H ; Read the status of ISR. IN C1 H ; Read the status of IMR. Example 11.6. An interrupt service routine written for 8259A having port addresses F0 H and F1 H, ends with the instruction sequence given as: MVI A, 22 H OUT F0 H RET How does the 8259A interpret these instructions? Solution. First instruction MVI A, 22 H will show the bit format for OCW 2 is given by: D7 D6 D5 D4 D3 D2 D1 D0 0 0 1 0 0 0 1 0 This resets the IR2 in service bit of ISR. This is a non-specific end of interrupt command (EOI) may be issued by the CPU by the OUT instruction to the 8259A with A0 = 0.

1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11.

12.

A, 0B H

PROBLEMS Draw the block diagram of programmable interrupt controller (PIC) 8259A and discuss its various blocks. Describe how the interfacing of 8259A with 8085A microprocessor is done. Discuss how the cascading of 8259A is carried out. How many 8259s may be cascaded? What is the function of master 8259A in the cascading mode? Discuss how initialization of 8259 is carried out. Describe various Initialization command words in 8259A (PIC). What do you understand by operation command words in 8259A? Discuss any one command word. Explain the various interrupt modes of 8259A. Discuss status read operation of 8259A. Explain the vectoring data format of 8259A (PIC). Discuss Rotating Priority mode of operation of 8259A. Initialize 8259A to interface eight edge triggered inputs. The restart address of first interrupt request is 1020 H. There is a spacing interval of four byte between each interrupt request. No cascading of 8259A is made. Let the port address is C0 H and C1 H for A0 = 0 and A0 = 1 respectively. Assume that initialization command words have been written to 8259A(single) having the port address F0 H and F1 H for A0 = 0 and A0 = 1 respectively. Now

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13.

14. 15. 16.

write proper operation control words for a fully nested priority structure. Mask IR2, IR3 and IR5; enable ISR for a read. What code should be used at the end of interrupt service routine? Write Initializing command word to program 8259A (single) with port addresses 20 H and 21 H for A0 = 0 and A0 = 1 respectively. Let the starting address of the interrupt request is 8000 H with interval spacing of 4. The interrupts are edge triggered. Interrupts 0 and 4 are masked. Write a non-specific end of interrupt command (EOI) to reset IR3 in service bit of ISR4. Assume the port addresses 20 H and 21 H for 8259. After initializing 8259A with port addresses F0 H and F1 H for A0 = 0 and A0 = 1 respectively. Give the instruction sequence to read ISR status and IMR status. Explain the following initialization instructions: MVI A, 3E H ; ICW 1 OUT 80 H ; Initialize 8259A MVI A, E0 H ; ICW 2 OUT 81 H ; Initialize 8259A

_________

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12 Direct Memory Access Controller: 8257 It has already been discussed in an earlier chapter of this book, that the Direct Memory Access (DMA) is the efficient way of transferring the data from the memory to the I/O devices or vice versa without involving the CPU. In DMA operation, the CPU relinquishes the control over the data bus and address bus, so that these can be used for transfer of data between the memory and I/O devices directly. For the data transfer using DMA process, a request to the microprocessor by the I/O device is sent and on receipt of such request, the microprocessor relinquishes the address and data buses and informs the I/O devices of the situation by sending Acknowledge signal. However, in the usual method of data transfer between the I/O devices and the memory, it involves the microprocessor. Each byte is routed through the accumulator, as a result of which it takes lot of time for transferring a large amount of data. For the purpose of DMA operation, a DMA controller is necessary to interface the peripheral to the system. Intel 8257 is a 4chennel programmable DMA controller used with 8085 and other microprocessors for this mode. In this chapter the details of the DMA controller 8257 will be discussed. 12.1 BLOCK DIAGRAM OF 8257 The 8257 Programmable DMA controller is available in the form of IC dual in line package. It consists of 40 pins and requires +5 volt d.c. supply for its operation. The 8257 enables to interface up to four I/O devices to the microprocessor for the data transfer between the memory and the I/O devices or vice versa using DMA. It has forum DMA channels. Each channel consists of two 16 bit registers. One of these registers holds the address to be used in the next DMA cycle. The other register holds, in the least significant 14 bits, the total number of bytes to be transferred between the memory and peripherals. The two most significant bits of this register are set to indicate the operation to be performed by the device on that channel. A total of 16384 (214 = 16 K) bytes of data may directly be transferred under DMA control without any intervention of the microprocessor. Figure 12.1 shows the pin diagram of 8257. The pin names of this IC are given below:

D0-D7 A0-A7 I/OR I/OW MEMR MEM W CLK

Data bus Address bus I/O Read I/O Write Memory Read Memory Write Clock Input

HLDA AEN ADSTB TC MARK DRQ0-DRQ3 DACK 0 - DACK 3

RESET READY HRQ

RESET Input Ready HOLD Request

CS VCC GND

HOLD Acknowledge Address Enable Address Strobe Terminal Count Modulo 128 MARK DMA Request Input DMA Acknowledge OUT Chip Select +5 V Ground

Fig. 12.1 The internal block diagram and schematic diagram of 8257, DMA Controller (DMAC) are shown in figures 12.2 and 12.3 respectively. It contains the following blocks:

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DMA Channels Data Bus Buffer Read/ Write Logic Control Logic Mode Set Register Status Word Register

Fig. 12.2

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Fig. 12.3 12.1.1 DMA Channels The 8257 provides 4 channels which can be connected to four separate I/O devices. These channels are designated as Channel 0 (CH-0), Channel 1 (CH-1), Channel 2 (CH-2) and Channel 4 (CH-4). Each of these channels has two 16-bit registers: DMA Address Register Terminal Count Register. DMA Address Register contains the memory address from where the data transfer should begin. This address is loaded by the CPU. The terminal count register is used to store the number of bytes to be transferred. In this 16 bit register, the least significant 14 bits are used to store the number of bytes to be transferred. In this way one DMA operation can transfer to a maximum of 16 K bytes. The most significant two bits of the terminal register represent the operation to be performed by the device. The operations to be performed are Write, Read and Verify. Figure 12.4 shows the format of the terminal count register of a DMA channel.

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Fig. 12.4 During DMA write operation, the data is transferred from the peripheral to memory. During DMA read operation, the data is transferred from memory to peripheral. DMA verify operation does not actually involve the transfer of data. Each channel has two signals: DMA REQUEST Signal and DMA ACKNOWLEDGE Signal. DMA REQUEST Signals (DRQ0 – DRQ3): There are four DMA request signals (DRQ0 – DRQ3) in the 8257 connected one with each channel. Each channel accepts a DMA request through this pin from the peripheral. The DMA controller 8257 has priority facility. The channel 0 (CH 0) has the highest priority and the channel 3 (CH 3) has the lowest priority. As per the priority, a request is generated by the peripheral by making corresponding DRQ line high and holding it high until DMA operation is over. DMA ACKNOWLEDGE Signals ( DACK 0 - DACK 3 ):

Likewise the DMA request signals, 8257 has the four DMA acknowledge signals ( DACK 0 - DACK 3 ) connected one with each channel. As discussed above, each channel accept a DMA request through it DRQ line from the peripheral. After the receipt of the request channel issues an acknowledge signal through DACK output of that channel. It is an active low signal and signifies that the request to be serviced for a DMA cycle is accepted. This signal is made high on completion of the transfer.

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12.1.2 Data Bus Buffer This three state, bidirectional eight bit buffer (D0-D7) interfaces the 8257 to the system data bus. When the CPU has the control over the system buses (Slave Mode), the D0-D7 pins of the 8257 are used as input pins. The eight bits of data for a DMA address register and terminal count register or the mode set register are received on the data bus. In this slave mode, the CPU can also read eight bits of data at a time from the 16-bit DMA address and terminal count register or from the eight bit status register. However, in the master mode (for DMA cycle, when the CPU relinquishes the control over the control and data buses), the D0-D7 pins are used for different purpose. At the beginning of each DMA cycle, most significant bits of DMA address register are put on these pins which are further latched to an external chip 8212 used as latch. These latched values are put on A8-A15 of the system address bus. The D0-D7 bus is then released to handle the memory data transfer during the remainder of the DMA cycle. 12.1.3 Read/ Write Logic When the CPU is programming or reading one of the registers of 8257 (i.e. when the 8257 is in slave mode), the Read/ Write logic accepts the I/ O Read ( I/OR ) or I/O Write ( I/OW ) signal. It then decodes the least significant four address bits (A0-A3), and writes the contents of the data bus into the addressed register (if I/OW is active) or places the contents of the addressed register onto the data bus (if I/OR is active). During DMA cycle (i.e. when the 8257 is in master mode), the Read/ Write logic generates the I/O Read and Memory Write cycle (DMA Write cycle) and generates the Memory Read and I/O Write Cycle (DMA Read cycle).

I/OR (I/O Read) This is an active low, bidirectional three-state pin. In the slave mode, it is an input signal which allows the 8-bit status register or the upper/lower byte of a 16-bit DMA address register or terminal count register to be read. In the master mode, I/OR is a control output, which is used to access data from a peripheral during the DMA write cycle.

I/OW (I/O Write) This is also an active low, bidirectional three-state pin. In the slave mode, it is an input signal which allows the contents of the data bus to be loaded into the 8-bit mode set register or the upper/lower byte of a 16-bit DMA address register or terminal count register. In the master mode, I/OW signal is a control output which allows data to be output to a peripheral during a DMA read cycle. CLK (Clock input) This input is generally connected to an external clock or to the 8085A CLK output. RESET (Reset) This is an active high asynchronous input which disables all DMA channels and clears the mode set register. It also tri states all the control lines. 365

CS (Chip Select) This is an active low input which enables the I/O Read or I/O write input when the 8257 is being read or programmed in the slave mode. In the master mode, CS input is automatically disabled. This is done to prevent the 8257 from selecting itself when it puts out DMA addresses on the address bus. A0-A3 (Address lines) These least significant four address lines are bidirectional. In the slave mode, they are inputs which select one of the registers to be read or programmed. In the master mode, they are outputs which constitute the least significant four bits of the 16-bit address generated by the 8257. 12.1.4 Control Logic This block controls the sequence of operations during all DMA cycles by generating the appropriate control signals and the 16-bit address that specifies the memory location to be accessed. The pins associated with the control logic are described below.

A4-A7 (Address lines) These four address lines are the three state output lines. Bits 4-7 of the DMA address register are put on these address lines during the DMA cycles. So, the A0-A7 of 8257 carry the least significant byte of DMA address during the execution of a DMA cycle. READY This ready input signal can be used by the devices with slow access time in order to insert the wait states during DMA transfer. It has similar function to the Ready input pin of 8085. HRQ (Hold Request) This output requests control of the system bus. In systems with only one 8257, this signal will be normally applied the HOLD input of the CPU. HRQ must confirm to specified setup and hold times. HLDA (Hold Acknowledge) This is an input from the CPU that informs the 8257 that it has relinquished control of the buses and 8257 may take over the control. MEMR (Memory Read) This is a three-state active low output which is used to read data from the addressed memory location during DMA Read cycles.

MEMW (Memory Write) This is also three state active low output which is used to write data into the addressed memory location during DMA Write cycles.

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ADSTB (Address Strobe) This is an active high signal which is generated at the beginning of each DMA cycle and has a similar function as that of ALE pin of 8085A. AEN (Address Enable) This is an output pin used to float the system data bus and the system control bus. It may also be used to float the system address bus. It may further be used to isolate the 8257 data bus from the system data bus to facilitate the transfer of the 8-bit most significant DMA address bits over the 8257 data I/O pins. When the 8257 is used in an I/O device structure, this AEN output is used to disable the selection of an I/O device when the DMA address is on the address bus. The I/O device selection should be determined by the DMA acknowledge output for the four channels. TC (Terminal Count) This is an active high output. When this pin is high it indicates to the currently selected peripheral that the present DMA cycle is the last cycle for this data block. This output goes high, when the contents of the terminal count register of the selected channel are equal to zero. By programming the mode word, a channel can automatically be disabled after its last DMA cycle. MARK (Modulo 128 Mark) This active high output notifies the selected peripheral that the current DMA cycle is the 128th cycle since the previous mark output. Mark always occurs at 128 (and all multiples of 128) cycles from the end of the data block. Only if the total umber of DMA cycles (n) is evenly divisible by 128, mark will occur at 128 cycles from the beginning of the data block. 12.1.5 Mode Set Register The format of Mode Set Register of 8257 is shown in figure 12.5. The control word in the mode set register enables or disables channels and determines other functions. The mode set register can be accessed only for write operation. The various bits in this mode set register enable each of the four DMA channels and four different options for the 8257. The mode set register is cleared by the RESET input, thus disabling all options, inhibiting all channels. This mode set register is also used for programming the 8257 in the following options: • Rotating Priority • Extended Write • TC Stop • Auto Load

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Fig. 12.5 Rotating Priority The bit 4 (D4) of the Mode Set Register enables to set the rotating priority mode of the 8257. In the rotating priority mode, the priority of the channels has a circular sequence as shown in figure 12.6. After each DMA cycle the priority of channels has circular sequence. After each DMA cycle, the priority of each channel changes. The channel which had just been serviced will have the lowest priority (Figure 12.7).

Fig. 12.6 If the rotating priority bit is not set (D4 = 0), each DMA channel has a fixed priority. In the fixed priority mode, channel 0 has the highest priority and the channel 3 has the lowest priority. If the rotating priority bit D4 is set to 1, the priority of each channel changes after each DMA cycle (not each DMA request). Each channel moves up to the next highest priority assignment, while the channel which has just been serviced moves to the lowest priority assignment.

368

Fig. 12.7 Extended Write The bit 5 (D5) of the mode set register is used for extended write option. The data transfer with in microcomputer systems takes place asynchronously which allow the use of various types of memory and I/O devices with different access times. If the device can not be accessed within the specified amount of time, it returns a ‘Not Ready’ signal on the READY input of the 8257 due to which one or more wait states are inserted in the internal sequencing. Some devices are fast enough to be accessed without the use of wait states. But if they generate their Ready response with the leading edge of the I/OW or MEMW signal (which generally occurs late in transfer sequence), they would normally cause the 8257 to enter a wait state because it does not receive Ready in time. For systems with these types of devices, the extended write operation provides alternative timing for the I/O and memory write signals which allows the devices to return on early Ready and prevents the unnecessary occurrence of wait states in the 8257. TC Stop If the TC stop bit (D6) of the mode set register is set, a channel is disabled (i.e. its enable bit is reset) after the terminal count (TC) output goes high, thus automatically preventing further DMA operation on that channel. To continue or begin another DMA operation, the enable bit of that channel must be reprogrammed. If the TC is not set, the occurrence of TC bit output has no effect on the channels enable bits. In that case, it will be responsibility of the peripheral to cease DMA requests in order to terminate a DMA operation. Auto Load Bit D7 of the mode set register enables Auto Load mode. In some cases, it becomes necessary to perform DMA operation repeatedly. In case of a CRT monitor, the data has to repeatedly send to the monitor and this process is called refreshing. With the auto load option, the DMA controller permits such repetitive operation. This bit permits channel 2 to be used for repeat block operation. If the auto load mode is set (D7 = 1), the initial parameters of channel 2 are automatically copied onto channel 3. The channel 2 is programmed with the initial parameters for the first DMA block. When the DMA block of channel 2 is completed, the parameters stored in channel 3 are copied onto channel 2. The channel 2 is then serviced again with the same parameters for repetitive DMA operations. For chaining operation, channel 3 is loaded with a different set of parameters

369

after channel 2 is loaded; the new parameters are copied onto channel 2 during the update cycle and channel 2 is serviced with a new set of parameters. 12.1.6 Status Word Register The eight bit status register is shown in figure 12.8. The status register can be read for the status of the terminal counts of the four channels. It also contains the update flag. The count bits (D0-D4) of the four channels are set when the terminal count output is high for that channel. The TC bits go low when the status word is read or when the 8257 receives a Reset input. The update flag is reset when: 8257 is reset or Auto load option in the mode set register is disabled or Update cycle gets completed.

Fig.12.8 12.2 PROGRAMMING OF 8257 As discussed above, there are four pairs of channel registers in 8257; each pair consisting of a 16-bit Address Register and 16 bit Terminal Count Register i.e. one pair for each channel. The 8257 also includes two general registers one 8-bit Mode Set Register and other 8-bit Status Register. These various registers are accessed with the help of four input lines (A0-A3) and an internal F/L flip-flop (First/ Last Flip-flop). The address bit 3 (A3) signifies whether a channel register or the mode set register is being accessed. If A3 = 0, then channel register is accessed and if A3 = 1, then the mode set register is accessed. The other three address bits (A0-A2) specify which register is to be accessed. When these bits (A0-A2) are all zero, the mode set register or status register is being accessed. The 8257 distinguishes between the mode set register (which is write only operation) and the status operation (which is read only operation) by the I / OW and I / OR inputs respectively. Table 12.1 illustrates the status of A3 and the control inputs for accessing the various registers. For channel registers, A2 A1 specify one of the four channels i.e. for channel 0, it is 00, for channel 1 it is 01, for channel 2 it 01 and for channel 3 it is 11. The bit A0 specifies whether channel register or terminal count register 370

is to be accessed. If A0 = 0, channel register is accessed and if A0 = 1, terminal count register is accessed. The F/L flip-flop is reset by reset input. This flip-flop toggles for access of the 8257 registers and determines whether upper or lower order byte of a particular register is accessed. It requires that the reading of the address registers or the terminal count registers should be done in pairs; the lower order byte should be accessed first. The addressing of the registers is shown in table 12.2. Table 12.1 I / OW

I / OR

A3

0

1

0

0

1

0

0

Program Mode Set Register

0

0

1

1

Read Status Register

0

1

0

0

CONTROL INPUT

CS

Program Half of a Channel Register

0

Read Half of a Channel Register

Table 12.2

ADDRESS INPUTS A3 A2 A1 A0

State of FF CS F/L 0 0 1 0

Register Accessed

0 0

0 0

0 0

0 0

0 0

0 0

0 0

1 1

0 1

0 0

LOB of Counts of Terminal Count Register CH 0 HOB of Counts of Terminal Count Register CH 0

0 0

0 0

1 1

0 0

0 1

0 0

LOB of DMA address CH 1 HOB of DMA address CH 1

0 0

0 0

1 1

1 1

0 1

0 0

LOB of Counts of Terminal Count Register CH 1 HOB of Counts of Terminal Count Register CH 1

0 0

1 1

0 0

0 0

0 1

0 0

LOB of DMA address CH 2 HOB of DMA address CH 2

0 0

1 1

0 0

1 1

0 1

0 0

LOB of Counts of Terminal Count Register CH 2 HOB of Counts of Terminal Count Register CH 2

0

1

1

0

0

0

LOB of DMA address CH 3

LOB of DMA address CH 0 HOB of DMA address CH 0

371

0

1

1

0

1

0

HOB of DMA address CH 3

0 0

1 1

1 1

1 1

0 1

0 0

LOB of Counts of Terminal Count Register CH 3 HOB of Counts of Terminal Count Register CH 3

1 1

0 0

0 0

0 0

0 0

0 0

Mode Set Register (Write Only) Status Register (Read Only)

HOB – High order byte LOB – Low order byte The microprocessor can either read data from or write data into DMA address register and the terminal count register of each channel of 8257. The status register can be read and mode set register may be programmed. All these operations have been discussed above and carried out during the slave mode of 8257. If the address decoder circuit for the chip select terminal of DMA controller 8257 shown in figure 12.9 is used, it will give the addresses of DMA registers and terminal count registers of all the four channels along with the address of the mode set registers. These addresses are given in table 12.3.

Fig. 12.9

372

Table 12.3 A7

A6

A5

A4

A3

A2

A1

A0

Address

0 0

1 1

0 0

0 0

0 0

0 0

0 0

0 1

70 H 71 H

DMA address CH 0 TC address CH 0

0 0

1 1

0 0

0 0

0 0

0 0

1 1

0 1

72 H 73 H

DMA address CH 1 TC address CH 1

0 0

1 1

0 0

0 0

0 0

1 1

0 0

0 1

74 H 75 H

DMA address CH 2 TC address CH 2

0 0

1 1

0 0

0 0

0 0

1 1

1 1

0 1

76 H 77 H

DMA address CH 3 TC address CH 3

0

1

0

0

1

0

0

0

78 H

Mode Set Reg addr.

The various registers have to be first initialized and then DMA operation will be started. The steps, to be followed for the DMA operation of 8257 (Master Mode), after its initialization, are given as: • The I/O device sends a DMA request signal (DRQ) when it is ready to for the data transfer. • The 8257 sends Hold Request signal (HRQ) high to the processor. It then enables the particular channel. • In response to HRQ signal, the processor will relinquishes the system busses in the next cycle and will send a Hold Acknowledge (HLDA) signal to the 8257. • In response to this HLDA signal from the microprocessor, the DMA controller will generate ( DACK ) DMA acknowledge signal (active low) through its Control Logic block as an acknowledgement to the requesting peripheral. At the same time the 8257 enables the Address Enable (AEN) signal which disables systems address lines (A0-A7). These address lines becomes the output lines. The low order byte of the memory location is placed of these lines. The address strobe (ADSTB) signal goes high when AEN is high and places higher byte of the memory location generated by 8212 on the address bus A15-A8. • The data transfer continues till the terminal count is reached. 12.3 DMA INTERFACING CIRCUIT Figure 12.10 shows the interfacing circuit of DMA controller 8257. In this circuit

373

Fig. 12.10

374

8212 is used to de-multiplex the 8085 bus to generate the low order address bus (A7-A0). The 8257 has eight address lines, but requires sixteen address lines to address a memory location. The additional eight lines are generated by using the signal ADSTB to strobe a high order memory address into the 8212 from the data bus. This IC is not related to 8085 not to the DMA controller 8257, but only DS1 is controlled by AEN signal of 8257. The IC 74LS257 is a multiplexer which is used to generate control signals. The OE terminal of this multiplexer is also controlled by AEN. The AEN output signal is used to disable (float) the system bus and control bus. This signal is also necessary to switch the 8257 from the slave mode to the master mode. The port addresses of the registers of 8257 are used as discussed above and circuit for the same is given in figure 12.9. The port addressed may be chosen as desired. The second 8212 connected to the DMA controller accepts the data during the DMA operation. Example 12.1 Initialize 8257 DMA controller to transfer 2K bytes of data stored in memory locations starting at 2101 H to floppy disk connected to the channel 1 of 8257. Assume that the address of the Mode Set Register is 78 H. The addresses of DMA address register for channel 1 and the Terminal Count Register are 72 H and 73 H respectively. Solution. The format for Mode Set register is given below: D7 D6 D5 D4 D3 D1 D0 0 1 0 0 0 1 0 = 42 H

Enable TC stop Format for Terminal Count Register is given below: D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 1 0 0 0 0 1 1 1 1 1

Enable CH 1

D1 D0 1 1 = 87FF H D15 and D14 as 10 indicate it is memory read operation and D10 to D0 as 11111111111 represents 2 K bytes of data to be transferred to the floppy. For the initialization of 8257, following steps are to be followed: Load mode word in the Mode Set Register. Load counts to the terminal count register first LS byte and then MS byte. Load starting address of the memory location, from where the data is to be transferred to the floppy disk, to the DMA address register. The initialization program is therefore given as: MVI A, 42 H OUT 78 H MVI A, FF H OUT 73 H

D5 D4 1 1

D3 1

D2 1

; Load mode word in the Mode Set Register. ; Address of the Mode Set Register. ; Load LS byte of the count in the terminal count register. ; Address of TC register.

375

MVI A, 87 H

; Load MS byte of the count in the terminal count register. OUT 73 H ; Address of TC register. MVI A, 00 H ; Load the LS byte of the starting address of the memory location from where the data is to be transferred. OUT 72 H ; Address of the DMA address register. MVI A, 21 H ; Load the MS byte of the starting address of the memory location. OUT 72 H ; Address of the DMA address register. Example 12.2 Initialize 8257 DMA controller to transfer 512 bytes of data from a peripheral to memory locations starting at 3000 H through channel 0. Assume that the address of the Mode Set Register is 28 H. Assume the addresses of DMA address register for channel 0 and the Terminal Count Register are 20 H and 21 H respectively. Solution. The format for Mode Set register is given below: D7 D6 D5 D4 D3 D1 D0 0 1 0 0 0 0 1 = 41 H Enable TC stop Format for Terminal Count Register is given below: D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 0 1 0 0 0 0 0 1 1 1

Enable CH 0

D1 D0 1 1 = 41FF H D15 and D14 as 01 indicate it is memory write operation and D8 to D0 as 111111111 represents 512 bytes of data to be transferred. The initialization program is therefore given as: MVI A, 41 H ; Load mode word in the Mode Set Register. OUT 28 H ; Address of the Mode Set Register. MVI A, FF H ; Load LS byte of the count in the terminal count register. OUT 21 H ; Address of TC register. MVI A, 41 H ; Load MS byte of the count in the terminal count register. OUT 21 H ; Address of TC register. MVI A, 00 H ; Load the LS byte of the starting address of the memory location from where the data is to be transferred. OUT 20 H ; Address of the DMA address register. MVI A, 30 H ; Load the MS byte of the starting address of the memory location. 376

D5 D4 1 1

D3 1

D2 1

OUT 20 H ; Address of the DMA address register. Example 12.3 An I/O device which is associated with channel 2 of 8257 DMA controller is to be periodically refreshed with 4K bytes of data starting from 2200 H locations. Write the initialization routine for the DMA controller to be operated with auto-load and extended write operations. The addresses of DMA registers and terminal count registers of all the four channels along with the address of the mode set registers are given in table 12.3. Solution. The format for Mode Set register is given below: D7 D6 D5 D6 D5 D4 D3 D1 D0 1 0 1 0 0 1 1 0 0 = A6 H D7 = 1 indicates that the auto load enabled, and D5 = 1 indicates the extended write enabled. D4 and D3 = 11, indicate that the channel 2 and channel 3 are enabled, which are needed for the auto load and extended write mode. Format for Terminal Count Register is given below: D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 = 8FFF H D15 and D14 as 10 indicate it is memory read operation and D11 to D0 as 111111111111 represents 4096 (4K) bytes of data to be transferred. In this case the starting address of the memory location is to be loaded to both DMA address registers of both channel 2 and channel 3 for auto load and extended write mode. The initialization program is therefore given as: MVI A, A6 H ; Load mode word in the Mode Set Register. OUT 78 H ; Address of the Mode Set Register. MVI A, FF H ; Load LS byte of the count in the terminal count register of channel 2. OUT 75 H ; Address of TC register of channel 2. MVI A, 8F H ; Load MS byte of the count in the terminal count register of channel 2. OUT 75 H ; Address of TC register of channel 2. MVI A, FF H ; Load MS byte of the count in the terminal count register of channel 3. OUT 77 H ; Address of TC register of channel 3. MVI A, 8F H ; Load MS byte of the count in the terminal count register of channel 3. OUT 77 H ; Address of TC register of channel 3. MVI A, 00 H ; Load the LS byte of the starting address of the memory location.

377

OUT 74 H MVI A, 22 H OUT 74 H MVI A, 00 H OUT 76 H MVI A, 22 H OUT 76 H

; Address of the DMA address register channel 2. ; Load the MS byte of the starting address of the memory location. ; Address of the DMA address register ch.2. ; Load the LS byte of the starting address of the memory location. ; Address of the DMA address register channel 3. ; Load the MS byte of the starting address of the memory location. ; Address of the DMA address register ch.3. PROBLEMS

1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14.

What do you understand by Direct Memory Access? What is the use of DMA controller for the data transfer from memory to I/O devices or vice-versa? Draw the block diagram of 8257 DMA controller. Discuss the functions of it blocks. How many I/O devices can be connected with the 8257? How many register are there in 8257? Discuss these registers. Give the format of terminal count register. Discuss the functions of the bits of TC register. What is the function of the Read/ Write Logic block of the 8257 DMA controller? Mention the function of each signal of the control logic block of 8257 DMA controller. What is the function of Mode Set Register of the 8257? How 8257 is programmed in Auto Load option? How 8257 is programmed in Rotating Priority option? Give and discuss the format of the Status Word Register of 8257. How the programming of 8257 DMA controller is done? Give the address decoder circuit for addresses of various registers as C0 H to C8 H. The decoder circuit enables chip select terminal ( CS ) of the 8257. What steps are carried out for initialization of 8257? Draw and discuss the interfacing circuit of 8257 with 8085A microprocessor. Initialize 8257 DMA controller to transfer 4K bytes of data stored in memory locations starting at 2501 H to an output device connected to the channel 2 of 8257. Assume that the address of the Mode Set Register is C8 H. The addresses of DMA address register for channel 2 and the Terminal Count Register are C4 H and C5 H respectively.

378

15.

16.

17.

18.

Initialize 8257 DMA controller to transfer 200 bytes of data stored in memory locations starting at 2000 H to an output device connected to the channel 0 of 8257. Assume that the address of the Mode Set Register is 28 H. The addresses of DMA address register for channel 0 and the Terminal Count Register are 20 H and 21 H respectively. The DMA controller 8257 should be initialized as follows: DMA channel 2 must be enabled and terminal count stop bit is to be enabled. 2500 H must be written in DMA address register channel 2. 500 (decimal) must be written in Terminal counter of channel 2 and D14 and D15 are set for memory read operation. Assume the address of the DMA address register for channel 2 is 94 H and the terminal count is 95 H; and the address of the mode set register is 98 H. Initialize 8257 DMA controller to transfer 8K bytes of data from a peripheral to memory locations starting at 21FF H through channel 1. Assume that the address of the Mode Set Register is 98 H. Assume the addresses of DMA address register for channel 1 and the Terminal Count Register are 92 H and 93 H respectively. An I/O device which is associated with channel 2 of 8257 DMA controller is to be periodically refreshed with 1K bytes of data starting from 2500 H locations. Write the initialization routine for the DMA controller to be operated with auto-load and extended write operations. The addresses of DMA registers and terminal count registers of all the four channels are C0 H to C7 H; and the address of the mode set register is CH H.

__________

379

13 Interfacing Data converters: A/D and D/A Converters Sometimes the information available for processing in microprocessor based system is in digital form while in most of the cases it is available in analog form. For example, the outputs of digital voltmeter, digital frequency meter, digital clock and calculators etc. are available in digital form but most physical quantities such as temperature, pressure, light, voltage and current etc. gives information in analog form. It is often necessary to convert information in one form to another form for the purpose of interfacing with the system. For example, to design the microprocessor base temperature controller, the temperature of the device obtained from the transducer such as thermocouple or thermister is first converted to the digital form using D/A converter then interfaced with the microprocessor. Similarly, for plotting the output of a system on a curve plotter or X-Y recorder, the digital output is first converted to analog output with the help of digital to analog converter, the output of which drives a servomotor. So analog to digital (A/D) converters or digital to analog (D/A) converters are the interfacing devices with the system. In this chapter various types of A/D and D/A converters and their interfacing with the microprocessor will be discussed. 13.1 DIGITAL TO ANALOG CONVERTER Digital to Analog (D/A) converter converts the digital information into analog form. The input may be of n-bit long having different voltage levels. So in the D/A converters, some method is to be used which can convert this voltage level of n-bits to its equivalent analog form. This can be accomplished by using different resistive networks. Following two types of resistive networks are basically used for this purpose: 1. Resistive Divider Network or weighted resistor network 2. Binary Ladder Network or R-2R network The converter which comprises the resistive divider network is known as Resistive Divider D/A converter and the D/A converter which comprises the binary ladder network is known as Binary Ladder D/A converter. These converters will now be discussed. 13.1.1 Resistive Divider D/A converter As discussed above, the resistive divider D/A converter consists of a resistive divider network, so before discussing the complete circuit diagram of a resistive divider D/A converter, it is better to understand the working of resistive divider network. The resistive divider network changes each of the n-bit digital level into its equivalent analog

output. The discussion will now be made for the method of converting the n-bit digital input to its equivalent analog signal. A weight is assigned to each bit of n-bit digital input in such a way that the sum of weight must be equal to 1. In general, the binary weight 1 assigned to LSB in an n-bit digital input is n . The weights assigned to 2nd LSB, 3rd 2 −1 LSB, 4th LSB and so on are obtained by multiplying the weights of LSB to 21(=2), 22 (=4), 23 (=8)…. respectively. For instance, weights assigned to different bits of 4-bit binary input b3 b2 b1 b0 are: 20 1 Weight assigned to LSB (b0 bit) is = 4 2 − 1 15 Weight assigned to 2nd LSB (b1 bit) is

21 2 = 4 2 − 1 15

Weight assigned to 3rd LSB (b2 bit) is

22 4 = 4 2 − 1 15

Weight assigned to MSB (b3 bit) is

23 8 = 4 2 − 1 15

The sum of weights assigned to each bit of 4-bit digital input is 1 as 1 + 2 + 4 + 8 = 1 . 15

15 15

15

In a four bit binary system there will be 16 different possible input combinations, corresponding to which the analog signal will be obtained if it is assumed that a certain reference voltage (VREF) is applied whenever there is a 1 in binary bit. In a 4 bit digital system if VREF =15 volts, the analog voltage available for each combination of binary input should be as given in table 13.1. Table 13.1 b2 b1 b0 Weight Analog Voltage b3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

(0/15)VREF = 0 Volt (1/15) VREF = 1 Volt (2/15) VREF = 2 Volt (3/15) VREF = 3 Volt (4/15) VREF = 4 Volt (5/15) VREF = 5 Volt (6/15) VREF = 6 Volt (7/15) VREF = 7 Volt (8/15) VREF = 8 Volt (9/15) VREF = 9 Volt (10/15) VREF = 10 Volt (11/15) VREF = 11 Volt (12/15) VREF = 12 Volt (13/15) VREF = 13 Volt (14/15) VREF = 14 Volt (15/15) VREF = 15 Volt

0/15 1/15 2/15 3/15 4/15 5/15 6/15 7/15 8/15 9/15 10/15 11/15 12/15 13/15 14/15 15/15

So the analog voltage for binary word = (weight of the binary word) x VREF

381

It may be noted from this table 13.1 that the analog voltage corresponding to binary equivalent is discrete step value as given in figure 13.1. The discrete step is of 1 volt if VREF is assumed to be 15 volts in a four bit digital input. The step voltage (analog) will be dependent on the reference voltage. There will, however, be 2n steps in n-bit digital system.

Fig. 13.1 Resistive divider network is used for converting digital inputs to analog outputs. The network for 6 bit binary system shown in figure 13.2 is known as the weighted network, as the resistors are weighted inversely with their current values. The input binary bits are b5 b4 b3 b2 b1 b0 where b0 is the LSB and b5 is MSB. These binary bits may be logic 0 or 1. Logic 0 may further be assumed as 0 volt and logic 1 as VREF. So V0, V1, V2, V3, V4 and V5 are the input voltage levels which may be 0 volt or VREF depending on the binary bits. The resistors R0, R1, R2, R3, R4 and R5 are connected to bits b0, b1, b2 , b3, b4, b5 respectively. It may be noted from this network that the resistor connected to the binary bit is half the value of resistor connected to the previous (lower) bit. Hence this network also called as the resistive divider network. Let RL is the load resistance which is supposed to very high i.e. very much higher than the resistor R0.

382

Fig. 13.2 Now the voltage VL across the load resistance RL can be obtained by using Millman’s theorem. This theorem states that the voltage appearing at any node in a resistive network is equal to the sum of all the currents that would enter to the node divided by the sum of conductances connected to that node. V5 V4 V3 V2 V1 V0 + + + + + R5 R4 R3 R2 R1 R0 Thus VL = 1 1 1 1 1 1 + + + + + R5 R4 R3 R2 R1 R0 V5 V4 V3 V2 V V + + + + 1 + 0 = R 2 R 4 R 8 R 16 R 32 R 1 1 1 1 1 1 + + + + + R 2 R 4 R 8 R 16 R 32 R [32V5 + 16V4 + 8V3 + 4V2 + 2V1 + V0 ] 32 = [32 + 16 + 8 + 4 + 2 + 1] 32 V0 + 2V1 + 4V2 + 8V3 + 16V4 + 32V5 = 63 1 = 6 (2 0 V0 + 21V1 + 2 2 V2 + 2 3 V3 + 2 4 V4 + 2 5 V5 ) …(13.1) (2 − 1) In this equation (13.1), the load resistance RL is not considered as it is assumed to be large enough offering low (almost zero) conductance. From this equation it is clear that if the input binary bits are all 1 (in a six bit system) and reference voltage VREF = 6.4 volts (say), the VL is given by: 1 VL = x 63V REF = 6 . 4 volts 63 In general, the equation (13.1) for output voltage of n-bit binary digits is given as:

383

VL =

1 (2 0 V0 + 21V1 + 2 2 V2 + 2 3 V3 + 2 4 V4 ......... + 2 n −1Vn −1 ) (2 − 1) …(13.2) n

The output of this network is as per our requirement, and is proportional to the input binary data. Using the network discussed above, a D/A converter (called binary weighted D/A converter or Resistive divider D/A converter) can be designed as given below. The schematic diagram of 6-bit D/A converter is shown in figure 13.3. It consists of the following major parts: n switches, one for each bit applied to the input, (i) (ii) A binary weighted resistive network which changes each of the digital level into equivalent binary weighted voltage or current. (iii) A reference voltage source VREF. (iv) A summing amplifier that adds the currents flowing in the resistors of the network to develop a signal that is proportional to the digital input.

Fig. 13.3 In this circuit, one switch is connected to each binary bit. In fact these switches are such that when the binary bit is 0, the corresponding resistor of the network gets connected to the ground potential and when the binary bit is 1, the corresponding resistor of the network gets connected to the VREF volt. The current flowing through any branch of the network will be the logical voltage (0volt or VREF volts) divided by the corresponding resistor. So the total current I will be given by (ref. fig. 11.3): V V V V V V I= 5 + 4 + 3 + 2 + 1 + 0 R5 R4 R3 R2 R1 R0 V V V V V V = 5 + 4 + 3 + 2 + 1 + 0 R 2 R 4 R 8R 16 R 32 R Since the voltages V5 through V0 are either 0 or VREF volts depending upon the bit value, so it is customary to take common voltage VREF and bits are kept in place of voltages. So V5 is replaced by VREF.b5, V4 by VREF.b4 and so on; the bits b5, b4, b3 etc will be 0 or 1. The current I may, therefore, be represented as follows:

384

V REF [32b5 + 16b4 + 8b3 + 4b2 + 2b1 + b0 ] 32 R V = REF 2 0 b0 + 21 b1 + 2 2 b2 + 2 3 b3 + 2 4 b4 + 2 5 b5 5 2 .R This is the equation of current I for 6 input bits. The general equation of current I for n input bits is given by: V 2 0 b0 + 21 b1 + 2 2 b2 + 2 3 b3 + 2 4 b4 ..... + 2 n −1 bn −1 I = nREF 2 −1.R …(13.3) The voltage at the output of operational amplifier will be given by: Vout = − R f .I The resistor Rf is the feed back resistance in the operational amplifier. The output voltage of the operational amplifier is proportional to input binary data. The switches connected in figure 13.3 can be replaced by the electronic switches (transistorized) as shown in figure 13.4. When the bit is at logic 1, the corresponding transistor conducts and the current flows through the collector resistor as required; and when the bit is at logic 0 the transistor goes into cutoff and no collector current flows. I=

[

]

[

]

Fig. 13.4 This D/A converter is economical and simple method to design but suffers the following serious drawbacks: 1. The network in this D/A converter is constructed using the precession resistors and resistors have different values. So it is difficult in practice to choose the resistors with accuracy and stability. 2. When the number of bits in the network is large, then the current from the source will be large enough. The current in the MSB branch (resistor) will be much larger than LSB branch. In a 10 bit D/A converter, the current in MSB branch will be 512 times larger than the MSB branch. 13.1.2 Binary Ladder D/A Converter A more commonly used D/A converter is a binary ladder D/A converter, which removes the drawbacks discussed in resistive divider D/A converter. This type of D/A converter contains an R-2R ladder network. The R-2R resistive ladder network will now be discussed, which gives the output a weighted sum of digital inputs. Such a ladder 385

network for 4-bit input is shown in figure 13.5. This network is constructed having only two resistor values i.e. R and 2R. In this network b0, b1, b2 and b3 are the input binary bits and b0 is the LSB and b3 is MSB. Any of these bits will be at the ground potential when the corresponding bit is at logic 0 or at the reference potential (VREF) when the input bit is at logic 1.

Fig. 13.5 To examine the behaviour of this network, it is assumed that the bit b3 is at logic 1 (or VREF potential) as shown in figure 13.6(a). The output voltage corresponding to MSB may be calculated as follows. The equivalent resistance at the point X is the parallel combination of two resistances each having the value of 2R. So the equivalent resistance looking at point X and ground is R as shown in figure 13.6(b). At the point Y again there is a parallel combination of two 2R resistances; the equivalent resistance looking at the point Y and ground is R as shown in figure 13.6(c). Similarly, one can find the equivalent resistance looking at the point Z and ground is R as shown in figure 13.6(d).

(a)

(b)

386

(c)

(d) Fig. 13.6 From figure 13.6(d) it is clear that the resistance looking at the point W and ground is 2R, and the resistance looking towards the bit b3 is also 2R. Thus the output voltage at the point W due to bit b3 (MSB) assumed at VREF potential is given by: V x 2 R VREF V0 = REF = (2 R + 2 R) 2 The output voltage V0 due to the binary input 1000 (only MSB is high) is half of the reference voltage having Thevenis’s resistance R in series with it. Similarly one can calculate the output voltage due to the binary input 0100 (i.e. second MSB); the network for this case is shown in figure 13.7(a). The resistance looking at the point Y and ground is R as shown in figure 13.7(b). The resistance between the point Z and ground is 2R. The voltage at point Z and ground is (VREF/ 2) have a Thevenin’s resistance R, as shown in figure 13.7(c).

(a)

387

(b)

(c) Fig. 13.7 From this figure the output voltage V0 at the point W is given by: (V / 2) x 2 R V REF V0 = REF = (2 R + 2 R) 4

So the output voltage due to second MSB (or for binary input 0100) is

VREF with 4

Thevenin’s resistance R in series with it. It can further be shown that the output due to third MSB (for binary input 0010) V V is REF . And for LSB (0001 binary input) the output is REF . Each voltage source will 8 16 have Thevenin’s resistance R in series with the source. The total output voltage in analog form, due to all the inputs as 1 (for 1111) can easily be found by adding the outputs obtained for each bit as given below: V V V V V0 = REF + REF + REF + REF 2 4 8 16 VREF V It may be noted that is the voltage due to MSB, REF due to second MSB, 2 4 VREF VREF for third MSB and for LSB. So to distinguish these voltages it is useful to 8 16 write the bit positions along with VREF as given below. So if the bit is 0 the voltage corresponding to that bit will be zero otherwise the voltage as discussed above. V xb V xb V xb V xb V0 = REF 3 + REF 2 + REF 1 + REF 0 2 4 8 16 VREF = [8 xb3 + 4 xb2 + 2 xb1 + 1xb0 ] 16

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[

]

V REF 0 2 xb0 + 21 xb1 + 2 2 xb2 + 2 3 xb3 …(13.4) 24 The equation (13.4) is the equation for voltage at the output of 4 bit binary ladder network. A general equation for the output of n-bit binary data can be given as follows: V V0 = REF 2 0 xb0 + 21 xb1 + 2 2 xb2 + 2 3 xb3 + ..... + 2 n −1 xbn −1 …(13.5) n 2 =

[

]

The output of this network is proportional to the input binary data. So using this R-2R ladder network, a D/A converter (called binary ladder D/A converter) can be designed as given below. The schematic diagram of 4-bit D/A converter is shown in figure 13.8. It consists of the following major parts. (i) n switches, one for each bit applied to the input, (ii) A binary ladder network which changes each of the digital level into equivalent binary weighted voltage or current. (iii) A reference voltage source VREF. (iv) A summing amplifier that adds the currents flowing in the resistors of the network to develop a signal that is proportional to the digital input.

Fig. 13.8 The output voltage Vout of this D/A converter due to MSB (1000 binary input) will be calculated as given below: The voltage at the point W due to MSB is VREF / 2 having a Thevenin’s resistance R in series with it as discussed above and is shown in figure 13.9

Fig. 13.9 From this figure, the current I is given by: 389

V REF 1 ( ) 2 3R and the output voltage Vout is given by: Vout = − I .R f I=

VREF 1 V ( ).3R = − REF 2 3R 2 The output voltage is the same as calculated in equation 13.5, with the difference that it has a negative value because the operational amplifier is used in inverting configuration. Note that the resistors in the ladder network are either R or 2R. It is the ratio of resistances matters rather than the absolute value of resistances. Further the resistors do not cover a wide range of magnitude; it is, therefore, practically possible to get the precision in the ratio of their magnitudes. The temperature coefficients of these resistances can easily match. Because of these advantages, the ladder network is widely used in D/A converters. 13.2 PERFORMANCE CRITERIA FOR D/A CONVERTER The D/A converters are available in the form of ICs with different specifications for their performances. So before discussing D/A converter ICs it will be better to discuss first the characteristics of the converters specified by the manufacturers. These specifications include: 1. Resolution 2. Accuracy 3. Monotonicity 4. Settling time 1. Resolution: As discussed above, the analog output of D/A converter is proportional to the digital input (binary data), so a perfect staircase is obtained if there is an LSB increment. The resolution is, therefore, a measure of quality of D/A converter, which is defined as the ratio of the LSB increment to the maximum output. For an n-bit D/A converter the resolution is given by: The change in output due to LSB increment for n-bit digital input (Step size) = Full scale output / No. of steps =−

where (2 n − 1) is the number of steps for n-bit D/A converter.

The step size for a 10 bit D/A converter, having full scale output voltage as 10 10 10 volts, is given by = 10 = = 9.8mV 2 − 1 1023 And % Resolution = 0.0978%

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2. Accuracy: Accuracy of a D/A converter is the closeness of the output analog voltage to the expected theoretical output. In a linear variation of analog output with digital input, the relative accuracy is the maximum deviation of the D/A output compared with the linear behaviour. It is expressed as a percent of a full-scale or maximum output voltage. For example, if a converter has a full scale output of 10 V and the accuracy is ± 0.1% , then the maximum error for any output voltage is (10V)(0.001) = 10 mV. Ideally, the accuracy should be at most ± ½ of an LSB. 1 For an 8 bit D/A converter, one LSB is = 0.0039 = 0.39% of full scale. The 256 accuracy should be approximately ± 0.2% . 3. Monotonicity: A D/A converter is said to be monotonic if it gives an analog output voltage which increases regularly and linearly with increase in input digital signal. Such a quality of the converter is called as monotonicity. In order to demonstrate monotonicity of a D/A converter, a counter output is given as digital input to a D/A converter and the analog output is displayed on the CRO. Monotonicity then requires that the output waveform should be a perfect staircase waveform with steps equally spaced and of same magnitude. If the steps are missing or have varying magnitude, the D/A converter is defective. 4. Settling Time: After the application of digital input to a D/A converter, it takes about few nanoseconds to microseconds to produce the correct output. So the settling time is defined as the time the converter takes to give an output to settle within ± ½ LSB of its final value. For example, if a D/A converter has a resolution of 10mV, the settling time is the measure of the time the converter takes to settle with in ± 5mV of its final value. Figure 13.10 illustrates the settling time in a D/A converter. The settling time is important because it places a limit on how fast one can change the digital input. The settling time depends on the stray capacitance, saturation delay time, and other factors.

Fig. 13.10 13.3 D/A CONVERTER IC 0808 There are many commercially available D/A converter ICs. The IC 0808 is the most popular, inexpensive and widely used 8 bit D/A converter. It contains a reference current source, an R-2R binary ladder network and 8 transistor switches to steer the binary currents to the network. Figure 13.11 shows the pin configuration of this D/A converter IC 0808.

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Fig. 13.11 In this IC, pins 5 through 12 are the 8 bit input data, so should be connected to input data bits. Pin 15 is to be connected to ground through a resistance. Pin 13 is to be connected to +5 volt supply. Pin 3 (VEE) is to be connected to – 15 volts. Pin 4 is the output current of the ladder network should be connected to the operational amplifier. Pin 2 is the ground pin. The pin 16 is the frequency compensation pin, a capacitor between pin 16 and 3 is to be connected for this purpose. A circuit diagram to get the analog output voltage corresponding to 8 bit digital input is shown in figure 13.12. A +5 V supply sets up a reference current of 2mA for the ladder. The output current Iout drives the operational amplifier to give final output between 0 and 2 volts (approximately) for the 8 bit digital input.

Fig. 13.12 There are many other commercially available D/A converter as given below: DAC 0800 – A monolithic 8-bit high speed current output DAC. DAC 0806 and DAC 0807 – 8 bit monolithic D/A converters. DAC 1000 and DAC 1008 – 10 bit microprocessor compatible advanced CMOS D/A converters. DAC 1202 and DAC 1203 – Three-digit (BCD) D/A converter. 13.4 INTERFACING OF D/A CONVERTER For the interfacing of 0808 D/A converter with the microprocessor 8085A, the circuit shown in figure 13.12 may be connected to the system through the 8255 PPI (Programmable Peripheral Interface as shown in figure 13.13.

392

393

Fig. 13.13

394

In this circuit feedback resistor Rf is considered as 5 KΩ and the reference voltage is taken as VREF = 10 V, so that we get the output current I Out as:

[

]

I REF 0 2 xb0 + 21 xb1 + 2 2 xb2 + 2 3 xb3 + ..... + 2 n −1 xbn −1 n 2 Here the value of n = 8 as it is 8 bit D/A converter. I So I Out = REF 2 0 xb0 + 21 xb1 + 2 2 xb2 + 2 3 xb3 + ..... + 2 n −1 xbn −1 256 V 10V I REF = REF = = 2mA and RREF 5 KΩ 2mA 0 and VOUT = 2 xb0 + 21 xb1 + 2 2 xb2 + 2 3 xb3 + ..... + 2 n −1 xbn −1 xR f 256 10 0 = 2 xb0 + 21 xb1 + 2 2 xb2 + 2 3 xb3 + ..... + 2 n −1 xbn −1 256 If all the input bits (b0 – b7) are 1 (FF H), then the output voltage (known as full scale output voltage) is given by: 255 VOUT = x10 ≈ 10V 256 The output voltage corresponding to the input 1000 0000 (80 H) is given by: 128 VOUT = x10 = 5V 256 So we have the linear output corresponding to the binary inputs i.e. Digital Input Output Voltage 00 H 0V 80 H 5V FF H 10 V These input output levels may be verified, if the following three programs are executed and the voltages at the outputs in the three cases are measured. Program 1: MVI A, 80 H ; 8255 is initialized with all the ports as output port. OUT 03 H ; Control word is written in control word register. MVI A, 00 H ; Get A = 00 H, so that 00 H is applied to the input of D/A converter. OUT 00 H ; 00 H is available at the Port A of 8255 so that it is applied to the input of D/A converter. HLT ; Stop processing. After execution of this program, if the voltage at the output of the circuit of D/A converter is measured we get 0 V. It verifies that 00 H is applied at the input of the converter, we get 0 V. Program 2: MVI A, 80 H ; 8255 is initialized with all the ports as output port. I Out =

[

]

[

]

[

]

395

OUT 03 H

; Control word is written in control word register. MVI A, 80 H ; Get A = 80 H, so that 80 H is applied to the input of D/A converter. OUT 00 H ; 80 H is available at the Port A of 8255 so that it is applied to the input of D/A converter. HLT ; Stop processing. After execution of this program, if the voltage at the output of the circuit of D/A converter is measured we get 5 V. It verifies that 80 H is applied at the input of the converter, we get 5 V. Program 3: MVI A, 80 H

; 8255 is initialized with all the ports as output port. OUT 03 H ; Control word is written in control word register. MVI A, FF H ; Get A = FF H, so that FF H is applied to the input of D/A converter. OUT 00 H ; FF H is available at the Port A of 8255 so that it is applied to the input of D/A converter. HLT ; Stop processing. After execution of this program, if the voltage at the output of the circuit of D/A converter is measured we get 10 V. It verifies that FF H is applied at the input of the converter, we get 10 V. Example 13.1. The input bits of the D/A converter is connected to the output pins of Port A of 8255, which is already connected with the microprocessor (ref. fig.13.13). Write a program to generate stair case voltage with ten steps. It should have the constant pulse duration. Solution. There should be 10 steps for the stair case voltage to be generated with the D/A converter. So the height of the stair case should be approximately 1 volt. Since FF H gives 10 volts, so 19 H should be decreased each time in 10 go. When 19 H is subtracted from FF H in the first go we get E6 H. The output voltage corresponding to E6 H is given by: 230 VOut = x10 = 8.984 volts 256 Therefore, the subtraction of 19 H from FF H gives a decrement of 1 volt at the output. The program for the generation of stair voltage is given as: PROGRAM Label Mnemonics Operand Comments MVI A, 80 H ; Initialize 8255-I to work all the ports as output ports. OUT 03 H ; Write the control word (80 H) in the control word register of 8255-I. START MVI A, FF H ; Load FF H to accumulator.

396

REPEAT

END

OUT CALL

00 H DELAY

MVI B,

00 H

SBI

19 H

OUT INR B CPI JZ PUSH PSW PUSH B CALL

00 H

DELAY

POP B POP PSW JUMP

REPEAT

MVI A, OUT CALL

00 H 00 H DELAY

JMP SUBROUTINE PROGRAM: Label Mnemonics DELAY LXI D,

0A H END

START Operand 0020 H

; Send FF H (10 V) to PA0. ; Jump to delay subroutine to introduce a delay of constant pulse width. ; Use B-register as counter for 10 steps. ; Subtract 19 H to calculate next weight for the output of D/A converter. ; Send the data to the output. ; Increment B-register. ; If 10 steps complete then ; Jump to repeat the process. ; Save PSW ; Save B-C register pair. ; Jump to delay subroutine to introduce a delay of constant pulse width. ; Restore the contents of B-C pair. ; Restore the PSW. ; Jump to repeat to output for the next weight. ; Store 00 H to the accumulator. ; Outputs for 00 H. ; Jump to delay subroutine to introduce a delay of constant pulse width. ; Repeat for next cycle.

Comments ; Loads DE register pair with a 16bit number. LOOP1 DCX D ; Decrements DE register pair by 1. MOV A, E ; Moves the contents of E register to accumulator. ORA D ; ORing of the contents of D and E registers are performed to set the zero flag. JNZ LOOP1 ; If result is not zero than jump to LOOP1. RET ; Go back to main program. In the subroutine program, DE register pair may be loaded with any other 16-bit number to change the pulse width. The exact time of the pulse width may be calculated as discussed in the delay programs. After the execution of this program, the output may be seen on the CRO. The output will be stair case wave.

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Example 13.2. Write a program to generate square wave of 1 KHz frequency with a peak voltage of 2.5 volts. Use D/A converter (ref. fig. 13.13) for this purpose. The square wave should be available at the output of the converter. Solution. It is required to generate square wave of 1 KHz frequency, the time period of such wave should be 1msec. During 1 msec the output should be high for 0.5 msec and low for the same time. Time delay can be introduced by using the following subroutine program: SUBROUTINE PROGRAM: Label Mnemonics Operand Comments DELAY LXI D, 0040 H ;Loads DE register pair with a 16-bit number. LOOP DCX D ;Decrements DE register pair by one. MOV A, E ;Moves the contents of E register to accumulator. ORA D ;ORing of the contents of D and E registers are performed to set the zero flag. JNZ LOOP ;If result ≠ 0 jump to loop RET ;Go back to main program. Total T-states used for the above sub routine program are given as: Mnemonics T-states LXI 10 DCX 5 MOV 5 ORA 4 JNZ LOOP 10/7 RET 10 24 T-states are used for the inner loop and 10+7+10 = 27 T-states are used for outer loop. In this program the execution of loop is for 64 times (as 0040 H = 6410). The condition for the check of zero flag can not be applied just after DCX instruction, since no flag gets affected with this instruction. So to check the zero flag ORA instruction affect the zero flag. The zero flag will be set if the contents of both D and E registers are zero. The time delay introduced by the inner loop is: TLOOP = 64 x 24 x Time of one T-state. If the system clock frequency is 3 MHz, then 1 TLOOP = 64 x 24 x µsec 3 = 512 µsec = 0.5 msec. Delay introduced for outside loop is:

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1 Tout = 27x1x µsec 3 = 9 µsec So the total time delay introduced by the above subroutine program is given by: TDelay = 0.5 msec + 9 µsec ≈ 0.5 msec Further, it is required that the voltage level of the output should be 2.5 volts, for which the digital input should be 40 H as 80 H gives 5 volts. So the main program is given as: MAIN PROGRAM Label Mnemonics Operand Comments MVI A, 80 H ; Initialize 8255-I to work all the ports as output ports. OUT 03 H ; Write the control word (80 H) in the control word register of 8255-I. START MVI A, 00 H ; Load 00 H to accumulator. OUT 00 H ; Send 00 H (00 V) to PA0. PUSH PSW ; Save PSW CALL DELAY ; Jump to delay subroutine to introduce a delay of 0.5msec. POP PSW ; Restore the PSW. MVI A, 40 H ; Store 40 H to the accumulator. OUT 00 H ; Outputs for 40 H. PUSH PSW ; Save PSW CALL DELAY ; Jump to delay subroutine to introduce a delay of 0.5msec. POP PSW ; Restore the PSW. JMP START ; Repeat the process for next cycle. During the execution of this program the wave shape at output of the D/A converter can be checked. It will be a square wave of 1 KHz frequency. Example 13.3. Write a program to generate a triangular wave form using 8255 and DAC 0808 (ref. fig. 13.13). Solution. The program for the same is given below: MAIN PROGRAM Label Mnemonics Operand Comments MVI A, 80 H ; Initialize 8255-I to work all the ports as output ports. OUT 03 H ; Write the control word (80 H) in the control word register of 8255-I. LOOP MVI A, FF H ; Load FF H to accumulator. OUT 00 H ; Send FF H (10 V) to PA0. INR A ; Increment accumulator. OUT 00 H ; Output corresponding to this weight is available (i.e. increasing

399

voltage is available at the output of the converter). CPI FF H ; Compare if output has become 10 Volts. JZ LOOP 1 ; If yes go to LOOP 1. JMP LOOP ; If no go to LOOP. LOOP 1 DCR A ; Decrement accumulator. OUT 00 H ; Outputs for decrement data. JZ LOOP ; If accumulator content becomes 0, go to LOOP. JMP LOOP ; Else to LOOP. During the execution of this program the wave shape at output of the D/A converter can be checked. It will be triangular wave. 13.5 MICROPROCESSOR COMPATIBLE D/A CONVERTER Now a days microprocessor compatible D/A converters are also available, which are designed for the purpose of directly interfacing with the microprocessor without the use of external latch. Among such converters, AD558 is very simple, inexpensive and commonly used D/A converter to be connected directly to the microprocessor.

Fig. 13.14 Figure 13.14 shows the block diagram of this D/A converter, which includes internally a latch and output op amp. It can be operated with + 4.5 V to 16.5 V d.c. power

400

supply. Two pins CS (chip select) and CE (chip enable) are provided with the chip to interface with the microprocessor 8080 or 8085. For the interfacing with 8085 CE may be connected to IOW of the processor and CS may be connected to the A7 bit of the address line. The other pins of the address lines may be assumed as 0, so that 80 H will be the port address of this converter. When both the signals CS and CE are at logic 0, the latch is transparent means the input is transferred to the D/A block of this converter. When either of CS or CE goes to logic 1, the input is latched in the register and held until both control signal go to logic 0. The programs given in the above examples (solved) can be executed with this converter by using the proper port address. 13.6 ANALOG TO DIGITAL CONVERTER Generally the information to be processed by the digital systems is in the analog form. So before applying such signals to the digital systems it is necessary to convert the signal into its equivalent digital form. The method with the help of which the analog signal is converted to digital form is known as analog to digital (A/D) converter. The A/D converter is more complex and difficult than the D/A converter. Followings are the different methods for A/D converter, which will be discussed in the next sections. (i) Simultaneous A/D converter (ii) Successive approximation D/A converter (iii) Counter or Digital Ramp type A/ D converter (iv) Single slope D/A converter (v) Dual slope D/A converter 13.7 SIMULTANEOUS A/D CONVERTER This is the fastest and simplest method of converting an analog signal to digital signal. It utilizes the parallel differential comparators; the input analog voltage is compared by these comparators with known voltages called as reference voltages. The comparators gives the low output (logic 0) when the input is less than the reference voltage and gives the high output (logic 1) when the input analog voltage exceeds the reference voltage. This method of conversion is also called as Flash or parallel type A/D converter.

Fig. 13.15 For the conversion of analog voltage ranging between 0 to V volts into two bit digital output, three comparators (in general 2n – 1 comparators where n in the number of

401

bits) are required. The input analog voltage is converted to the 4 (in general 2n) equal regions as shown in figure 13.15. If the analog voltage is lying in the first region, then the binary bits (b1, b0) are 00, similarly to second, third and forth regions the binary bits are 01, 10 and 11 respectively. The reference voltages to the three comparators C0, C1, C2 should be V/4, V/2, 3V/4 respectively as shown in figure 13.16. The output of the three comparators should be connected to the logic gates to produce the desired binary output. The read gates and output registers are used to read the digital output.

Fig. 13.16 Referring to figures 13.15 and 13.16, if the input analog voltage exceeds the reference voltage to any comparator, the comparator gives high output (logic 1); if on the other hand if the input analog voltage is less than the reference voltage of the comparator, it gives low output (logic 0). In this way if all the comparators give low output, the analog input voltage must be between 0 and V/4 volts (I region) and digital binary output should be 00. If the C0 is high and C1 and C2 are low, the input must be between V/4 and V/2 volts (II region) and digital binary output should be 01. If C0 and C1 are high and C2 is low, the input must be between V/2 and 3V/4 volts (III region) and digital binary output should be 10. Finally if all the comparators give high outputs, the input must lies 3V/4 and V volts (IV region) and digital binary output should be 11. Table 13.2 summarizes outputs of the comparators. Table 13.2

By drawing the K –maps (figure 13.17), the expressions for b0 and b1 are obtained as:

b1 = C1

b0 = C1 ⋅ C 0

and

402

(a)

(b) Fig. 13.17 These expressions may be realized using the gates as shown in figure 13.18. The output may be reset by applying high signal to the reset line and to read the data a high signal is applied to the read line.

Fig. 13.18 For the conversion of analog input voltage (0 to V volts) into three bit binary output we proceed in the similar method as for the two bits output. For the three bits outputs the input voltages are divided into 8 (as 23 = 8) equal regions and 7 (as 23-1 = 7) comparators are to be used. So the logic circuit to be designed should have seven inputs (output of the seven comparators) and three outputs. The output of comparators and the corresponding binary output are shown in table 13.3. Table 13.3

The expressions of the output bits can easily be obtained by examining the table 13.3. 403

The bit b2 gives the high output whenever the output of the comparator C3 is high. So b2 = C 3 . The bit b1 is high whenever the output of comparator C1 is high and output of C3 is low, or whenever the output of comparator C5 is high. So b1 = C1 ⋅ C 3 + C5 . Similarly, the expression for bit b0 can be obtained as: b0 = C 0 ⋅ C 1 + C 2 ⋅ C 3 + C 4 ⋅ C 5 + C 6

Fig. 13.19 These expressions may be realized using the gates as shown in figure 13.19. The output may be reset by applying high signal to the reset line and to read the data a high signal is applied to the read line. The design of a simultaneous A/D converter is quite straight forward and relatively easy to understand. However, the design becomes complicated as the number 404

of bits is increased, since the number of comparators to be used increases drastically. This method has highest speed of conversion. 13.8 SUCCESSIVE APPROXIMATION A/D CONVERTER Simultaneous A/D converter has the very fast conversion time but becomes unwieldy when the required digital bits are more. The successive approximation method is most useful and commonly used method. The block diagram four bit successive approximation A/D converter is shown in figure 13.20. It consists of a D/A converter, successive approximation register (SAR) and a comparator. The basic principle of this A/D converter is as follows:

Fig. 13.20 In this type of converter, the bits of D/A converter are enabled one by one, starting with the most significant bit (MSB). The analog output of the D/A converter corresponding to the enabled bit is compared with the input analog voltage. The comparator gives the output low if the input analog voltage is less than the output of the D/A converter and it gives the high out if the input analog voltage is more than the output of the D/A converter. The low output of the comparator resets the corresponding bit of SAR, on the other hand if the comparator’s output is high then that bit is retained in SAR. In this way the output of D/A converter are compared with the input voltage for all the bits starting with the most significant bit. Thus the successive approximation method is the process of approximating the analog voltage bit by bit starting with MSB. This process is shown in figure 13.21.

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Fig. 13.21 In order to understand the operation of this type of A/D converter, we will take a specific example of a four-bit conversion. Figure 13.22 (a through d) shows the step –bystep conversion of a given analog input voltage (say 6 volts). It is further assumed that D/A converter has the following output characteristics: Vout = 8 volts for bit 3 (MSB or b3) Vout= 4 volts for bit 2 (2nd MSB or b2) Vout= 2 volts for bit 1 (3rd MSB or b1) Vout=1 volt for bit 0 (LSB or b0)

(a)

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(b)

(c)

(d) Fig. 13.22 It is clear from these figures that after completing the conversion cycle. The binary code 0110 is retained in SAR, which is binary value of the input voltage (6Volts). It is finally displayed on the display devices. 13.9 COUNTER OR DIGITAL RAMP TYPE A/D CONVERTER Another method of converting the analog signal to digital one is the counter or digital ramp type A/D converter which utilizes a binary counter to count a continuous pulse of standard width and height from a clock. The standard clock pulses are passed through a gate which is open for some time to allow these pulses to go to the input of counter. Normally the gate is closed and as soon as the start signal is applied a stair case voltage is initiated. This voltage is increased linearly with the increase of the binary counts in the counter. The gate remains open for the time the linear stair case voltage

407

becomes equal to the input analog voltage. The counter records the number of clock pulses which is proportional to the input analog voltage. Figure 13.23 shows the schematic diagram of this type of A/D converter. The analog signal, to be converted to its equivalent digital output, is applied to one input of an operational amplifier being used as a comparator. When a start of conversion pulse is applied to the control unit it resets the binary counter and opens the gate. The counter

Fig. 13.23 starts counting the clock pulses which are of standard width and height. The output of the counter is fed to a D/A converter which produces an analog output (stair case voltage) in response to the digital signal (output of the counter) as its input. This analog output voltage is fed to the reference input of the comparator. So long as the input analog signal is greater than the stair case voltage the comparator provides the high output to the gate, the gate remains open and the clock pulses are allowed to reach to the input of the counter. These pulses are counted by the counter thus continuously increasing the digital output. The moment the analog output of D/A converter (stair case voltage) exceeds the input analog voltage, the comparator provides a low output disabling the gate and the counter stops counting. The binary number stored in the counter represents the digital output voltage corresponding to the input analog voltage. The digital output is displayed on the display devices.

408

Fig. 13.24 For a steady input the digital output is as shown in figure 13.24. The output is represented by the number of clock pulses counted by the counter till the stair case voltage becomes equal to the input voltage. This method of conversion is slow; as for maximum input, the counter has to count from zero to maximum number of states for the comparison. For each conversion cycle the counter is to be reset and counting starts from beginning. The time of conversion is not important in d.c. or slow varying signals as the output waveform gives a good representation from which the input waveform can be constructed as shown in figure 13.25. But if the conversion time and the signal transient time are comparable the reconstructed digital output will not be correct. In this case it is necessary to reduce the conversion time by using faster D/A converter.

Fig. 13.25 A modification to this converter is possible if the resetting of the counter is avoided each time. For this purpose an up/down counter may be used in place of up

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counter. The circuit shown in figure 13.26 illustrates this modification in which an

Fig. 13.26 up/down binary counter is used and the converter proceeds without resetting. The circuit is almost the same as the counter or digital ramp type A/D converter. The up/Down counter is operated by up or down signals from the control unit. The digital to analog converter output controls the output of the comparator. Till the D/A converter output is less than the analog input voltage, the up signal is enabled and the counter counts in forward direction. When the analog input falls, the down signal is enabled and the counter starts reverse counting giving an output corresponding to new analog input as shown in figure 13.27.

Fig. 13.27 13.10 SINGLE SLOPE A/D CONVERTER This type of method is similar to counter or digital ramp type A/D converter. In this type of A/D converter also, a gate whose period is proportional to the amplitude of the analog sample is generated. For the generation of gate, the input analog voltage is compared with the output of an integrator. The output of integrator is a ramp voltage of constant slope. The standard clock pulses are passed through the gate and are counted by the counter. The gate remains open for the time proportional to the input analog signal. The recorded number of pulses is, therefore, the required digital output of the analog signal.

410

The schematic block diagram of such an analog to digital converter is shown in figure 13.28. Initially a reset pulse is applied which clears the counter and resets the integrator. The integrator produces a linearly rising ramp voltage, whose slope will depend on the values of the resistance R and capacitor C. The input analog voltage is compared by a comparator with the ramp voltage. As long as the integrator output is smaller than the input analog voltage, the comparator output is high. This high output enables the AND gate. The standard clock pulses are, therefore, allowed to pass through the gate which will be counted by the counter. When the ramp voltage becomes greater than the input analog voltage, the comparator changes the state thereby disabling the AND gate. The counter stops counting. It can easily be seen that the gate duration is linearly related to the magnitude of the input analog signal. Hence the count accumulated in the counter is a digital representation of the input analog voltage. It may be mentioned here that the precision in the proportionality between the gate duration and the magnitude of the input analog signal depends upon the linearity of the ramp voltage obtained at the output of the operational amplifier. So the overall accuracy will depend upon the stability of reference source, the off-set of the operational amplifier, the frequency stability of the clock as well as the values of resistance R and capacitance C.

Fig. 13.28 13.11 DUAL SLOPE A/D CONVERTER

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In single slope A/D converter, the accuracy of the converter depends on the linearity of the ramp voltage generated by the integrator. The linearity of ramp voltage, however, depends on the accuracy of the values of Resistance R and capacitance C of the integrator, whose values may vary with time and temperature. The dual slope analog to digital converter utilizes two different ramps, one for fixed time and other for fixed slope. It is very popular and widely used D/A converter because it has the slowest conversion time and relatively low cost. This method offers good accuracy, good linearity, and very good noise rejection characteristics.

Fig. 13.29 The logic diagram of the dual slope A/D converter is given in figure 13.29. This converter is similar to that of the single slope A/D converter. In this converter, the integrator forms two different ramps, one for fixed time and other for fixed slope. The capacitor of the integrator is first charged with constant current obtained from input analog voltage for fixed time then the capacitor is discharged for fixed slope through other constant current obtained from a reference voltage source. The basic operation of this converter can be understood as follows: This converter consists of standard clock pulses applied to the gate. The gate allows the pulses to the input of the counter which counts these pulses. Initially all the counters are reset to 0’s and ramp too is reset to zero. Now the control logic allows switch S to connect the input analog voltage Vin to the integrator circuit. A constant V current equal to in flows through the capacitor C as the inverting input of the R operational amplifier of the integrator is at virtual ground. The capacitor C will charge linearly with this constant current. This results a negative going ramp at the output of the integrator. The comparator’s output will be positive which allows the clock pulse to pass through the AND gate to the input of the counter. This ramp is allowed for fixed time say t1. The actual time t1 is determined by the count detector. The voltage VC at the output of the integrator is given by:

412

t

VC = −

1 1 Vin .dt R.C ∫0

1 … (13.6) .Vin .t1 R.C The counter when reaches the fixed count at t1, the control logic generate a pulse to clear the counter to zero and the switch S connects the integrator input to a negative reference voltage ( – VREF). The capacitor C of the integrator starts discharging linearly due to the constant current from – VREF. The integrator thus produces a positive going ramp beginning at -VC and increases steadily till it reaches to 0 volt as shown in figure 11.29. At this time the counter is counting. The conversion cycle ends when VC = 0 volt; the comparator produces the low state, which disables the gate and counter stops counting. =−

Fig. 13.30 Let t2 is the time when the output of integrator becomes zero, so the output of the integrator is given by: V … (13.7) VC = REF .t 2 R.C Since the integrator’s output beginning at 0 volt and integrates down to –VC and then integrate back to 0 volt, so the equations (13.6) and (13.7) may be equated as: Vin V .t1 = REF .t 2 R.C R.C t or Vin = VREF . 2 … (13.8) t1 In this equation VREF and time t1 are constants, so Vin ∝ t 2 … (11.9) This equation is independent of the values of resistance R and capacitance C. Further at the end of conversion cycle, the counts measured by the counter are proportional to the input analog signal are latched to display on the display devices. 13.12 ADC 0808/0809 The ADC 0808/0809 is an 8-bit A/D converter with 8-channel multiplexer which can be interfaced with the microprocessor. It is the most popular, inexpensive and widely

413

used A/D converter. It is a monolithic CMOS device which uses the method of successive approximation A/D converter. It does not require external zero and full scale adjustment. The device operates with + 5 V d.c. supply. The conversion time is 100 µsec at clock frequency of 640 KHz. The 8-channel multiplexer can directly access any of the 8 single ended analog signals. The ADC 0808 / 0809 offers following features: • High speed • High accuracy • Minimal temperature dependence • Excellent long term accuracy and repeatability • Consume minimal power

Fig. 13.31 The pin diagram and schematic block diagrams of this IC ADC 0808 / 0809 are shown in figures 13.31 and 13.32 respectively. The pin description of this IC is given as: Pins 26-28 and 1-5 – are 8 input channels IN0 – IN7 (multiplexed), which are selected by the three (address) lines ADD A, ADD B and ADD C. Pin 6 SOC – Start of conversion pin. A high to this pin starts the conversion. Pin 7 EOC – End of conversion. This an output terminal and gives high signal when the conversion ends. Pins 21-18, 8, 15-14 & 17 8-bit output (latch) pins to be connected to the port of 8255.

414

Pin 9

OE

–

Pin 10 CLK

–

Pin 11 VCC Pin 12 Ref (+)

– –

Pin 13 GND Pin 16 Ref (-) Pins 25-23

– – –

Output enable pin which is connected to the positive supply. Clock terminal. It is to be connected either to the external clock of frequency between 10 to 1280 KHz or the clock out frequency of the 8085A after dividing it by a factor of four may be connected to this pin. Supply pin (+5 V). Reference pin which is to be connected to the + supply.

Fig. 13.32 Ground terminal. Reference pin to be connected to the ground. Address pins (ADD A, ADD B and ADD C). These pins are used to select the channels as given below (Table 13.4): Table 13.4 Channels Selected IN0

415

Address lines C B A 0

0

0

IN1 IN2 IN3 IN4 IN5 IN6 IN7

0 0 0 1 1 1 1

0 1 1 0 0 1 1

1 0 1 0 1 0 1

The timing diagram of this IC is shown in figure 13.33.

Fig. 13.33 The interfacing connection of ADC 0808 / 0809 with the microprocessor 8085A is shown in figure 13.34. In this circuit an analog voltage, whose equivalent digital value

416

is to be obtained, is applied to IN0. The output terminals of the ADC are connected to

Fig. 13.34 Port A of 8255 PPI. This port is to be used as the input port. The PC7 terminal of the Port CUpper is connected to the End of Conversion terminal of the ADC. This port is also used as the input port. The port CLower is used as the output port. The three terminals PC0 to PC2 are connected to the three address pins of the ADC 0808 / 0809 for the selection of input channel. The PC3 terminal is connected to the SOC (Start of Conversion) and the ALE terminals of the converter. The OE and REF (+) terminals are connected to the + 5V supply. The assembly language program is given below: In the above circuit diagram, the channel used is IN0, so for its selection we have: C B A PC1 PC0 PC2 0 0 0 = 00 H To enable the start of conversion first PC3 is made high and then low without changing the selection of channel, we proceed as follows: PC3 PC2 PC1 PC0 1 0 0 0 =08 H PC3 0 PROGRAM Label

PC2 0 Mnemonics MVI A,

PC1 0

PC0 0

Operand 98 H

417

=00 H

Comments ; Initialize 8255-I to work Port A and Port CUpper as input ports, and port CLower as output port.

OUT

03 H

; Write the control word in the control word register of 8255-I. MVI A, 00 H ; Load accumulator with 00H. OUT 02 H ; 00H is sent to Port CLower to select IN0 channel. MVI A, 08 H ; Load 08 H to accumulator. OUT 02 H ; ALE and SOC are enabled (high). MVI A, 00 H ; Load 00 H to accumulator. OUT 02 H ; ALE and SOC will be low. A pulse is applied from high to low for the conversion through PC3 without affecting the channel selected. READ IN 02 H ; Read End of conversion (PC7). RAL ; Rotate left to check if PC7 is one. JNC READ ; If not 1 READ again. IN 00 H ; Read digital output of the A/D converter. STA 2100 H ; Store the result in 2100 H memory location. HLT ; Stop processing. After the execution of this program, the values stored in the memory location 2100 may be checked.

Analog Voltage 0V 1V 1.4 V 2V 2.8 H 3V 4V 5V

Digital output 00 H 34 H 47 H 6D H 90 H 94 H CE H FF H

13.13 A/D CONVERTER USING D/A CONVERTER AND SOFTWARE The A/D converter can also be realized using the D/A converter and the software. For this purpose the software is used to implement successive approximation A/D converter. Figure 13.35 shows the interfacing connection for this. The input analog voltage is applied to a comparator. This voltage is compared by the output of the D/A converter. The output of the comparator is sensed by the microprocessor through the PC7 of the 8255. A digital input is applied to the D/A converter, through port A of 8255.

418

Fig. 13.35 The microprocessor first applies 00 H as the digital input to the DAC 0808 and checks through PC7 for high signal. If a high pulse does not appear at the output terminal of the comparator, the microprocessor increments the digital input by 1 and the process is repeated till a high signal appears at the output of the comparator. As a high signal appears the microprocessor stops successive approximation and the corresponding digital input value is stored in the memory location. This digital value is equivalent to the analog signal applied at VIN terminal of the comparator. The software for the same is given as: PROGRAM Label Mnemonics operand Comments LXI SP, XXXX H ; Initialize stack pointer. MVI A, 88 H ; Initialize 8255-I to work Port A, Port B and port CLower as output ports, and Port CUpper as input ports. OUT 03 H ; Write the control word in the control word register of 8255-I. MVI A, 00 H ; Load accumulator with digital input to send it to D/A converter. LOOP OUT 00 H ; The digital input is sent to D/A converter through Port A. PUSH PSW ; Save PSW

419

CALL IN

DELAY 02 H

; Call delay subroutine program. ; Check the output of the comparator through PC7, Read PC7 bit. ; Rotate left to check PC7, if it is high. ; If is high go to NXT. ; Else get the digital value from the stack. ; Increment digital value. ; Jump to LOOP. ; Get the digital value from the stack. ; Store the result in 2100 H memory location. ; Stop processing.

RAL JC POP PSW

NXT

NXT

INR A JMP POP PSW

LOOP

STA

2100 H

HLT SUBROUTINE PROGRAM: Label Mnemonics DELAY LXI D,

Operand 0002 H

Comments ; Loads DE register pair with a 16bit number. LOOP1 DCX D ; Decrements DE register pair by one. MOV A, E ; Moves the contents of E register to accumulator. ORA D ; ORing of the contents of D and E registers are performed to set the zero flag. JNZ LOOP1 ; If result ≠ 0 jump to loop1 RET ; Go back to main program. After the execution of this program, the values stored in the memory location may be checked for the input applied voltage. Analog Input Digital output 0V 00 H 2.5 V 40 H 5V 80 H 10 V FF H PROBLEMS 1. Discuss the resistive divider D/A converter. Find the general expression for the output voltage of a resistive divider network. 2. Using the resistive divider network draw the circuit of a 6 bit D/A converter and explain its operation. What are the drawbacks of this D/A converter? 3. Show that the outputs of a binary weighted resistor network are directly proportional to the binary inputs. 4. Draw the schematic diagram of a resistive divider D/A converter. Explain its operation. Mention the drawbacks of this converter.

420

5. 6.

7.

8. 9. 10. 11. 12.

13.

14.

15.

16. 17. 18.

19. 20.

A 5 bit resistive divider network has 0 volts full scale output, find the output voltage for a binary input 10101. (Ans. 6.774 V) A 6 bit resistive divider D/A converter has resistance of 100 KΩ in MSB branch. The reference voltage is 15 V. The resistance in the feed back path of the operational amplifier is 39 KΩ. What is the output voltage for the binary input 101101? (Ans. – 8.22V) For a 6 bit resistive divider network, the reference voltage is 10 V, find the following: (i) Full Scale output voltage. (ii) The analog output voltage for a digital input of 010011. (iii) The output voltage change due to least significant bit. (Ans.:10V, 3.02 V, 0.16 V) Draw the schematic diagram of a binary ladder D/A converter. Explain its operation. Mention its merits and demerits. Find the expressions for the output due to MSB and second MSB of a 4-bit binary ladder network. Discuss the binary ladder D/A converter. Find the general expression for the output voltage of a binary ladder network. What are the performance criteria for the D/A converter? Discuss their importance while selecting a D/A converter. For a 6-bit binary ladder D/A converter the input levels are 0 = 0 V and 1 = 10 V, find (i) The output voltages caused by each bit. (ii) The output voltage corresponding to an input of 101101. (iii) The full scale output voltage of the ladder. (Ans. (i) -5V, -2.5 V, -1.25 V, -0.625 V, -0.3125 V, -0.15625 V (ii) – 7.03125 V (iii) – 9.84 V) For a 5-bit binary ladder D/A converter the input levels are 0 = 0 V and 1 = 10 V, find the output voltage corresponding to binary input of (i) 10111 (ii) 01101. (Ans. – 7.1875 V, – 4.0625 V) What is the step size (or resolution in volts) of a 10 bit D/A converter, if the full scale output is +10 volts? Find the percentage resolution also. (Ans. 9.78 mV, 0.0978%) How many bits are required at the input of a D/A converter to achieve a resolution of 15mV, if the full scale output is 15 volts? (Ans. 10 bits) Give the details of D/A converter IC 0808. Using this IC draw a circuit diagram to get the analog output voltage corresponding to 8 bit digital input. Describe how the interfacing of the D/A converter is done with the microprocessor 8085A. Give its circuit diagram. Discuss the simultaneous A/D converter to convert 0 to V volts analog voltage to 3 bit digital output. Draw the logic diagram also. What are the disadvantages of this type of A/D converter? Give the details of the microprocessor compatible D/A converter IC AD558. Draw a logic diagram to convert 0 to V volt analog voltage to its equivalent 2 bit digital output using simultaneous A/D converter.

421

21. 22. 23. 24. 25. 26. 27. 28.

29.

30. 31. 32.

33.

Describe the successive approximation method for A/D conversion. Draw a schematic diagram of counter or digital ramp type A/D converter. Explain its operation. Describe the modified counter or digital ramp type A/D converter with neat diagram. Draw a schematic diagram of a D/A converter. Explain its operation. Describe single slope A/D converter with it logic diagram. Mention its merits and demerits. Describe Dual slope A/D converter with it logic diagram. Give the details of A/D converter IC 0801. The input bits of the D/A converter is connected to the output pins of Port A of 8255, which is already connected with the microprocessor (ref. fig.13.13). Write a program to generate stair case voltage with ten steps. It should have the constant pulse duration. Write a program to generate square wave of 2 KHz frequency with a peak voltage of 2.5 volts. Use D/A converter (ref. fig. 13.13) for this purpose. The square wave should be available at the output of the converter. Give the details of A/D converter IC ADC0808/0809. Using this IC draw a circuit diagram to get the digital value of the input analog voltage. Describe how the interfacing of the A/D converter is done with the microprocessor 8085A. Give its circuit diagram. Write a program to get the digital output of an analog signal applied to ADC 0808/0809 interfaced with the 8085A. The input analog signal is applied to the channel 3 of this IC. Explain how the A/D converter can be designed using D/A converter and the software. For this purpose the software is used to implement successive approximation A/D converter. __________

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14 Serial Communication and Programmable Communication Interface In continuation to the series of interfacing devices, the discussion will now be made on serial data communication and programmable communication interface, since the serial data transmission is always preferred for long distance transmission. Though the serial data transmission can be made through the SID (serial input data) and SOD (serial out data) lines of 8085A microprocessor, but it requires suitable software for the data transfer. Moreover, most of the microprocessors do not have the provision of SID and SOD lines. Apart from this, it can not offer high baud rate. Hence this chapter will deal the detailed discussion on serial communication and most powerful programmable communication interface IC 8251. 14.1 SERIAL DATA COMMUNICATION There are two types of data communication, Parallel and Serial data communications. In parallel data communication each bit of a word is to be transmitted on a separate line along with a common ground line. In the 8085A microprocessor the data to be transmitted is of 8 bits. This parallel data transmission is not recommended for long distance communication as large number of data lines is needed. In serial data transmission, data is transmitted bit by bit either from the microprocessor to I/O devices or vice-versa. There are certain input/output devices in the microprocessor based systems, which only accept the serial data. The common I/O devices for such a data communication are CRT terminals, printers, cassette recorders etc. The microprocessors thus have the provision for transferring the data in the serial fashion. In such I/O devices, a parallel to serial conversion is required for the data transfer from the microprocessor to the peripheral device (figure 14.1a). Similarly, a serial to parallel conversion is required in transmitting the data from the peripheral device to the microprocessor (figure 14.1b). As already discussed, the 8085A microprocessor has the provision of SID and SOD lines for the serial data transfer between the microprocessor and I/O devices. But it requires the software. Moreover, most of the microprocessors do not have the provision of these SID and SOD lines. Apart from this, it can not offer high baud rate. So, serial data communication is generally used for the long distance communication with high baud rate. Further, it requires less number of lines for the data transmission.

(a)

(b) Fig. 14.1 The serial communication occurs either in the following two formats: • Synchronous • Asynchronous In synchronous format, a receiver and a transmitter are synchronized. In this format the data is divided into fairly large blocks, typically 1000s of bytes. A block of characters is transmitted along with the synchronization information. The synchronizing signals are added once before each block. The synchronization characters mark the beginning of the transmission. This format is generally used for high baud rate (more than 20 K bits/second). The baud rate is defined as the number of bits transmitted or received per second. Figure 14.2 illustrates this format.

Fig. 14.2 In asynchronous format, timing signals are added to each character of data. A START bit is added at the beginning of each character. A STOP bit is added at the end of the character data. A low signal is used for the START bit and a high signal is used for STOP bit. When no data is being transmitted, a receiver stays high, called MARK. The process of adding start and stop bits to a character is known as FRAMING. The asynchronous format is generally used for low speed transmission. This format is illustrated in figure 14.3.

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Fig. 14.3 The serial mode of data transfer can be divided into three groups namely: Simplex Method Duplex Method Half Duplex Method In simplex method data transfer takes place in unidirectional i.e. either from the system to the I/O devices or from I/O devices to the system, of course through the serial link. A typical example is the transmission from a system to a printer. In the duplex method data transfer takes place in both the directions. However, if the transmission goes one way at a time, it is called half duplex; if it goes both ways simultaneously, it is called full duplex. The walkie talkie is an example of half duplex and the communication between the computers is an example of full duplex. 14.2 MODEM One of the most common applications of the serial transmission would be data transmission between large computers. For such serial digital transmission the existing telephone lines are used. The telephone lines are designed to carry analog signals in the range of 40 Hz to 4 KHz. These lines will not readily support digital signals. Therefore, the digital data is to be converted into audio frequency format. A device that can convert the digital value in the form of the audio signal has to be used because the basic binary bits can not be placed directly on these lines. Such a device is known as MODEM (MODULATOR- DEMODULATOR). The modem is be used at both the ends; at the

Fig. 14.4 425

receiving end as well as at the transmitting end. The modem at the transmitting end converts digital signal into analog signal format (audio frequency range) and at the receiving end the modem converts audio signal back to the digital data.

Fig. 14.5 Modems often use frequency shift keying technique for the conversion. It converts a 1 level signal into an audio signal of 1200 HZ and 0 level into audio signal of 2200 Hz. These converted audio signals are modulated on the carrier and then transmitted to the telephone lines. However at the receiving end another modem is used to convert the audio signal back to digital form. Figure 14.4 shows the block diagram of such transmission system. The originators and receptors of the digital data are called Data Terminal Equipments (DTE) and the modem units are called Data Communication Equipments (DCE). Figure 14.5 shows the modem connections using telephone lines. 14.3 SERIAL COMMUNICATION STANDARD There are primarily two standards for transmitting the information in serial form. All the serial I/O devices work on either of these standards. • Current Loop • Voltage standard In a current loop method, the current flows through the lines for the logic 1 and no current flow for the logic 0. The two standards for the current loop are: 20 milliampere loop 60 milliampere loop. A current loop reduces noise pickup and is suitable for long distance transmission. The other standard is the voltage signal. When the data is transmitted as voltage, the commonly used standard is known as RS 232C. It is defined in reference to DTE (Data Terminal Equipment) and DCE (Data Communication Equipment) – terminal and Modem as shown in figure 14.6, which illustrates the connections of DTE to DCE. This standard was developed before the existence of TTL logics; its voltage levels are not compatible with TTL logic levels.

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Fig. 14.6 RS 232C Figure 14.7 shows the RS 232C 25-pin connector. The signals are divided into four groups namely: • Data Signals • Control Signals • Timing Signals • Ground

Fig. 14.7 The pin assignments are given below: Pin 1: Protective Ground Pin 2: Transmitted Data (T x D) DCE Pin 3: Received Data (R x D) DTE Pin 4: Request to Send (RTS) DCE Pin 5: Clear to Send (CTS) DTE Pin 6: Data Set Ready DTE Pin 7: Signal Ground Pin 8: Received Line Signal Detector Pin 9: Reserved for Data Set Testing Pin 10: Reserved for Data Set Testing Pin 11: Unused Pin 12: Secondary Received Line Signal Detector Pin 13: Secondary Clear to send Pin 14: Secondary Transmitted Data Pin15: Transmission Signal Element Timing (DCE Source)

427

Pin 16: Pin 17: Pin 18: Pin 19: Pin 20: Pin 21: Pin 22: Pin 23: Pin 24: Pin 25:

Secondary Received Data Receiver Signal Element Timing (DCE Source) Unused Secondary Request to Send DCE Data Terminal Ready (DTR) Signal Quality Detector Ring Indicator Data Signal Rate Selector (DTE/DCE Source) Transmit Signal Element Timing (DTE Source) Unused Technically the RS232C has -3V to -12V for logic '1' and +3V to +12V for logic '0'. This is negative logic. Because of incompatibility with TTL logic, voltage translator called line drivers and line receivers are required to interface TTL logic with RS232 signals. As shown in figure 14.6, the minimum interface requires three lines: pins 2, 3 and 7. These lines are defined in relation to the DTE; the terminal transmits on pin 2 and receives on pin 3. On the other hand, the DCE transmits on pin 3 and receives on pin 2. The comparative study of synchronous and Asynchronous modes of data transfer to and from the serial I/O devices is given in table 14.1. Table 14.1 Serial Transmission Sr. No.

Format

Synchronous

Asynchronous

1. 2.

Data format Framing

Groups of characters Synchronous characters are sent with each group.

One character at a time. START and STOP bit/bits are sent with each character.

3.

Speed

High speed, 20 K bits/sec or more.

Low, Less than 20 K bits/sec.

4.

Distance for Recommended for long distance communication. communication.

Recommended for small distance communication.

5.

Implementation

Hardware.

Hardware or Software.

6.

Data direction

Simplex, half and full duplex.

Simplex, half and full duplex.

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The computer communicates with the serial I/O devices either in Asynchronous or Synchronous modes. Here the discussion will be made on the Asynchronous mode of serial data transfer, as it is both hardware and software implemented. 14.4 ASYNCHRONOUS SOFTWARE APPROACH In this case, the framing of each character is done by introducing START and STOP bits using the software. The data in parallel form is available with the microprocessor to be transmitted to serial I/O devices. The data is then converted to serial form using the software and sent to the serial I/O devices through an interfacing circuit. The interfacing circuit is to be designed for the microprocessor 8085A microprocessor is shown in figure 14.8. This circuit consists of D-type flip-flop (IC 7475) whose device address is chosen to be FF H. The address bus is decoded using an 8-inpout NAND gate (IC 7430), and combined with the control signal IOW to clock the latch. When the instruction OUT FF H is executed, the clock goes high and bit at the DIN terminal is transferred to output Q of the flip-flop. The bit is latched as the clock goes low. If the Q is high 20 mA current flows through the TTY (Tele Type) circuit.

Fig. 14.8 Let us consider, a message is to be transmitted to teletype (TTY) using the 8085A microprocessor. The interfacing circuit, shown in figure 14.8, is used for this transmission. The characters of the message are stored in the memory locations starting at 2101 H. Each character includes framing information (START and STOP bits). Each character has 11 bits for the transmission; 8 bits for ASCII character, one START bit and two STOP bits. .Let the first character of the message is W (ASCII code for W is 57 H). Figure 14.9 shows a stream of eleven bits for this first ASCII character of the message. The character bits are transmitted beginning with the least significant bit (LSB) D0. The

429

bit time, the delay between two successive bits, is determined by the transmission rate (baud rate).

Fig. 14.9 A typical (TTY) sends (or receives) 10 ASCII characters per second. If each character has 11 bits, then TTY transmits 110 bits/second. TTY transmission rate = 110 bits/second 1 sec Time for each bit = 110 = 9.1 msec. Therefore, microprocessor should send bit by bit information (including framing bits) to TTY to transmit the bit a time interval of 9.1 msec. For the transmission the necessary software for 8085A is given as: PROGRAM Label

NXT

Mnemonics LXI SP, LXI H,

Operand XXXX H 2101 H

MVI A, OUT

01 H FF H

MOV A,

M

CPI

0D H

MOV B, JZ

A END

430

Comments ; Initialize Stack pointer. ; Initialize H-L register pair for index pointer. ; Set up MARK bit as 1. ; Goes to the output of Flip-flop, whose address is FF H. ; Accumulator is loaded with the character of the message. ; Compare if the character is Carriage return (0D H is the ASCII Code of carriage return). ; Save the character in register B. ; If the character is Carriage return, jump to END.

CALL

SERIAL

; Else Call subroutine for converting into the serial form of the character. ; Point to next character of the message. ; Jump for next character. ; Call subroutine for converting into the serial form of the character ‘Carriage return’. ; Load the character of Line feed (0A H is the ASCII code for line feed). ; Transmit line feed serially. ; Stop Processing.

INX H

END

JMP CALL

NXT SERIAL

MVI B,

0A H

CALL HLT

SERIAL

SUBROUTINE PROGRAM: This is the subroutine for the conversion of bit of a character into serial form and then transmits to a TTY with a baud rate of 110. Label SERIAL

NXT1

Mnemonics MVI C,

Operand 08 H

MVI A, OUT

00 H FF H

CALL

DELAY

MOV A,

B

OUT CALL

FF H DELAY

RRC DCR C JNZ

NXT1

MVI A, OUT

01 H FF H

CALL

DELAY

431

Comments ; Load register C with 08 H, which is used as counter. ; Load START bit. ; Send the start bit at the output of the flip-flop. ; Call delay subroutine which introduces a time delay of 9.1 msec after START bit. ; Load the character into the accumulator from register B. ; Send the bit. ; Call delay subroutine which introduces a time delay of 9.1 msec between each bit. ; Rotate right for the serial conversion. ; Decrement C. ; If rotated 8 times then jump to NXT1. ; Introduce STOP bit. ; STOP is sent to the output of the flip-flop. ; Call delay subroutine which introduces a time delay of 9.1 msec.

CALL

DELAY

; Call delay subroutine which introduces a time delay of 9.1 msec. RET ; Go back to main program. Delay Program may be written for the time delay of 9.1 msec. Similar, circuit and software may be used for the reception of the messages in the serial fashion. The RIM and SIM instructions can also be used for the transmission and reception of data in serial fashion. 14.5 PROGRAMMABLE COMMUNICATION INTERFACE Many types of UART (Universal Asynchronous Receiver Transmitter) and USART (Universal Synchronous/Asynchronous Receiver Transmitter) have been developed for data transfer between serial I/O device and the microcomputer in the form of the chips. The USART is most powerful and commonly used LSI chip. It provides a programmable serial communication interface between the microprocessor and serial I/O devices. The data transfer between the microprocessor and USART takes place in the parallel form. On the other hand the data transfer between the I/O devices and the USART is in the serial form. The USART has to be initialized before the data transfer takes place. The desired data format and synchronization method for the data transfer are specified during initialization by command byte written by the microprocessor for the USART. Thus an USART works as parallel to serial converter from microprocessor to I/O devices and vice-versa. Here we shall discuss the details of the popular USART chip 8251. 14.6 BLOCK DIAGRAM OF 8251A The 8251A is a programmable communication interface available in the form of IC dual in line package. It consists of 28 pins and requires + 5 V d.c. supply for its operation. Figure 14.10 shows the pin diagram of 8251A. The pin details are as given below: D0-D7 Data bus (8 bits) Receiver Clock RxC Receiver Data Control or data to C/ D RxD be written or read Receiver Ready RxRDY Read Data Transmitter Ready RD TxRDY Command Data Set Ready DSR Write Data or Data Terminal Ready WR DTR Control Command Sync/Break Detect SYNDET/BD Request to Send Data CLK Clock Pulse (TTL) RTS Chip Enable Clear to Send Data CS CTS RESET RESET Input Transmitter Empty TxE Transmitter Clock VCC +5V TxC Transmitter Data GND Ground TxD

432

Fig. 14.10 The functional block diagram of 8251A is shown in figure 14.11. It includes the following four sections: • • • • 14.6.1 Read/Write Control Logic

Read/Write Control Logic Transmitter Section Receiver Section Modem Control

This section includes 6-input signals: CS , C / D , WR , RESET and CLK; and three buffer registers: • • •

Control Register Status Register Data Bus Buffer Register

:

It is a Chip Select terminal. A low to this terminal selects the 8251A for communication with the microprocessor. This is connected to a decoded address bus.

C/D :

It is a Control/Data pin. A high on this terminal addresses the control register or status register; whereas a low addresses the data bus buffer.

:

It is an active low Write signal. When a low signal is applied to this terminal, the microprocessor either writes in the control word register or

CS

WR

433

sends output to the data buffer. This pin is connected to either IOW or MRMW .

Fig. 14.11 It is an active low Read signal. When this terminal is low, the microprocessor either reads the status from the status register or accepts data from the data buffer. This is connected to either IOR or MEMR . RESET : It is a Reset input pin. When this terminal is high, it resets the 8251 and forces it in the idle mode. CLK : This is the Clock input, usually connected with the system clock. The details of the three registers are as: Control Register: This is a 16-bit register and contains the control word with two independent bytes. The first byte is called the Mode Instruction Word, and the second byte is called the Command Instruction Word. RD

:

This register can be accessed as an output port when C / D pin is high. Status Register:

434

This input register checks the Ready status of a peripheral. This register is addressed as an input port when C / D terminal is high. It has the same port address as the control register. Data Bus Buffer Register This is a bidirectional register and can be addressed as an input port and an output port when C / D pin is low. Table 14.2 gives the summary of interfacing and control signals. Table 14.2

CS 0 0 0 0 1

C/D

RD

WR

Functions

1 1 0 0 X

1 0 0 0 X

0 1 1 1 X

Microprocessor writes instruction in USART control register. Microprocessor reads from USART status register. Microprocessor outputs data to USART data buffer. Microprocessor accepts data from USART data buffer. USART not selected.

Figure 14.12 shows the expanded version of this section.

Fig. 14.12

435

14.6.2 Transmitter Section The expanded block diagram of the transmitter section is shown in figure 14.13. It consists of the following registers: • Transmitter Buffer Register – It holds 8-bit data. • Serial Output Register – Converts 8-bits into a stream of serial bits. • Transmitter Control Logic – It directs the output register to send the serial data at the output register through TxD terminal. Three output signals and one input signal are also associated with the transmitter section. These signals are describes as: It is Transmit Data terminal. The serial bits are transmitted on this TxD : line.

TxC :

TxRDY :

TxE :

This pin is Transmitter Clock. This controls the rate at which bits are to be transmitted by the 8251A. The clock frequency can be 1, 16 or 64 times of the baud. This is Transmitter Ready pin. When this output terminal is high, it indicates that the buffer is empty and the 8251 is ready to accept a byte. It can be used either to interrupt the microprocessor or to indicate the status. This signal becomes reset when the data byte is loaded into the transmitter buffer register. This is Transmitter Empty signal used as output terminal. A high on this terminal indicates that the output register is empty and becomes reset when a byte is transferred from the buffer register to the output register.

Fig. 14.13

436

14.6.3 Receiver Section The expanded block diagram of the receiver section is shown in figure 14.14. It consists of the following registers: • Receiver Buffer Register • Serial Input Register • Receiver Control Logic The receiver section accepts serial data on the RxD terminal and converts it to parallel data. When the RxD line goes low, the control logic assumes that it is a START bit and waits for half a bit time, and samples the line again. It the line is still low, the input register accepts the next coming bits and forms a character. The character is then loaded to the buffer register. Subsequently, the parallel byte is transferred to the microprocessor when a request is made. Following signals are associated with the receiver section which are described below: It is Receive Data terminal. The serial bits are received on this line RxD : and converted to a parallel byte in the receiver input register.

RxC :

RxRDY :

This pin is Receiver Clock. This controls the rate at which bits are received by the 8251A. In the asynchronous mode, the clock can be set to 1, 16 or 64 times of the baud. This is Receiver Ready pin. When this output terminal is high, the 8251A has a character in the buffer register and is ready to transfer it to the microprocessor. It can be used either to indicate the status or to interrupt the microprocessor.

Fig. 14.14 14.6.4 Modem Control

437

The modem control section of the 8251A provides two input signals DSR (Data Set Ready) and CTS (Clear to Send); and two output control signals DTR (Data Terminal Ready) and RTS (Request to Send) to handle DTE and DCE. These signals are described as:

DSR (Data Set Ready):

This is an active low input terminal used by the modem to indicate that it is ready for communication.

CTS (Clear to Send):

This active low input terminal is used by the modem to signal the DTE that the communication channel is clear and it can send out the serial data. DTR (Data Terminal Ready): This output signal is used by the 8251 to signal the modem to indicate that the terminal is ready to communicate. This output signal is used by the 8251A to signal to RTS (Request to Send): modem that it has data to be transmitted. 14.7 INTERFACING OF 8251A Figure 14.15 shows the interfacing connection of 8251A with the microprocessor. The eight data lines of 8251A are to be connected to the data bus of the microprocessor.

Fig. 14.15

438

The RD and WR lines of 8251A are to be connected to the RD and WR of the control lines of 8085A microprocessor respectively. The CLK pin of the 8251A is be connected to the CLK out terminal of the microprocessor. The RESET pin is connected to the RESETOUT of the microprocessor. The terminal C / D is used to select the internal registers either control register or data register. So it is connected to the A0 address line of the microprocessor. The chip select terminal CS of the PCI 8251A is to be connected to the output of an address decoder circuit. The address decoder circuit uses the address lines A1 to A7 of the microprocessor. From the decoder circuit used in this figure, the chip select terminal of 8251A will be enabled when A7 and A4 are high and all other inputs are low. The port addresses for reading the data word, writing the data word, reading the status word and writing the control word will be as shown in table 14.3. Table 14.3 A0

RD

WR

Function

Port Address

0 0 1 1

0 1 0 1

1 0 1 0

Read Data Word Write Data Word Read Status Word Write Control Word

90 H 90 H 91 H 91 H

14.8

PROGRAMMING OF 8251A It has already been discussed that there is a 16 bit control register in a 8251A which contains two independent bytes (words). The first byte (word) is known as mode word which tells about the initialization parameters like mode (Asynchronous or Synchronous), baud, stop bits and parity bits etc. The second byte (word) is known as command word which tells about enabling the transmitter and receiver sections. The readiness of the peripherals can also be checked by reading the status word. 14.8.1 Initialization of 8251A in Asynchronous Mode To initialize 8251A in asynchronous mode, a certain sequence of control words must be followed. After a reset operation (through system RESET or through instruction) a mode word must be written into the control register followed by a command word. Any control word written into the control register immediately after the mode word will be interpreted as a command word that means a command word can be changed anytime during the operation. However, the 8251A should be reset prior to writing a new mode word, and it can be reset using internal reset bit (D6) in the command word. Figure 14.16 shows the format of the mode word. The bits of this mode word are described below: Bits D1-D0: These bits program the baud rate factor. These bits are set to 00 for synchronous operation. However, for asynchronous operation these bits specify the factor by which the transmit/receive clocks TxC and RxC , exceeds the baud rate. The other clock inputs CLK to the 8251A is used to generate the internal device timing and must simply be greater than 30 times the transmitter/receiver baud rate. 439

Bits D3-D2: Bit D4: Bit D5:

Fig. 14.16 These bits specify the number of data bits in the character is to be sent or received. This bit enables the parity. If this bit is 0, the parity is disabled. This bit selects the even or odd parity. If this bit is 0, odd parity is selected. The even parity is selected if this bit is 1. These bits specify the number of stop bits.

Bit D6-D7: Command Word Once the function definition of the 8251A has been programmed by the mode word instruction, the device is ready for data communication. The command word 440

instruction controls the actual operation of the selected format. Functions such as Enable Transmit/ Receive, Error Reset and modem control are provided by the command word instruction. The format of the command word is shown in figure 14.17.

Fig. 14.17 The bits of the command word are described below: Bit D0: This bit enables the Transmitter. Bit D1: This bit controls the Data Terminal Ready. Bit D2: This bit enables the Receiver. Bit D3: This bit makes the transmitter to send continuous break characters.

441

Bit D4: Bit D5:

Bit D6: Bit D7:

This resets the error flags. It resets Parity Error flag (PE), Over Run Error flag (OE) and Framing Error flag (FE). This bit controls the request to send to RTS pin of the device. A high at this bit makes the RTS pin to become active. It is used as an internal reset. A high to this bit resets the device, so that a new mode word can be entered. It is used in synchronous mode. It enables the receiver to look for the synchronous data.

Programming Sequence When programming the 8251A in asynchronous mode, following sequence must be followed: 1. Reset (either internal or external) 2. Mode Instruction (specify the asynchronous mode) 3. Command Instruction The resetting of the 8251A can be done by loading the control register with a command word whose D6 bit is high. This bit reset the device. The command word is, therefore, loaded as: MVI A, 40 H ; Command word whose D6 bit is high is loaded to accumulator. OUT 91 H ; Command word is loaded to control register whose port address is 91 H as discussed earlier. Now the mode instruction word is loaded to the control register. The mode word is formed as per the required modes of transmission. For example, for asynchronous transmission with 7 data bits, 2 stop bit and odd parity; also a 16 X clock is used. For this the format is shown in figure 14.18 and mode word will be given as:

Fig. 14.18 MVI A, DA H ; Mode word is loaded to accumulator. OUT 91 H ; Mode word is loaded into control register. The command word with RTS, error reset and DTR enable with be given as shown in figure 14.19.

442

Fig. 14.19 The command word to be loaded in the control register is given below: MVI A, 37 H OUT 91 H

; Command word is loaded to accumulator. ; Command word is loaded into control register. For initializing the 8251A a dummy mode is sent before resetting it. The resetting is done using command word with D6 bit as 1. The mode word followed by the command word is sent. With all these requirements the initialization program of 8251A is writhen as: MVI A, 00 H OUT 91 H ; Dummy mode word. MVIA, 40 H ; Resetting of 8251A by using the command word with D6 bit as high. OUT 91 H MVI A, DA H ; Mode word is loaded to accumulator. OUT 91 H ; Mode word is loaded into control register. MVI A, 37 H ; Command word is loaded to accumulator. OUT 91 H ; Command word is loaded into control register.

14.8.2 Initialization of 8251A in Synchronous Mode When programming the 8251A in asynchronous mode, following sequence must be followed: 1. Reset (either internal or external) 2. Mode Instruction (specify the Synchronous Mode and number of synchronizing characters)

443

3. One or two synchronizing character 4. Command Instruction For initializing of the 8251A in synchronous mode the mode instruction word is to be written only after resetting the PCI as in the case of asynchronous mode. Then with one or two sync characters, a command word is written in the control register. The mode word format in synchronous operation is shown in figure 14.20. As discussed earlier the D1 and D0 bits program the baud rate factor which are set 00 for synchronous operation.

Fig. 14.20 The format to be used for command instruction format for the synchronous operation is the same as for the asynchronous operation which is shown in figure 14.21. Once the functional definition of the 8251A has been programmed by the mode instruction and the Sync characters are loaded (in synchronous mode) then the device is ready to be used for data communication. The command instruction controls the actual operation of the selected format. Functions such as Enable Transmit/ Receive, Error Reset etc are provided by the command instruction. Once the mode instruction has been written into the 8251A and Sync characters inserted, then all further “control writes” ( C / D = 1 ) will load a command instruction. A reset operation (internal or external) will return the 8251A to the mode instruction format.

444

Fig. 14.21 In data communication system, it is necessary to examine the status of the active device to ascertain if errors have occurred or other conditions that require the processor’s attention. The 8251A has facilities that allow the programmer to read the status of device at any time during functional operation. A normal read command is issued by the CPU with C / D = 1 to accomplish the function. The microprocessor can output the data to be transmitted only after checking the status TxRDY (D0) bit of status word as shown in figure 14.22. The sync characters will automatically be inserted if the buffer of the transmitter becomes empty at any time.

445

Fig. 14.22 Example 14.1 Write a subroutine program to transmit serially 256 bytes of data stored in the memory locations starting at 3000 H. The bytes are to be transmitted in synchronous mode (without parity) with two sync characters using 8251A. Consider 90 H and 91 H are the port addresses for control/status register and data register respectively. Solution. The mode word format for the given problem is shown in figure 14.23.

446

Fig. 14.23 The subroutine program may then be given as: SUBROUTINE PROGRAM Label

STATUS

Mnemonics LXI H,

Operand 3000 H

MVI C, MVI A, OUT MVI A,

FF H 00 H 91 H 40 H

OUT

91 H

MVI A,

0C H

OUT

91 H

IN ANI

90 H 01 H

JZ

STATUS

MOV A,

M

OUT DCR

91 H C

JNZ

STATUS

RET

447

Comments ; Initialize H-L register pair for index pointer. ; Register C to be used as counter. ; Dummy word ; Command word for resetting 8251A. ; Command word loaded to the control register. ; Mode word 0C H is loaded to the accumulator. ; The mode word for two sync character is loaded to the control register. ; Read the status word. ; Mask all the bits except D0 for checking the status. ; If D0 bit is zero jump to STATUS to read again. ; Loads the character to be transmitted to the accumulator. ; Character is transmitted. ; Decrements the data in C register for next byte for transmission. ; If all bytes are not transmitted then jump to STATUS to read the next byte. ; Returns to main program.

PROBLEMS 1. 2. 3. 4. 5. 6. 7. 8.

9. 10. 11. 12. 13. 14.

What are the advantages and disadvantages of serial I/O data transfer over the parallel I/O data transfer? Name three methods of serial mode of data transfer and explain them in brief. Draw and explain the block diagram of Programmable Communication Interface 8251A. Discuss the Transmission section of 8251A. Discuss the Receiver section of 8251A. Explain the working principle of RS 232 interface. Explain how Programmable Communication Interface 8251A is interface with the CPU. Draw the schematic diagram of interfacing 8251A with 8085 microprocessor. The connections should be such that the port address for control register and data registers are 71 H and 70 H respectively. Explain the mode word format of 8251A. Explain the command word format of 8251A. Explain how the 8251A is initialized in Asynchronous mode. Explain hoe the 8251A is initialized in synchronous mode. Explain the following terms related to 8251A: C / D , RxC , RxD , DSR , TxC , TxD , DTR , CTS Explain the following terms related to 8251A: RxRDY , TxRDY , TxEMPTY

_________

448

15 Applications of Microprocessor After the study of all the details of microprocessor 8085, including the assembly language programming and peripheral devices we are now in a position to design some microprocessor based systems. Real time clock with on/off timer, running light, washing machine control, water level control etc. are some designs will be discussed in this chapter. These designs are supposed to be very interesting and useful. The assembly language programming of these designs have been verified on M/S Vinytics Kit 15.1

REAL TIME CLOCK WITH ON/OFF TIMER

In the present section of this chapter, the details of the assembly language programming of the design of Real Time Clock with On/Off Timer will be discussed. In this microprocessor based design six FNDs of the microprocessor kit (four of address field and two of data field) have been used to display the current time. The four 7segments of the address field would display hours and minutes of the current time and two 7- segments of data field would display the seconds of the current time. For example, current time is 10:25:30, the address and data field of the kit would display as shown in Fig. 15.1. It would then continuously update the current time after every second. In other words, it will work as the real time clock (digital clock).

Fig. 15.1

For the working of real time clock, the software prepared was checked on the Vinytics kit (VMC-8506) and found to work satisfactorily. Two monitor programs (stored in Kit’s ROM /EPROM) at the locations 0347 H (for clearing the display) and 05D0 H (displaying the contents of memory of memory locations 2050 H through 2055 H in the address and data fields respectively) have been used in the program. Please note that before calling the display routine, registers A and B are required to be initialized with either 00 or 01 to indicate to the monitor program as to where the contents of above mentioned memory locations are to be displayed (e.g. address field or data field) and whether a dot is to be displayed at the end of address field or not. The assembly language program was executed to switch ON an electrical appliance after a preset time period. This program was proved to be very useful microprocessor based system. This type of microprocessor based system has the useful requirement in research laboratories. An electronic circuit was also designed which was interfaced with the 8085A microprocessor through the programmable peripheral Interface (PPI) 8255A. The PPI-8255A was available with the microprocessor kit.

ASSEMBLY LANGUAGE PROGRAM The assembly language program for the universal timer and for switching ON electrical device is given below: PROGRAM

Main Program Label

AA

Mnemonics

Operand

Comments

LXI SP, MVI A, OUT

27FF H 80H 03H

CALL

0347 H

XRA MOV B,

A A

;Initialize Stack Pointer. ;Control word for 8255-I. ;Work all the ports of 8255-I as output port . ;Clears the display. It is the program stored in ROM of the kit. ;Clears the accumulator ;Clears the B register also.

450

DD YY

RR

LXI H,

2050 H

CALL

05D0 H

MVI A, MVI B, LXI H,

01 H 00 H 2054 H

CALL

05D0 H

CALL

ONOFF

LXI H,

2055 H

MOV A,

M

ADI CPI JZ

01 H 0A H RR

MOV M,

A

MVI B, LXI D,

02 H FA00 H

CALL DCR JNZ JMP

DELAY B YY AA

MVI A,

00 H

MOV M,

A

451

;Intialize H-L pair where the current time is stored. ;Displays the current time in address field. It is the program stored in ROM of the Kit. ;Stores 01 H in accumulator. ;Stores 00 H in B register. ;Initialize H-L register pair with 2054 H. :Displays the current time in data field. ;Calls subroutine program to switch on the electrical appliance. ;Initialize H-L register pair with 2055 H. ;Moves the least significant digit (LSD) of current seconds to the accumulator. ;Add 01 to the accumulator. ;Compares with 0A H. ;If Acc.=0A H, then jump to RR, indicating that LSD of seconds has become 9. Else goes to next statement. ;Moves the accumulator contents to memory location addressed by H-L register pair i.e. current seconds are stored back in the memory locations. ;Stores 02 H in accumulator. ;Intialize D-E register pair with FA00H. ;Calls the delay program. ;Decrement B- register. ;If B≠0 then jump to YY. ;Jump to AA for the display of current time. ;LSD of current time becomes 0, which is stored in accumulator. ;Stores it to the memory location of LSD of seconds

UU

VV

DCX

H

MOV A,

M

ADI CPI

01H 06 H

JZ

UU

MOV M,

A

JMP MVI A MOV M,

DD 00 H A

DCX

H

MOV A,

M

ADI

01 H

CPI JZ

0A H VV

MOV M,

A

JMP MVI A, MOV M,

DD 00 H A

DCX

H

whose address is given in H-L register pair. ;Decrement H-L register pair. ;Moves MSD of the current second to accumulator. ;Add 01 H to it ;Compaers if MSD of the current seconds is 06. ;If Acc.=06 then jump to UU, indicating that MSD of seconds has become 6. Else goes to next statement. ;If A≠06 then stores to the memory location addressed by the H-L register pair. ;Jump to DD for 1 sec.delay. ;Store 00 to accumulator. ;Stores 00 to the memory location of MSD of seconds addressed by the H-L register pair. ;Decrement H-L register pair. ;Moves the LSD of the current minutes to accumulator. ;Add 01 H to the LSD of the current minutes. ;Compares it with 0A H. ;If LSD of minutes is 0A H, then jump to VV else to the next instruction. ;Stores it to the memory location of LSD of minutes addressed by H-L register pair. ;Jump to DD for 1 sec delay. ;Stores 00 H to accumulator. ;Stores 00 to the memory location of LSD of minutes addressed by H-L register pair. ;Decrement H-L register pair.

452

SS

LL

MOV A,

M

ADI

01 H

CPI

06 H

JZ

SS

MOV M,

A

JMP

DD

MVI A MOV M,

00 H A

DCX

H

MOV A,

M

ADI

01 H

* CPI JZ

03 H LL

MOV M,

A

CPI JZ

0A H WW H

MOV M,

A

JMP

DD

DCX

H

;Moves the MSD of the current minutes to accumulator. ;Add 01 H to the MSD of the current minutes. ;Compaers if MSD of the current minutes is 06. ;If Acc.=06 then jump to SS, indicating that MSD of minutes has become 6. Else goes to next statement. ;If Acc≠06 then stores to the memory location addressed by the H-L register pair. ;Jump to DD for delay of 1 sec. ;Store 00 to accumulator. ;Stores 00 to the memory location of MSD of minutes addressed by the H-L register pair. ;Decrement H-L register pair. ;Moves the LSD of the current hrs. to accumulator. ;Add 01 H to the LSD of the current hrs. ;Compares it with 03 H. ;If LSD of hrs is 03 H, then jump to LLelse to the next instruction. ;Stores it to the memory location of LSD of hrs. addressed by H-L register pair. ;It is also compared by 0AH. ;If it is 0A H, then jump to EE else go to next instruction. ;Stores it to memory locations addressed by H-L register pair. ;Jump to DD for delay of 1sec. ;Decrement H-L register pair.

453

MOV A,

** CPI JZ

WW

;Moves the contents of memory location addressed by H-L register pair to Acc. ;Compares it with 01 H. ;If it is 01 H, then jump to GG H. ;Increment the H-L register pair. ;Moves the contents of MH-L to the Acc. ;Add 01 H to it. ;Compares it with 0A H. ;If it is 0A H then jump to WW. ;Else stores the accumulator contents in MH-L. ;Jumps to DD for the delay of 1sec. ;Stores 00 H to Acc. ;Moves 00 H to the memory location addressed by H-L register pair. ;Increments the H-L register pair. ;Loads Acc. to 01 H. ;Moves the Acc. Contents to MH-L. ;Jumps to DD for the delay of 1sec. ;Stores 00 H to accumulator. ;Stores it to MH-L. ;Decrements the H-L register pair. ;Moves MH-Lto accumulator. ;Add 01 H to it. ;Acc. Contents are loaded to MH-L. ;Jump for delay of 1sec.

01 H GG

INX

H

MOV A,

M

ADI CPI JZ

01 H 0A H WW

MOV M,

A

JMP GG

M

DD

MVI A, MOV M,

00 H A

INX

H

*** MVI A, MOV M,

01 H A

JMP

DD

MVI A, MOV M, DCX

00 H A H

MOV A, ADI MOV M,

M 01 H A

JMP

DD

Delay Subroutine Program Label

Mnemonics

Operand

DELAY

DCX

D

Comments ;Decrement D-E register pair.

454

MOV A,

D

ORA

E

JNZ

DELAY

RET

;Moves the contents stored in MD-E to Acc. ;The contents of A and E registers are ORed bit by bit. ;If the result is not zero then jump to DELAY else next instruction. ;Return to main program.

Subroutine Program to check the time (ON time) after every second Label

Mnemonics

Operand

Comments

ONOFF

LXI H,

2055 H

LXI D,

205C H

MVI B, LDAX D

06 H

CMP RNZ DCX

M H

DCX

D

DCR

B

JNZ MVI A,

AGAIN 01 H

;Initialize H-L register pair with 2055 H. ;Initialize D-E register pair with 205C H. ;Stores 06 H to B-register. ;Loads the contents of MD-E to the accumulator. ;Compares it with MH-L. ;Return if not zero. ;Decrements H-L register pair. ; Decrements D-E register pair. ;Decrements the contents of B-register. ;Jump if not zero to AGAIN. ;Stores 01 H to Acc.

OUT

00 H

AGAIN

:D0 bit of port A of 8255 becomes high to energies the relay (to switch on the appliance). ;Returns to main program.

RET DATA 2050 H

-

MSD of hrs.

2051 H

-

LSD of hrs.

2052 H

-

MSD of Minutes

2053 H

-

LSD of Minutes

2054 H

-

MSD of Seconds

2055 H

-

LSD of Seconds

Current Time

455

2056 H

-

01H (if wish to switch ON the electrical appliance)

2057 H

-

MSD of Hrs.

2058 H

-

LSD of Hrs.

2059 H

-

MSD of Minutes

205A H

-

LSD of Minutes

Time For On Electrical

205B H

-

MSD of Seconds

Appliance

205C H

-

LSD pf Seconds

This program written in assembly language is self-explanatory. The comment column will help in understanding the operation of the project. The current time is stored in the beginning before the start of the program in the memory locations starting at 2050 H to 2055 H. In the memory location 2056 H, 01H is stored if we wish to switch on the electrical device connected with the PPI-8255 A; otherwise any number can be stored in this memory location. If 01H is stored in the memory location 2056H, then the time for switching ON the electrical appliance is stored in the memory location starting at 2057 H to 205C H. Suppose current time, when we wish to start the program is: Hrs.

Min.

Sec.

02

25

30

And we wish to switch on the electrical appliance at: Hrs.

Min.

Sec.

04 23 00 The data to be stored in the memory locations starting at 2050 to 205C is given below: Memory Location Data 2050 H 2051 H 2052 H 2053 H 2054 H 2055 H 2056 H

00 H 02 H 02 H 05 H 03 H 00 H 01 H

2057 H 2058 H 2059 H 205A H 205B H 205C H

00 H 04 H 02 H 03 H 00 H 00 H

02 Hrs. 25 Minutes

Current Time

30 Seconds 01 for switch ON the appliance 04 Hrs. 23 Minutes 00 Seconds

456

Time when electrical appliance to ON

A relay circuit to be connected to the Programmable Peripheral Interface IC 8255I is shown in Fig. 15.2.

Fig.15.2

This circuit consists of a relay, a diode and transistor. The base of the transistor is connected to PA0 of 8255 although a 10 k resistance. A diode IN4007 is connected in parallel with coil of 12V relay. The electrical appliance is connected to the a.c.mains through the N/O pins of the relay. The working of this circuit may be explained as: When a high signal is available through the software to a PA0 (D0 bit of port A) of 8255-I, the transistor goes into saturation. The relay is energized. The N/O terminals of the relay get connected and electrical appliance become ON. When the program is executed, the current time is displayed in the address and data fields of the microprocessor kit. The current time is updated after every second by the programming. For this LSD (Least significant Digit) of the seconds is transferred to accumulator, which is added with 1. The contents after addition are compared with 0A H (decimal number 10). In other words LSD of the second is continuously increased (after every one second) by 1 to reach to 0A H. When it reaches to 0A H then program will jump to MSD (Most Significant Digit) of the seconds after storing 00H in the memory location 2050 H.

457

Now MSD of the second is moved into accumulator and then increased by 1 which then compared with 06H. When MSD of the second reaches to 06H, it will make 00H to its corresponding location. The program will then jump to LSD of the minutes. The program will execute in such a way the minutes will be checked after every one minute and it will be updated in the address field so that it displays up to 59H. After that, it becomes 00 H. In the similar fashion, Hrs. will be checked after every hour so that it displays the updated current time. To switch ON the electrical appliance at the predetermined time the subroutine program was developed. The subroutine program is executed after every second to check if the current time is equal to the time when the electrical appliance is to switched ON. When the current time is equal to the ON time (required time), 8255A sends a high signal to PA0 (D0 bit of Port A). The high signal energies the relay and appliance becomes ON. After switching ON the appliance the program will, however, continue displaying the updated time. The observations were made to check the ON time and found to work fine. The working of the real time clock was also very accurate. It was proved to be satisfactory assembly language programming of the 8085A. Further, to change the real time clock to display the timing in address and data field in 24 Hrs., i.e. after 12:59:59 it should display 13:00:00 onwards, rather than 01:00:00 onwards. So certain changes in the main program should be incorporated. The instructions marked by stars (*, **, ***) be replaced as given below: * Replace the instruction CPI 03 H by CPI 05 H ** Replace the instruction CPI 01 H by CPI 02 H *** Replace the instruction MVI A, 01 H by MVI A, 00 H. 15.2 MICROPROCESSOR BASED LED DIAL CLOCK Here the design of microprocessor based LED dial clock has been discussed which runs using microprocessor 8085. It works purely on the basis of the software; and some hardware has also been used. The software is prepared in the assembly language of 8085A microprocessor. This program was tested on Vinytics 8085 µp kit and found to work very fine. In this dial clock 73 LEDs are used which are interfaced with the different ports of two 8255 PPI ICs available on µp kit. Out of 73 LEDs, 12 LEDs of Amber color are used to show hours, 60 LEDs of red color are used to show minutes and one green LED alternately glows for half second showing that the seconds are continuously being counted by the clock. All these LEDs are connected in a circle in the form of a dial of a wall clock. The beauty of this project is the software part; and the students of Electronics discipline would definitely like to design this project or this idea may be used in other

458

projects also. It is worthwhile to mention that no electronic circuit was used, except the LEDs are connected to the two PPI-8255 ICs available with the microprocessor kit. Figures 15.3 and 15.4 show the circuit diagrams to be interfaced with the µp-Kit. The cathodes of all the 12 Amber colored Hours LEDs are connected to the ground. The Anodes of these LEDs are connected to the Port A and Port B of 8255 –II, the anodes of LEDs showing Hrs 1 to 8 are connected respectively to D0 –D7 Bits of Port A of 8255-II and the anodes of LEDs showing Hours 9 to 12 are connected respectively to D0 – D3 bits of Port B of 8255 – II. Look – up table 15.1 provides Logic 1 to Hours LEDs 1-8. However, logic 1 to Hours LEDs 9 – 12 are provided using the software. The bit D0 of Port C lower of 8255 – II is connected to the anode of Green LED (showing second) and cathode of this LED is also grounded.

Fig. 15.3 The minutes red colored 60 LEDs are divided into 6 Groups (Group 0 to Group 5) and each group contains 10 LEDs. The cathodes of each group are connected together. The D0 – D5 bits of Port B of 8255 – I are connected to the cathodes (Common Points) of Group 0 to Group 5 LEDs respectively. The ground signal is provided to the cathode pin of each Group through the software using Look up table 15.2. 459

Fig. 15.4 The anodes of 10 LEDs (1 to 10) of each of 6 Groups are connected in parallel, i.e. LED No. 1 of each Group is connected together, and similarly LED No 2 of each

460

Group is connected together and so on. In this way 10 different Anode leads (1 to 10 ) are finally available to be connected to different pins of Port A and Port C of 8255 – I. D0 – D7 bits of Port A of 8255 – I are connected to 1 – 8 Anodes leads and 9 – 10 Anode leads are connected to D0 – D1 bits of Port C of 8255– I respectively. Look up table III provides Logic 1 to 1 – 8 Anode Leads; and to the 9 – 10 Anode leads the Logic 1, is provided by the software.

Table –15.1 Memory Location

Data Stores

Binary Equivalent

Comments (Port A of 8255-II)

2101 H 2102 H

01H 02H

0000 0001 0000 0010

Provides Logic 1 to D0 bit (Hrs.1) Provides Logic 1 to D1 bit (Hrs.2)

2103 H 2104 H

04H 08H

0000 0100 0000 1000

Provides Logic 1 to D2 bit (Hrs.3) Provides Logic 1 to D3 bit (Hrs.4)

2105 H

10H

0001 0000

Provides Logic 1 to D4 bit (Hrs.5)

2106 H

20H

0010 0000

Provides Logic 1 to D5 bit (Hrs.6)

2107 H 2108 H

40H 80H

0100 0000 1000 0000

Provides Logic 1 to D6 bit (Hrs.7) Provides Logic 1 to D7 bit (Hrs.8)

Table – 15.2 Memory Location 2200 H 2201 H

Data Stores FEH FDH

Binary Equivalent 1111 1110 1111 1101

Comments (Port B of 8255 - I) Provides Logic 0 to D0 bit (Group 0) Provides Logic 0 to D1 bit (Group 1)

2202 H

FBH

1111 1011

Provides Logic 0 to D2 bit (Group 2)

2203 H

F7H

1111 0111

Provides Logic 0 to D3 bit (Group 3)

2204 H

EFH

1110 1111

Provides Logic 0 to D4 bit (Group 4)

2205 H

DFH

1101 1111

Provides Logic 0 to D5 bit (Group 5)

Table – 15.3 Memory Location

Data Stores

Binary Equivalent

Comments (Port A of 8255 – I)

2300 H

01H

00000001

Provides Logic 1 to D0 bit

2301 H 2302 H 2303 H 2304 H 2305 H 2306 H 2307 H

02H 04H 08H 10H 20H 40H 80H

00000010 00000100 00001000 00010000 00100000 01000000 10000000

Provides Logic 1 to D1 bit Provides Logic 1 to D2 bit Provides Logic 1 to D3 bit Provides Logic 1 to D4 bit Provides Logic 1 to D5 bit Provides Logic 1 to D6 bit Provides Logic 1 to D7 bit

461

The software provides a signal continuously to Green LED so that it remains ON and OFF alternately for half a second. The minutes 60 LEDs glow one by one after every one minute. Port B of 8255 – I provides a low voltage (0 volt) to the cathodes of one block for 10 minutes and to the anode of these LEDs (1 to 10) are provided positive voltage (logic 1) alternately for one minute through D0 – D7 bits of Port A and D0 – D2 bits of Port B of 8255 – I. However, Hours’ 12 Amber colored LEDs glow one by one after every an Hour time, as positive voltage (logic 1) is provided to the anodes of these LEDs after every an Hour. As discussed earlier positive voltage to Hours LEDs (1 to 8) are provided by D0 – D7 bits of Port A of 8255 – II and to Hours LEDs (9 to 12 ) are provided by D0 –D3 bits of Port B of 8255 – II after every an hour time. All the LEDs glow in a sequence as the minutes and hours hands move in an analog clock. The current time is stored in the beginning in some memory locations. Hours, minutes and seconds of the current time are stored in the memory locations say 2000 H to 2002 H respectively. Figures 15.5 show the flow chart of the program. The software in the assembly language of 8085A for providing appropriate signal to different LEDs is given below:

Main Program

MEMORY LOCATIONS WHERE CURRENT TIME IS STORED

Label

START

2000H

-

CURRENT HRS

2001H

-

CURRENT MINUTES

2002H

-

CURRENT SECONDS

Mnemonics

Operand

Comments

LXI SP, MVI A, OUT

XXXX H 80H 03H

OUT

0B H

LXI H,

2000 H

MOV A,

M

CPI

09 H

;Initialize Stack Pointer. ;Control word for 8255-I. ;Works all the ports of 8255I as output port ;Works all the ports of 8255II as output port. ;Loads the H-L register pair with the address of Hrs. of current time. ;Moves the Hrs. of current time to accumulator. ;It is compared with 09 H.

462

463

464

Fig. 15.5 JC

PT0

JZ

PT1

CPI

10 H

JZ

PT2

CPI

11 H

MVI A,

00 H

;If ACCT ? ; If yes then jump to LOOP1. ; Switch on the heater. ; PB0 is high. ; Jump to START.

PROBLEMS 1.

2. 3. 4. 5. 6. 7. 8.

9.

10. 11.

How will you design the digital clock on the microprocessor kit? Hours and minutes should be displayed on the address field and seconds should be displayed on the data field. Monitor programs of the kit may be used for the display of time. Write program in assembly language of 8085. Design the digital clock which can display the time in 24 hours form on the microprocessor kit. Write program in assembly language of 8085. In problem 1, on time should also be introduced. Write program in assembly language of 8085. Discuss the design of microprocessor based LED dial clock. Write program in assembly language of 8085. Discuss the design of microprocessor based running light in which some LEDs can run in a sequence. Write program in assembly language of 8085. Discuss the design of microprocessor based school bell system. Write program in assembly language of 8085. Discuss the design of microprocessor based Traffic light (simple arrangement). Write program in assembly language of 8085. Discuss the design of microprocessor based Traffic light (complicated arrangement) in which traffic is allowed in left-right direction also. Write program in assembly language of 8085. In the above design of microprocessor based traffic light, the delay time should also be displayed on the address and data field of the microprocessor kit. Write program in assembly language of 8085. Discuss the design of microprocessor based Stepper Motor controller. Write program in assembly language of 8085. Write program in assembly language of 8085 to control the different function of washing machine.

509

12.

13.

Discuss the water level controller which can pump out the water from the underground tank to the tank placed on the roof of the building. The motor of the pump should be switched on if the water level in the upper tank is less than certain level. The pump should be switched off when the water level in the upper tank is completely filled. Program for same should be written in assembly language of the 8085 microprocessor. Discuss the design of microprocessor based Temperature controller which can maintain the temperature of a device constant. Write program in assembly language of 8085.

____________

510

Appendix - I Instruction codes of 8085 Microprocessor in Alphabetical Order Mnemonics

Operand

ACI

Bytes

Data

Op code CE

2

TStates 7

Status CY AC Z S P x x x x x

Flags Affected All

ADC

A

8F

1

4

x

x

x

x

x

All

ADC

B

88

1

4

x

x

x

x

x

All

ADC

C

89

1

4

x

x

x

x

x

All

ADC

D

8A

1

4

x

x

x

x

x

All

ADC

E

8B

1

4

x

x

x

x

x

All

ADC

H

8C

1

4

x

x

x

x

x

All

ADC

L

8D

1

4

x

x

x

x

x

All

ADC

M

8E

1

7

x

x

x

x

x

All

ADD

A

87

1

4

x

x

x

x

x

All

ADD

B

80

1

4

x

x

x

x

x

All

ADD

C

81

1

4

x

x

x

x

x

All

ADD

D

82

1

4

x

x

x

x

x

All

ADD

E

83

1

4

x

x

x

x

x

All

ADD

H

84

1

4

x

x

x

x

x

All

ADD

L

85

1

4

x

x

x

x

x

All

ADD

M

86

1

7

x

x

x

x

x

All

ADI

Data

C6

2

7

x

x

x

x

x

All

Mnemonics

Operand

ANA

Bytes

A

Op code A7

1

TStates 4

Status CY AC Z S P 0 1 x x x

Flags affected

ANA

B

A0

1

4

0

1

x

x

x

ANA

C

A1

1

4

0

1

x

x

x

ANA

D

A2

1

4

0

1

x

x

x

ANA

E

A3

1

4

0

1

x

x

x

ANA

H

A4

1

4

0

1

x

x

x

ANA

L

A5

1

4

0

1

x

x

x

ANA

M

A6

1

7

0

1

x

x

x

ANI

Data

E6

2

7

0

1

x

x

x

CALL

Label

CD

3

18

–

–

–

–

–

None

CC

Label

DC

3

18/9

–

–

–

–

–

None

CM

Label

FC

3

18/9

–

–

–

–

–

None

CMA

2F

1

4

–

–

–

–

–

None

CMC

3F

1

4

x

–

–

–

–

CY is 0 AC is 1 CY is 0 AC is 1 CY is 0 AC is 1 CY is 0 AC is 1 CY is 0 AC is 1 CY is 0 AC is 1 CY is 0 AC is 1 CY is 0 AC is 1 CY is 0 AC is 1

CMP

A

BF

1

4

x

x

x

x

x

Only CY All

CMP

B

B8

1

4

x

x

x

x

x

All

CMP

C

B9

1

4

x

x

x

x

x

All

CMP

D

BA

1

4

x

x

x

x

x

All

CMP

E

BB

1

4

x

x

x

x

x

All

CMP

H

BC

1

4

x

x

x

x

x

All

CMP

L

BD

1

4

x

x

x

x

x

All

CMP

M

BE

1

7

x

x

x

x

x

All

ii

Mnemonics

Operand

CNC

Bytes

Label

Op code D4

3

TStates 18/9

CNZ

Label

C4

3

18/9

–

–

–

–

–

None

CP

Label

F4

3

18/9

–

–

–

–

–

None

CPE

Label

EC

3

18/9

–

–

–

–

–

None

CPI

Data

FE

2

7

x

x

x

x

x

All

CPO

Label

E4

3

18/9

–

–

–

–

–

None

CZ

Label

CC

3

18/9

–

–

–

–

–

None

27

1

4

x

x

x

x

x

All Only CY flag Only CY flag Only CY flag Only CY flag

DAA

Status CY AC Z S P – – – – –

DAD

B

09

1

10

x

–

–

–

–

DAD

D

19

1

10

x

–

–

–

–

DAD

H

29

1

10

x

–

–

–

–

DAD

SP

39

1

10

x

–

–

–

–

DCR

A

3D

1

4

–

x

x

x

x

DCR

B

05

1

4

–

x

x

x

x

Flags Affected None

All Expt.

CY All Expt.

CY DCR

C

0D

1

4

–

x

x

x

x

DCR

D

15

1

4

–

x

x

x

x

All Expt.

CY All Expt.

CY DCR

E

1D

1

4

–

x

x

x

x

DCR

H

25

1

4

–

x

x

x

x

All Expt.

CY All Expt.

CY All Expt.

DCR

L

2D

1

4

–

x

x

x

x

DCR

M

35

1

10

–

x

x

x

x

All Expt.

DCX

B

0B

1

6

–

–

–

–

–

CY None

DCX

D

1B

1

6

–

–

–

–

–

None

CY

iii

Mnemonics

Operand

DCX DCX

Bytes

H

Op code 2B

1

TStates 6

SP

3B

1

6

–

–

–

–

–

None

DI

F3

1

4

–

–

–

–

–

None

EI

FB

1

4

–

–

–

–

–

None

HLT

76

1

5

–

–

–

–

–

None

DB

2

10

–

–

–

–

–

None

3C

1

4

–

x

x

x

x

All Expt.

IN INR

Port Addr. A

Status CY AC Z S P – – – – –

Flags affected None

CY INR

B

04

1

4

–

x

x

x

x

INR

C

0C

1

4

–

x

x

x

x

All Expt.

CY All Expt.

CY INR

D

14

1

4

–

x

x

x

x

All Expt.

CY INR

E

1C

1

4

–

x

x

x

x

INR

H

24

1

4

–

x

x

x

x

All Expt.

CY All Expt.

CY All Expt.

INR

L

2C

1

4

–

x

x

x

x

INR

M

34

1

10

–

x

x

x

x

All Expt.

CY

INX

B

03

1

6

–

–

–

–

–

CY None

INX

D

13

1

6

–

–

–

–

–

None

INX

H

23

1

6

–

–

–

–

–

None

INX

SP

33

1

6

–

–

–

–

–

None

JC

Label

DA

3

10/7

–

–

–

–

–

None

JM

Label

FA

3

10/7

–

–

–

–

–

None

JMP

Label

C3

3

10

–

–

–

–

–

None

JNC

Label

D2

3

10/7

–

–

–

–

–

None

iv

Mnemonics

Operand

JNZ

Bytes

Label

Op code C2

3

TStates 10/7

Status CY AC Z S P – – – – –

JP

Label

F2

3

10/7

–

–

–

–

–

None

JPE

Label

EA

3

10/7

–

–

–

–

–

None

JPO

Label

E2

3

10/7

–

–

–

–

–

None

JZ

Label

CA

3

10/7

–

–

–

–

–

None

LDA

Addr.

3A

3

13

–

–

–

–

–

None

LDAX

B

0A

1

7

–

–

–

–

–

None

LDAX

D

1A

1

7

–

–

–

–

–

None

LHLD

Addr.

2A

3

16

–

–

–

–

–

None

LXI

B

01

3

10

–

–

–

–

–

None

LXI

D

11

3

10

–

–

–

–

–

None

LXI

H

21

3

10

–

–

–

–

–

None

LXI

SP

31

3

10

–

–

–

–

–

None

MOV

A, A

7F

1

4

–

–

–

–

–

None

MOV

A, B

78

1

4

–

–

–

–

–

None

MOV

A, C

79

1

4

–

–

–

–

–

None

MOV

A, D

7A

1

4

–

–

–

–

–

None

MOV

A, E

7B

1

4

–

–

–

–

–

None

MOV

A, H

7C

1

4

–

–

–

–

–

None

MOV

A, L

7D

1

4

–

–

–

–

–

None

MOV

A, M

7E

1

7

–

–

–

–

–

None

MOV

B, A

47

1

4

–

–

–

–

–

None

v

Flags affected None

Mnemonics

Operand

MOV

Bytes

B, B

Op code 40

1

TStates 4

Status CY AC Z S P – – – – –

MOV

B, C

41

1

4

–

–

–

–

–

None

MOV

B, D

42

1

4

–

–

–

–

–

None

MOV

B, E

43

1

4

–

–

–

–

–

None

MOV

B, H

44

1

4

–

–

–

–

–

None

MOV

B, L

45

1

4

–

–

–

–

–

None

MOV

B, M

46

1

7

–

–

–

–

–

None

MOV

C, A

4F

1

4

–

–

–

–

–

None

MOV

C, B

48

1

4

–

–

–

–

–

None

MOV

C, C

49

1

4

–

–

–

–

–

None

MOV

C, D

4A

1

4

–

–

–

–

–

None

MOV

C, E

4B

1

4

–

–

–

–

–

None

MOV

C, H

4C

1

4

–

–

–

–

–

None

MOV

C, L

4D

1

4

–

–

–

–

–

None

MOV

C, M

4E

1

7

–

–

–

–

–

None

MOV

D, A

57

1

4

–

–

–

–

–

None

MOV

D, B

50

1

4

–

–

–

–

–

None

MOV

D, C

51

1

4

–

–

–

–

–

None

MOV

D, D

52

1

4

–

–

–

–

–

None

MOV

D, E

53

1

4

–

–

–

–

–

None

MOV

D, H

54

1

4

–

–

–

–

–

None

MOV

D, L

55

1

4

–

–

–

–

–

None

vi

Flags affected None

Mnemonics

Operand

MOV

Bytes

D, M

Op code 56

1

TStates 7

Status CY AC Z S P – – – – –

MOV

E, A

5F

1

4

–

–

–

–

–

None

MOV

E, B

58

1

4

–

–

–

–

–

None

MOV

E, C

59

1

4

–

–

–

–

–

None

MOV

E, D

5A

1

4

–

–

–

–

–

None

MOV

E, E

5B

1

4

–

–

–

–

–

None

MOV

E, H

5C

1

7

–

–

–

–

–

None

MOV

E, L

5D

1

4

–

–

–

–

–

None

MOV

E, M

5E

1

7

–

–

–

–

–

None

MOV

H, A

67

1

4

–

–

–

–

–

None

MOV

H, B

60

1

4

–

–

–

–

–

None

MOV

H, C

61

1

4

–

–

–

–

–

None

MOV

H, D

62

1

4

–

–

–

–

–

None

MOV

H, E

63

1

4

–

–

–

–

–

None

MOV

H, H

64

1

4

–

–

–

–

–

None

MOV

H, L

65

1

4

–

–

–

–

–

None

MOV

H, M

66

1

7

–

–

–

–

–

None

MOV

L, A

6F

1

4

–

–

–

–

–

None

MOV

L, B

68

1

4

–

–

–

–

–

None

MOV

L, C

69

1

4

–

–

–

–

–

None

MOV

L, D

6A

1

4

–

–

–

–

–

None

MOV

L, E

6B

1

4

–

–

–

–

–

None

vii

Flags affected None

Mnemonics

Operand

MOV

Bytes

L, H

Op code 6C

1

TStates 4

MOV

L, L

6D

1

4

–

–

–

–

–

None

MOV

L, M

6E

1

7

–

–

–

–

–

None

MOV

M, A

77

1

7

–

–

–

–

–

None

MOV

M, B

70

1

7

–

–

–

–

–

None

MOV

M, C

71

1

7

–

–

–

–

–

None

MOV

M, D

72

1

7

–

–

–

–

–

None

MOV

M, E

73

1

7

–

–

–

–

–

None

MOV

M, H

74

1

7

–

–

–

–

–

None

MOV

M, L

75

1

7

–

–

–

–

–

None

MVI

A, data

3E

2

7

–

–

–

–

–

None

MVI

B, data

06

2

7

–

–

–

–

–

None

MVI

C, data

0E

2

7

–

–

–

–

–

None

MVI

D, data

16

2

7

–

–

–

–

–

None

MVI

E, data

1E

2

7

–

–

–

–

–

None

MVI

H, data

26

2

7

–

–

–

–

–

None

MVI

L, data

2E

2

7

–

–

–

–

–

None

MVI

M, data

36

2

10

–

–

–

–

–

None

00

1

4

–

–

–

–

–

None CY is 0 AC is 0 CY is 0 AC is 0 CY is 0 AC is 0

NOP

Status CY AC Z S P – – – – –

ORA

A

B7

1

4

0

0

x

x

x

ORA

B

B0

1

4

0

0

x

x

x

ORA

C

B1

1

4

0

0

x

x

x

viii

Flags affected None

Mnemonics

Operand

ORA

Bytes

D

Op code B2

1

TStates 4

ORA

E

B3

1

4

0

0

x

x

x

ORA

H

B4

1

4

0

0

x

x

x

ORA

L

B5

1

4

0

0

x

x

x

ORA

M

B6

1

7

0

0

x

x

x

ORI

Data

F6

2

7

0

0

x

x

x

OUT

Port Addr.

D3

2

10

–

–

–

–

–

None

E9

1

6

–

–

–

–

–

None

PCHL

Status CY AC Z S P 0 0 x x x

Flags affected CY is 0 AC is 0 CY is 0 AC is 0 CY is 0 AC is 0 CY is 0 AC is 0 CY is 0 AC is 0 CY is 0 AC is 0

POP

B

C1

1

10

–

–

–

–

–

None

POP

D

D1

1

10

–

–

–

–

–

None

POP

H

E1

1

10

–

–

–

–

–

None

POP

PSW

F1

1

10

x

x

x

x

x

All

PUSH

B

C5

1

12

–

–

–

–

–

None

PUSH

D

D5

1

12

–

–

–

–

–

None

PUSH

H

E5

1

12

–

–

–

–

–

None

PUSH

PSW

F5

1

12

x

x

x

x

x

All

RAL

17

1

4

x

–

–

–

–

RAR

1F

1

4

x

–

–

–

–

RC

D8

1

12/6

–

–

–

–

–

Only CY Only CY None

RET

C9

1

10

–

–

–

–

–

None

RIM

20

1

4

–

–

–

–

–

None

RLC

07

1

4

x

–

–

–

–

Only CY

ix

Mnemonics

Operand

Bytes

RM

Op code F8

1

TStates 12/6

Status CY AC Z S P – – – – –

Flags affected None

RNC

D0

1

12/6

–

–

–

–

–

None

RNZ

C0

1

12/6

–

–

–

–

–

None

RP

F0

1

12/6

–

–

–

–

–

None

RPE

E8

1

12/6

–

–

–

–

–

None

RPO

E0

1

12/6

–

–

–

–

–

None

RRC

0F

1

4

x

–

–

–

–

RST

0

C7

1

12

–

–

–

–

–

Only CY None

RST

1

CF

1

12

–

–

–

–

–

None

RST

2

D7

1

12

–

–

–

–

–

None

RST

3

DF

1

12

–

–

–

–

–

None

RST

4

E7

1

12

–

–

–

–

–

None

RST

5

EF

1

12

–

–

–

–

–

None

RST

6

F7

1

12

–

–

–

–

–

None

RST

7

FF

1

12

–

–

–

–

–

None

C8

1

12/6

–

–

–

–

–

None

RZ SBB

A

9F

1

4

x

x

x

x

x

All

SBB

B

98

1

4

x

x

x

x

x

All

SBB

C

99

1

4

x

x

x

x

x

All

SBB

D

9A

1

4

x

x

x

x

x

All

SBB

E

9B

1

4

x

x

x

x

x

All

SBB

H

9C

1

4

x

x

x

x

x

All

x

Mnemonics

Operand

SBB

Bytes

L

Op code 9D

1

TStates 4

Status CY AC Z S P x x x x x

Flags affected All

SBB

M

9E

1

7

x

x

x

x

x

All

SBI

Data

DE

2

7

x

x

x

x

x

All

SHLD

Addr.

22

3

16

–

–

–

–

–

None

SIM

30

1

4

–

–

–

–

–

None

SPHL

F9

1

6

–

–

–

–

–

None

STA

Addr.

32

3

13

–

–

–

–

–

None

STAX

B

02

1

7

–

–

–

–

–

None

STAX

D

12

1

7

–

–

–

–

–

None

37

1

4

x

–

–

–

–

STC SUB

A

97

1

4

x

x

x

x

x

Only CY All

SUB

B

90

1

4

x

x

x

x

x

All

SUB

C

91

1

4

x

x

x

x

x

All

SUB

D

92

1

4

x

x

x

x

x

All

SUB

E

93

1

4

x

x

x

x

x

All

SUB

H

94

1

4

x

x

x

x

x

All

SUB

L

95

1

4

x

x

x

x

x

All

SUB

M

96

1

7

x

x

x

x

x

All

SUI

Data

D6

2

7

x

x

x

x

x

All

EB

1

4

–

–

–

–

–

None CY & AC Zero CY & AC Zero

XCHG XRA

A

AF

1

4

0

0

x

x

x

XRA

B

A8

1

4

0

0

x

x

x

xi

Mnemonics

Operand

XRA

Bytes

C

Op code A9

1

TStates 4

XRA

D

AA

1

4

0

0

x

x

x

XRA

E

AB

1

4

0

0

x

x

x

XRA

H

AC

1

4

0

0

x

x

x

XRA

L

AD

1

4

0

0

x

x

x

XRA

M

AE

1

7

0

0

x

x

x

XRI

Data

EE

2

7

0

0

x

x

x

E3

1

16

–

–

–

–

–

XTHL

Status CY AC Z S P 0 0 x x x

xii

Flags affected CY & AC Zero CY & AC Zero CY & AC Zero CY & AC Zero CY & AC Zero CY & AC Zero CY & AC Zero None

Appendix - II Instruction codes of 8085 Microprocessor in Hexadecimal Order Hex Code 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25

Mnemonics NOP LXI B STAX B INX B INR B DCR B MVI B RLC --DAD B LDAX B DCX B INR C DCR C MVI C RRC --LXI D STAX D INX D INR D DCR D MVI D RAL --DAD D LDAX D DCX D INR E DCR E MVI E RAR RIM LXI H SHLD INX H INR H DCR H

Hex Code 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 40 41 42 43 44 45 46 47 48 49 4A 4B 4C

xiii

Mnemonics DAA --DAD H LHLD DCX H INR L DCR L MVI L CMA SIM LXI SP STA INX SP INR M DCR M MVI M STC --DAD SP LDA DCX SP INR A DCR A MVI A CMC MOV B, B MOV B, C MOV B, D MOV B, E MOV B, H MOV B, L MOV B, M MOV B, A MOV C, B MOV C, C MOV C, D MOV C, E MOV C, H

26

MVI H

4D

MOV C, L

Hex Code 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74

Mnemonics MOV C, M MOV C, A MOV D, B MOV D, C MOV D, D MOV D, E MOV D, H MOV D, L MOV D, M MOV D, A MOV E, B MOV E, C MOV E, D MOV E, E MOV E, H MOV E, L MOV E, M MOV E, A MOV H, B MOV H, C MOV H, D MOV H, E MOV H, H MOV H, L MOV H, M MOV H, A MOV L, B MOV L, C MOV L, D MOV L, E MOV L, H MOV L, L MOV L, M MOV L, A MOV M, B MOV M, C MOV M, D MOV M, E MOV M, H

Hex Code 75 76 77 78 79 7A 7B 7C 7D 7E 7F 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B

Mnemonics MOV M, L HLT MOV M, A MOV A, B MOV A, C MOV A, D MOV A, E MOV A, H MOV A, L MOV A, M MOV A, A ADD B ADD C ADD D ADD E ADD H ADD L ADD M ADD A ADC B ADC C ADC D ADC E ADC H ADC L ADC M ADC A SUB B SUB C SUB D SUB E SUB H SUB L SUB M SUB A SBB B SBB C SBB D SBB E

xiv

Hex Code 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF C0 C1 C2

Mnemonics SBB H SBB L SBB M SBB A ANA B ANA C ANA D ADA E ANA H ANA L ANA M ANA A XRA B XRA C XRA D XRA E XRA H XRA L XRA M XRA A ORA B ORA C ORA D ORA E ORA H ORA L ORA M ORA A CMP B CMP C CMP D CMP E CMP H CMP L CMP M CMP A RNZ POP B JNZ

Hex Code C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9

xv

Mnemonics JMP CNZ PUSH B ADI RST 0 RZ RET JZ --CZ CALL ACI RST 1 RNC POP D JNC OUT CNC PUSH D SUI RST 2 RC --JC IN CC --SBI RST 3 RPO POP H JPO XTHL CPO PUSH H ANI RST 4 RPE PCHL

Hex Code Mnemonics EA JPE EB XCHG EC CPE ED --EE XRI EF RST 5 F0 RP F1 POP PSW F2 JP F3 DI F4 CP Total: 246 Instructions

Hex Code F5 F6 F7 F8 F9 FA FB FC FD FE FF

xvi

Mnemonics PUSH PSW ORI RST 6 RM SPHL JM EI CM --CPI RST 7

xvii