NDES’99 Final Camera Ready Copy, submitted 19 May 1999 NDES’99 Paper Tracking Number
013
MULTI-FLOPS - A VIEW OF THE DYNAMIC BEHAVIOUR
Anthony C. Davies Department of Electronic Engineering, King’s College London, Strand, London, WC2R 2LS, England e-mail:
[email protected] or
[email protected] Phone: +44-171-848-2441 Fax: +44-171-836-4781
My registration form was faxed to Denmark on 19th May, and the request to make the Bank Transfer of the registration fee and the accomodation cost was requested on 19th May A.C. Davies
MULTI-FLOPS - A VIEW OF THE DYNAMIC BEHAVIOUR Anthony C. Davies Department of Electronic Engineering, King’s College London, Strand, London, WC2R 2LS, England e-mail:
[email protected]
ABSTRACT The two-gate bistable flip-flop may be generalised to a coupled structure of many gates having more stable states. These multi-flop structures have applications as arbiters to control mutually-exclusive access by several concurrent processes to a single service or resource. The paper illustrates some aspects of their complex dynamic behaviour. 1. INTRODUCTION The bistable flip-flop (set-reset latch) is a well-known digital component made from a pair of cross-coupled inverting-gates. Normal implementations have two stable equilibrium states which are separated by a single saddle (with one unstable equilibrium point). The unstable equilibrium point is responsible for metastability, known for many years to be a source of possible failure modes in real-time and asynchronous computer systems [1,2]. By combining more gates in an analogous way, it is possible to make structures with more stable states (multi-flops), which have applications as arbiters in digital computer systems for the control of mutuallyexclusive access to a service or resource. The dynamic behaviour of such multi-flops is complicated by the presence of unstable equilibria, and trajectories in such systems can exhibit several forms of metastability. A symmetric configuration of n NAND gates, each with n inputs, can be formed into an n-flop, which can be used as a ‘1 out of n’ arbiter. The output of each gate is connected to the inputs of the other (n−1), leaving one ‘free’ input per gate. Fig. 1 shows a tri-flop. 2. ARBITERS A common multi-processing systems requirement is that access to some shared resources or services must be controlled so that at most one process can have access at any time. Correct operation may additionally require adherence to a scheme of priorities among the processes. An arbiter is a digital component which is designed for implementing such access control. When a process requests service the arbiter responds by issuing a ‘grant’ signal if the resource required is
available. If the resource is busy, the arbiter delays the grant until the release of the resource has been signalled by the process using the resource (and by any other already-waiting processes). Using a multi-flop as an arbiter involves keeping all inputs at logic-zero (low) while there is no request for service, so forcing all outputs to logic-one (high). If any single input goes high (request) the corresponding output goes low (grant). During this time, until the first input has returned to low (indicating release of the resource), requests on the other inputs have no effects on the outputs. Hence the structure can provide mutually-exclusive access-control, although there are risks of maloperation due to metastability, etc. in the case of multiple concurrent requests with particular timing relationships between them. 3. STABLE STATES OF n-FLOP For all input patterns except the all-zeros one, there is a stable equilibrium state with one output low and the rest high. No stable equilibrium states exist with two or more outputs low, whatever the inputs. A low input forces the corresponding output to high, which takes that gate out of the dynamic regime for determining stable states. Thus if there are (n−2) zeros in the input pattern, there are just two gates left whose outputs are not directly forced high. These gates form a conventional crosscoupled bistable latch - with two stable states when both inputs are high. Hence, for each distinct pattern of (n−2) zeros, a different pair of gates forms the bistable latch subsystem. Similarly, for (n−3) input zeros, there is a subsystem of three gates forming a tri-flop. With all inputs high, this has three stable states, each with a single low output. By continuing this reasoning recursively, the number of stable states for each input pattern may be deduced. In general, for (n−r) input zeros, there is an r-flop subsystem, which has r stable states when all its inputs are high. This is summarised in Table 1. The total number of ‘situations’, Ψ, is the sum of the entries in the ‘situations’ column - each one corresponds to a different combination of input pattern and stable-state.
For n = 2, Ψ = 5, for n = 3, Ψ = 13, for n = 4, Ψ = 33, and for n = 5, Ψ = 81 Note particularly that Ψ is NOT the number of distinct stable states. Thus, in the case of n = 2, the situations are: input (0,0) ⇒ stable output (1,1) input (1,0) ⇒ stable output (0,1) input (0,1) ⇒ stable output (1,0) input (1,1) ⇒ stable output (1,0) or (0,1) There are five situations but only three distinct stable states. For n = 3, there are thirteen situations but only four distinct stable states. Encoding inputs and states as binary integers for compactness: input 0 ⇒ stable output 7 input 4, 2, 1 ⇒ stable output 3, 5, 6, respectively input 6 ⇒ stable output 4 or 3 input 5 ⇒ stable output 6 or 3 input 3 ⇒ stable output 6 or 5 input 7 ⇒ stable output 6 or 5 or 3 In general, an n-flop has n+1 distinct stable states, and for k zeros at the input, (0 < k ≤ n), the number of situations is k.nCk. 4. SIMPLE DYNAMIC MODELS FOR SIMULATION OF BEHAVIOUR A detailed analysis of the tri-flop, using a realistic model of modern CMOS gate designs, and with illustrations from a commercial Spice-like simulator, has been given by van Berkel and Molnar [3]. Although Spice models of actual gates can provide accurate simulations, it is sufficient to use very simple gate models to illustrate many aspects of the dynamic behaviour. For this paper, one first-order differential equation was used for each NAND gate, based on the cascade of a minimum-selector, the non-linear transfer characteristic, and a linear first-order low-pass filter. The tri-flop shown in Fig. 1 can be represented by three non-linear state-equations: dx1 1 = − x1 + F1[min( x 2 , x3 , u1 )] dt τ1
(
)
(
)
(
)
dx 2 1 = − x 2 + F2 [min( x1 , x 3 , u2 )] dt τ2
dx 3 1 = − x 3 + F3 [min( x1, x 2 , u3 )] dt τ3 where F denotes the non-linear transfer characteristic, and τ is the time-constant. The inputs are u1, u2, u3 and the outputs are the state-variables x1, x2, x3. For an n-flop, the dynamic behaviour in moving from one state to another comprises a trajectory in an ndimensional state-space, in which the gate outputs are the state-variables. Since gate outputs are bounded by the high and low logic-levels, Vlow and Vhigh, the trajectories remain within an n-dimensional hypercube.
For visual clarity of the illustrations, the (unrealistic) choice of 0⋅5V for Vlow was made, with the cube-edges drawn at 0V and 5V ( = Vhigh). The tri-flop is the easiest to analyse, and because it has a state-space of only three dimensions, the dynamic behaviour can be illustrated by means of perspective representations of the trajectories in this state-space. To illustrate the intended behaviour suppose that the following sequence occurs: rest-state; request on 1; grant 1; request on 2; release 1; grant 2; request on 3; release 2; grant 3; release 3; rest-state. The state-sequence should be: (111) ⇒ (011) ⇒ (101) ⇒ (110) ⇒ (111) The simulation is shown in Fig. 3. Notice that the second and third transitions are equivalent to bistable flip-flop transitions, each taking place in two of the three dimensions. With this timing relationship, all trajectories remain on the surface of the cube. 4.1. The Metastable equilibrium point In the central region of the cube, the gates are in their ‘active’ region (e.g. between ‘off’ and ‘on’), and somewhere within this is a ‘metastable-point’, m, defined by
[
xi = Fi min( x j , j = 1.. n, i ≠ j )
]
If all Fi are identical, each gate has its output equal to its inputs and m is on a 45° line from the origin (0,0,0,0,...0) to the (1,1,1,1...1) vertex. A way to approach m is to force the system to start at or near the origin, while keeping all inputs high. Since for a NAND gate F(Vlow) = Vhigh, while the statevariables are near zero the state-equations simplify to: dx i 1 for i = 1,2, ... n = − xi + V high dt τi The equations are de-coupled and each gate output increases towards Vhigh : t xi = V high 1 − exp − τ i Thus, the trajectory aims towards the (1,1,1,1...1) vertex until the state-variables become large enough to start pulling down one or more of the the outputs via the function F. The state-equations then become coupled once more, and the trajectory moves on towards a stable state (a vertex for which a single statevariable is zero). Thus the trajectory initially heads towards m, before deflecting away towards one of the stable states. Fig. 2 shows two such trajectories for a bistable flip-flop, one terminating on each stable state. Points are plotted at equal time intervals to illustrate the rate: where the points are close, the trajectory is moving slowly, and where they are far apart, it is moving quickly. For gates with very similar time-constants and non-
(
)
linear transfer characteristics, this trajectory closely approaches m, resulting in a longer metastable transient than if the gates are dissimilar. The (0,0,0,0,...0) state cannot be reached in actual operation (although it might be regarded as a natural power-up condition). 4.2 Tri-flop with three overlapping requests In the example of Fig. 3 at most one request is ever pending. If all three requests occur before the first grant has been released, the sequence of granting the second and third may be interchanged, or, for some timing relationships, metastable transients might occur. This is because, at the instant of releasing the first grant, both other gates have their inputs simultaneously raised to Vhigh while their outputs are already at Vhigh. This is a symmetrical situation for these two gates, and the precedence of the two requests is lost. While the inputs are rising and the outputs falling, the trajectory moves into the interior of the cube, followed by divergence towards one or other stable state, the selection of which depends upon relative characteristics of the gates. Fig. 4 shows an example, which should be compared with Fig. 3 Fig. 5 shows trajectories of a tri-flop when it is repeatedly subjected to three concurrent requests for service. Random jitter was added to the three nearsimultaneous transitions, so that on each occasion, the reponse was different. These trajectories include various forms of metastability and failure to respond adequately to the three requests.
4.2 Projections of trajectories from a six-flop Fig. 6 is a projection onto a 3-dimensional subspace of the 6-dimensional state-space of a 6-flop for a number of trajectories starting from randomly chosen points in the neighbourhood of (1,0,0,1,0,1), leading to various stable states with a single ‘low’ state-variable. Although some trajectories appear to terminate on the (1,1,1) vertex, this is because of the projection: in reality they terminate with one of the other three statevariables ‘low’. The other trajectories terminate a short distance from vertices because the simulated gate model has Vlow at 0⋅5V and not 0V. 5. CONCLUSIONS The dynamic behaviour of the multi-flop includes many interesting features, but its use as an arbiter is questionable because of risks of metastability and incorrect or unfair responses to concurrent requests. Acknowledgement: The U.K. Engineering and Physical Sciences Research Council is thanked for financial support (Grant No. GR/L92471). 6. REFERENCES [1] T.J. Chaney and C.E. Molnar ‘Anomalous Behaviour of Synchroniser and Arbiter Circuits’, IEEE Trans., vol. C-22, pp 421-422, 1973 [2] C.L. Seitz ‘System Timing’, in C. Mead and L. Conway, Introduction to VLSI Systems, Addison Wesley, 1980 (pp 218-262) [3] C.H. van Berkel and C.E. Molnar ‘Beware the 3way arbiter’, IEEE Journal on Solid-state Circuits, vol. 34, June 1999
Table I - stable states of n-flop notation:{abc..}* denotes all distinct permutations of (abc..). Column 2 and column 1 permutations have to match input stable states situations comments (0000...00) - no ‘ones’ (111...11) 1 {1000...00}* - one ‘one’ {0111...11}* n {1100...00}* - two ‘ones’ {yz11...11}* y = not z e.g. (1,0) or (0,1) n(n−1) {1110...00}* - three ‘ones’ {xyz1...11}* x, y, z with just one ‘zero’ n(n−1)(n−2)/2 {1111...00}* - four ‘ones’ {wxyz1...11}* w, x, y, z with just one ‘zero’ n(n−1)(n−2)(n−2)/3! etc. etc. etc. (1111...11) {0111...11}* n
Fig. 1 Tri-flop structure
Fig. 2. Trajectories of bistable flip-flop
Fig. 3 Normal response to three requests
Fig. 4 Response involving two pending requests
tri-flop
Fig. 5 Superimposed responses of a tri-flop to many concurrent requests with small timing variations (random jitter at the transitions)
Fig. 6 Two view of various 6-flop trajectories projected onto three dimensions
