Arbitrary-Precision Signal Generation for Bandlimited Mixed-Signal Testing Xavier Haurie and Gordon W. Roberts Microelectronics and Computer Systems Laboratory Department of Electrical Engineering, McGill University 3480 University Street, Montreal, Quebec, Canada H3A 2A7
[email protected],
[email protected] Tel.: (514) 398-6029 Fax: (514) 398-4470 Abstract - This paper presents significant improvements in the generation of analog signals for on-chip analog circuit testing. In particular, the novel oscillators proposed here can achieve signal-to-noise ratios far greater than previous designs, while remaining area-efficient. One particular example illustrates a 30 dB improvement in the SNR. Alternatively, signals can be generated with the same SNR as with older designs but over a wider range of frequencies. Multitone signal generation is enhanced in the same fashion. Prototypes were built and satisfactorily tested on FPGA technology.
I. INTRODUCTION The predominance of testing costs in IC fabrication and the trends towards mixed-signal devices, especially in the telecommunications industry, warrant the development of Mixed-Analog/Digital Built-In-Self-Test (MADBIST) techniques [1][2]. Typical industrial tests on analog circuits require the use of a sinusoidal signal source at least as accurate as the device under test. Reliable, high-precision on-chip analog signal generation at a relatively low hardware cost has thus been identified as a key to successful MADBIST schemes. A promising solution to this technical challenge, a digital Lossless Discrete Integrator (LDI) resonator combined with a 1-bit delta-sigma modulator, has been presented in [3]. The basic limitation of this circuit is that it introduces some noise at frequencies near the generated tone. For a given digital clocking frequency and signal bandwidth (constraints of the device under test), the maximum SNR achieved by the oscillator in the signal band is fixed as reported in [3]. In addition, this oscillator generates large amounts of out-of-band noise whose spectral distribution cannot be modified for lack of degrees of freedom in the digital circuit. This paper first reviews the fundamentals of deltasigma modulator-based signal generation (Section II).
Sections III, IV and V then show how, for a given clocking frequency and signal bandwidth, the SNR can be increased by using a higher-order delta-sigma modulator, but without dramatically increasing the hardware cost of the device. Section VI demonstrates the generation of simultaneous tones using a single oscillator circuit. Bandpass circuits can be tested by high-order bandpass oscillators such as the one presented in Section VII. Section VIII briefly outlines how high-order oscillators can be made to generate signals whose noise spectra fit the characteristics of the circuit under test so as to reduce the analog filtering requirements for the MADBIST. Section IX describes the design, simulation and prototyping software which we developed and used in this work. Conclusions are drawn in Section X. II. PRINCIPLES OF DELTA-SIGMA MODULATED OSCILLATOR DESIGN FOR MADBIST APPLICATIONS A basic assumption underlying the MADBIST scheme proposed in [2] is that the digital hardware is tested before the analog hardware. Thus, if most of the circuitry implementing the analog source is digital, it can be properly tested before it is used for testing the analog hardware. As summarized below, an area-efficient bandlimited oscillator can indeed be built using mostly digital hardware, as first reported in [3]. A 1-bit digital-to-analog converter (such as a sample-and-hold circuit) is the only analog part needed, the rest of the circuit being implemented using digital registers and adders/subtractors. First we consider the LDI resonator shown in Fig. 1. It consists of two discrete-time integrators which hold the resonator’s state variables x1(n) and x2(n). Provided that 0 < k < 2, the output x1(n) is a sinusoidal signal described by the following equation: x 1(n) = A sin ( Ω 0 n + φ ) .
(1)
The frequency, amplitude and phase of the sinusoid
IEEE International Test Conference, Washington, D.C., October 1995.
x2
∆Σ Modulator
LDI Resonator
z-1
x1 x1 z-1
1-Bit DAC
out t
-k
t
t
Fig. 2: Basic oversampled oscillator configuration. The output consists of a pulse-density-modulated signal in which the low-frequency sinusoidal waveform is embedded.
Fig. 1: Lossless Discrete Integrator (LDI) resonator.
depend on the loop coefficient k and the initial conditions x1(0) and x2(0), and are given by: k , Ω 0 = acos 1 – --- 2
(2)
( 1 – k ) x 1(0) + x 2(0) A = ------------------------------------------------ , and sin ( Ω 0 + φ )
(3)
x 1(0) sin Ω 0 φ = atan ----------------------------------------------------------------------. ( 1 – k – cos Ω 0 ) x 1(0) + x 2(0)
(4)
k1=2-L -
Since three independent variables (k, x1(0) and x2(0)) are available to control the circuit’s operation, the three parameters of the sinusoid (A, Ω0, and φ) can arbitrarily be set. For instance, to obtain a period of oscillation of T samples and an amplitude A, the loop coefficient and the initial values of the two signals x1 and x2 can be set according to: 2π k = 2 1 – cos ------ T
(5)
x 1(0) = A
(6)
k x 2(0) = --- A 2
(7)
1 ---------------1 – z –1
MUX 1
x1
z –1 ---------------1 – z –1
y
0
x2
STF(z) NTF(z)
q
∆Σ Modulator
-k2 +k2 out (1 bit)
Fig. 3: Oversampled oscillator with delta-sigma modulator in the loop. The modulator must have STF(z)=1 at all physical frequencies.
by the coefficient k. A digital multiplier is quite a slow and area-intensive device and thus should be avoided if possible. A technique which circumvents this problem consists of including the modulator in a second resonating loop with a scaling coefficient k2, as shown in Fig. 3. In this case, k1 is set to a power of 2 so that it is realized by shifting the signal bits instead of performing a binary multiplication. k2 can be implemented by a two-input multiplexer, since the output of the delta-sigma modulator is a 1-bit signal. The generated tone is taken at the output of the modulator; using the superposition principle we deduce that its frequency is given by
The resonator is implemented in digital hardware, therefore its output is a multi-bit digital signal. It can be converted to a continuous-time analog signal using a Digital-to-Analog Converter (DAC). A 1-bit-output delta-sigma digital-to-analog converter [4] has the advantage of using only digital hardware except for a 1bit DAC, which, being a simple analog device, presents a definite advantage over other types of DACs for use in a MADBIST scheme. The resulting configuration is shown in Fig. 2. Note that the delta-sigma modulator output takes on one of two possible values, +1 and -1, represented by a single bit.
k1 + k2 Ω 0 = acos 1 – ---------------. 2
The major drawback of this signal generation scheme is that it requires a high-precision digital multiplier to implement the scaling of the LDI resonator loop signal
(8)
We must ensure that the delta-sigma modulator, which is a non-linear circuit, does not prevent the loop signals from oscillating. We can do so by using a linear model
2 IEEE International Test Conference, Washington, D.C., October 1995.
level of the sigma-delta modulator, equivalent to a sinusoidal amplitude of 0.32 (in fact the exact amplitude was set to 0.25). The modulator produces the spectrallyshaped noise floor. Notice the noise-power zero at DC, a distinguishing feature of the second-order delta-sigma modulator. The total inband noise power may be approximated from the plot itself. The resolution bandwidth is 2-15xFs and the signal bandwidth is 2-7xFs, so the total inband noise power is equal to the average inband noise power multiplied by 28, i.e. scaled upward by 24 dB. The SNR for this simulation is thus 65 dB.
0
Power Density (dB)
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−250 0
2 4 6 Normalized Frequency (F/Fs)
The following sections will show that the same technique can be used with higher-order modulators, yielding sinusoidal outputs of arbitrarily large dynamic range over a given portion of the frequency spectrum.
8 −3-3
x 10 x 10
Fig. 4: Inband power spectral density of the output of a digital oscillator with a 2nd order delta-sigma modulator in the loop.
There are some important side-effects to the inclusion of the delta-sigma modulator in the resonator loop as in Fig. 3. The first of these is a slight randomizing of the resonator’s initial conditions. Because the initial deltasigma modulator output can be equal to +1 as well as -1, the state variables of the loop after one iteration can be known with a precision of +/- k2. This imprecision will affect the amplitude and phase of the output tone. Furthermore, the modulator generates large amounts of noise power outside the signal band, which is scaled by k2 before being fed into the resonator. For this reason, k2 is made as small as possible. In other words, k1 is responsible for a coarse frequency selection while k2 does the fine-tuning.
of the modulator. Typically, the quantization error q introduced by the 1-bit quantizer inside a delta-sigma modulator is assumed to be additive white noise. The modulator is then characterized by its Quantization Noise Transfer Function NTF(z) and its Signal Transfer Function STF(z): Y(z) = STF ( z ) X 1(z) + NTF ( z ) Q(z) ,
(9)
where Y(z), X1(z) and Q(z) are the Z-transforms of y(n), x1(n) and q(n), respectively.
Second, the resonator-modulator combination can be considered as a single circuit with a noise-input located in the 1-bit quantizer. This noise input sees a NTF different from NTF(z); provided that STF(z)=1, the new NTF, which we call NTF’(z), is given by:
If the STF is strictly equal to 1 at all frequencies, and if the quantization error q is properly attenuated by the NTF at the resonant frequency, then it is reasonable to assume that the resulting closed-loop circuit may display the same oscillatory behavior as the pure digital resonator, at least over some significant period of time after the initial conditions have been set.
–2
1 + ( k1 – 2) + z - ⋅ NTF(z) NTF′(z) = -------------------------------------------------------------–1 –2 1 + ( k1 + k2 – 2) z + z
2nd
Indeed this is the case when a order delta-sigma modulator is used, as reported in [3] (the circuit topology presented here is a variation of the one in [3]). The inband power density spectrum for one possible simulated output of that circuit is shown in Fig. 4. The oversampling ratio (OSR) for this plot is 64, meaning that the signal bandwidth is Fs/2/64, where Fs is the sampling rate. The spectral data is obtained by running a 218-point FFT on the simulation output data and averaging over 8 bins. The resulting resolution-bandwidth is 3.05x10-5. The generated signal is thus represented by the sharp power-density spike at the frequency 0.0013 x Fs. Its power is roughly -10 dB relative to the output
(10)
A pair of zeros and a pair of poles are added on the unit circle (i.e. at physical frequencies). The normalized frequency at which the new zeros occur is equal to acos ( 1 – k 1 ⁄ 2 ) , while that of the new poles is acos ( 1 – ( k 1 + k 2 ) ⁄ 2 ) , the resonant frequency of the
system. The full effects of the poles are still not completely understood. In most cases they seem to make the system critically stable, but not instable (the desired property of the resonator). In fact, since the resonatormodulator pair is a non-linear circuit, frequency-domain (or linear systems) techniques alone cannot fully and accurately predict its stability properties. The same is 3
IEEE International Test Conference, Washington, D.C., October 1995.
x
y u e
H(z)
+
e
B2
+ -
+ -
A2
-
z –1 ----------------–1 1–z
1 ----------------–1 1–z
B1
true of delta-sigma modulators in general, although empirical findings compensate for our lack of theoretical knowledge.
B6
+ -
A6
A4 z–1 ----------------–1 1–z
A1
Fig. 5: Overall structure for delta-sigma modulators, which ensures a STF equal to unity.
B4
1 ----------------–1 1–z
B3
1 ----------------–1 1–z
u
A5
A3
+ -
z –1 ----------------–1 1–z
+ -
B5
Fig. 6: Realization of the linear block H(z) of the delta-sigma modulator. All the coefficients are powers-of-two and thus do not require multipliers. (A 6th order structure is shown here.)
III. MULTIPLIERLESS HIGH-ORDER DELTA-SIGMA MODULATOR-BASED OSCILLATOR Here we briefly outline a design method and a specific topology for multiplier-free 1-bit high-order digital delta-sigma modulators for lowpass signals. We also show that these area-efficient, high-precision modulators can be inserted in a resonating loop to create multiplier-free signal sources of virtually unlimited SNR.
bandwidth equal to one 128th of the digital clocking rate was designed. Note that if the sampling rate of the digital circuitry is 5 MHz, then the signal bandwidth will be approximately 40 kHz. Thus our sample design could be used to test audio-band analog circuits. The coefficients of the design are listed in Table 1.
The delta-sigma modulators used in this work have the structure shown in Fig. 5. The STF and NTF are given by:
Table 1: Coefficients of the 4th Order Delta-Sigma Modulator
1 NTF(z) = -----------------------------( 1 + H ( z) )
(11)
STF(z) = 1
(12)
It is important to note that the transfer function from the signal input to the output of the modulator (the STF), under the assumption of linearity, is strictly equal to 1. This allows us to introduce the modulator in the resonating loop while keeping the overall circuit critically stable. The NTF is usually designed to attenuate the quantization noise enough in the band of interest so as to produce the desired SNR, with the constraint that the modulator be stable for some range of non-zero inputs.
A COEFFICIENTS
B COEFFICIENTS
A1 = 2-7
B1 = 26
A2 = -2-4
B2 = -29
A3 = -2-4
B3 = 210
A4 = 2-6
B4 = 214
A5 = 0
B5 = 0
A6 = 0
B6 = 0
Fig. 7 shows the NTF over the Nyquist interval, while Fig. 8 shows it in the signal band. As desired, the NTF greatly attenuates the modulator’s quantization noise in the signal band, while at other frequencies this noise is slightly amplified.
The linear block H(z) is realized using a lossless digital integrator ladder as shown in Fig. 6. An LDI ladder [5] is used here because it allows the required NTF to be realized using power-of-two coefficients only, thereby eliminating the need for multipliers altogether. Thus an oscillator using an Nth order modulator can be realized quite cheaply with 3(N+2) additions or subtractions, 2N+1 fixed-shifts, N+2 registers, a 2-input multiplexer and a digital sign-detector.
IV. SIMULATION RESULTS This modulator was included in the digital oscillator loop as shown in Fig. 3 and the resulting circuit was simulated using floating-point arithmetic over a very large period of time (100 million samples, much longer than the oscillator would be required to operate in a typical analog device test). The loop coefficients were k1=2-14 and k2=9.15x10-6, resulting in a period of oscillation of 750 samples. The initial register values were
As an example, a 4th order modulator with a signal 4
IEEE International Test Conference, Washington, D.C., October 1995.
750.001
20
AveragePeriod Period (Samples) (Sam les) Average
0
Gain (dB)
−20
750
749.999
−40
749.998
−60 −80 −100 0
749.997 0
0.1
0.2 0.3 0.4 Normalized Frequency (F/Fs)
2
0.5
Fig. 7: NTF of the multiplier-less 4th order delta-sigma modulator over the Nyquist interval.
4 6 Time (Samples)
8
10 77 x 10 x 10
Fig. 9: Average period of oscillation of the oscillator of the oscillator using the 2nd order modulator.
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750.001
Average Period les) Average Period (Sam (Samples)
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Gain (dB)
−90
750
749.999
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749.998
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749.997
−130 0
2 4 6 Normalized Frequency (F/Fs)
8
0
−3-3
10 x x10
2
4 6 Time (Samples)
8
10 77 x 10 x 10
Fig. 8: NTF of the multiplier-less 4th order delta-sigma modulator in the signal band.
Fig. 10: Average period of oscillation of the oscillator of the oscillator using the 4th order modulator.
x1(0)=0.1 and x2(0)=3.51x10-6 for an amplitude of oscillation equal to 0.1 (or equivalently an average power of 5x10-3 or -23 dB). The design based on the 2nd order modulator presented in [3] was simulated under the same conditions, for comparison.
both designs. Here we can see that the average power reaches an almost constant value, 4.85x10-3 for the 4thorder design and 4.72x10-3 for the second-order one. This slight imprecision in the signal amplitude is most likely due to the fact that the initial conditions in the integrators are modified by the initial modulator output. For certain combinations of desired amplitude and frequency, the actual amplitude varies a great deal more than that shown in Fig. 11. Some care is thus required in selecting the parameters of the signals to be generated.
Fig. 9 shows the average period of oscillation of the internal signal x1 for the oscillator based on the 2nd order modulator. The period of oscillation seems to take on discrete values because of a limitation of the algorithm used to compute it. Fig. 10 shows the same information for the 4th order design. In both cases the period of oscillation remains within 0.004% of the expected 750.
Fig. 12 shows the wideband spectral content of the output signal of the 4th-order design taken over 218 samples after 1 billion iterations, this time for a 0.5 amplitude (-9 dB). Fig. 13 shows the inband power spectrum of the 1-bit output signals generated by the 2nd and 4th
Fig. 11 shows the average power of the signal x1 for 5
IEEE International Test Conference, Washington, D.C., October 1995.
−3
x 10
0
Power Density (dB)
Average Power
5
th
4 order design
4.9
4.8
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2nd order design 4.7 0
2
4 6 Time (Samples)
−200 0
8
10
2 4 6 Normalized Frequency (F/Fs)
8 −3-3
x x1010
7 7
x 10 x 10
Fig. 13: Inband power spectra of the 4th order and 2nd order oscillator outputs.
Fig. 11: Average power of x2.
0
the amplitude and frequency of the sinusoidal output. Preliminary results indicate that as the tone frequency increases, the maximum stable amplitude decreases. This seems to be due to the increase in the noise power injected from the modulator into the resonator, as the coefficient k2 increases.
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V. EXPERIMENTAL RESULTS −80
We have implemented our 4th-order oscillator on a Xilinx 4010 Field-Programmable Gate Array (FPGA) using 24-bit arithmetic. The design uses 50% of the hardware resources available on the FPGA, the equivalent of 5000 digital gates. It was designed to operate at clocking rates as high as 2 MHz. Our experiments were conducted at sampling rate of 1 MHz.
−100 −120 0
0.1
0.2 0.3 0.4 Normalized Frequency (F/Fs)
0.5
Fig. 12: Wideband power spectrum of the 4th-order oscillator output.
A 1-bit digital-to-analog converter was built using off-the-shelf components to condition the signal before visualizing it on an HP3588A Spectrum Analyzer. This converter, a polar-return-to-zero encoder, maps each output sample from the FPGA to a square pulse of amplitude 0.2 V and of a duration equal to half the sampling interval. The output impedance of the DAC is set to 50 Ohms. The pulse power is thus 0.2 mW or -7 dBm. The resulting spectrum analyzer data is shown in Fig. 14. Note that the oscillator noise in the signal band is lost under the measurement system’s noise floor. The third harmonic of the signal, created by the 1-bit DAC, can be seen at a power level of slightly less than -90 dB. The harmonic distortion created by the oscillator is thus masked by the distortion effects of the 1-bit DAC.
order designs. These results show that the oscillator based on the 4th order modulator displays enough stability and precision in the period and power of its sinusoidal output to be used as a 100-dB-SNR signal source over a bandwidth equal to 0.008 times the digital clocking rate. The third harmonic of the signal is seen at a power level of -115 dB (the dynamic range is thus 106 dB). As a comparison, the 2nd order delta-sigma modulator yields only 70 dB of SNR and 90 dB dynamic range over the same bandwidth. Thus, for the signal bandwidth chosen for this example, the 4th order circuit presents an improvement of 25 dB in the signal resolution at an additional hardware cost of 7 adders/subtractors and 2 registers.
Since our goal with this experiment is to illustrate the noise behavior of the delta-sigma oscillator, we abandoned the use of the spectrum analyzer and instead col-
We are currently studying how the stability of the various oversampled digital oscillator designs depends on 6
IEEE International Test Conference, Washington, D.C., October 1995.
0
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Power Density (dBm)
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−40 −60 −80 −100
1.5
2 Frequency (kHz)
2.5
−120 0
3
0.01 0.02 0.03 0.04 Normalized Frequency (F/Fs)
0.05
Fig. 16: Sampled data for the wide-band 4th-order oscillator clocked at 1 MHz.
Fig. 14: Spectrum analyzer data for the 4th-order oscillator clocked at 1 MHz.
SNR value for a given bandwidth. 0
VI. MULTITONE GENERATION
Power Density (dB)
−20
Multitone signal generators are essential to frequency response and intermodulation tests, such as the ones presented in [9]. Just as in [3] and [7], high-order oversampled digital oscillators can be time-interleaved to generate multi-tone signals. A higher-order circuit is capable of generating more tones at a given SNR, or alternatively it can spread the same number of tones over a wider signal band, still with the same SNR.
−40 −60 −80 −100 −120
Thus, even when extremely low noise levels are not required, higher-order oscillators can still be used to speed up the testing process by exciting an analog circuit at a greater number of frequencies simultaneously.
−140 −160 0
2 4 6 Normalized Frequency (F/Fs)
8
−3-3 x 10
x 10
Fig. 15 shows the simulated output of a four-tone gen-
Fig. 15: Sampled data for the 4th-order wideband oscillator clocked at 1 MHz.
lected the 1-bit digital data directly out of the oscillator. The power spectrum of that data is shown in Fig. 15, where it closely matches the simulated spectrum of Fig. 13, except for the tone amplitude which was set to 0.1 (20 dB) for this experiment.
−20
Power Density (dB)
−40
Another oscillator design for a signal bandwidth four times as large was also implemented and tested on an FPGA. The spectral density of its output is shown in Fig. 15. The cost of accommodating a larger signal bandwidth is that the noise power density has greatly increased so that the SNR now is only 40 dB for an amplitude of 0.5. This trade-off is typical of delta-sigma modulators and thus carries over to delta-sigma-modulator-based oscillators. One could also decrease the signal bandwidth and obtain a greater SNR value. Increasing the order of the modulator also increases the
−60 −80 −100 −120 −140 −160 −180 0
0.5
1 1.5 2 Normalized Frequency (F/Fs)
Fig. 17: Simulation data of a four-tone oscillator.
7 IEEE International Test Conference, Washington, D.C., October 1995.
2.5 −3 -3 x 10 x 10
0
0
−20 −40 Power Density (dB)
Power Density (dB)
−20 −40 −60 −80
−60 −80 −100 −120 −140
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−180 0.246
0.1
0.2 0.3 0.4 Normalized Frequency (F/Fs)
0.248 0.25 0.252 Normalized Frequency (F/Fs)
0.254
0.5
Fig. 19: Inband spectrum of the 4th-order bandpass oscillator.
Fig. 18: Wideband spectrum of the 4th-order bandpass oscillator.
advantage of the bandpass oscillator over the lowpass version is that no harmonics of the generated signal are present in the signal band.
erator. The amplitude of each tone was set to 0.25 or -15 dB. Since the four tones are actually time-domain multiplexed, their effective power is divided by four, resulting in -21 dB tones as seen on the plot (the tones are actually slightly lower on the plot due to the windowing of the data before the FFT is taken).
VIII. ACCOMMODATING THE SIGNAL SOURCE TO THE ANALOG CIRCUIT UNDER TEST The additional degrees of freedom provided by a high-order design can be used to shape the out-of-band noise in the digital domain so as to accommodate the limitations of the analog circuit under test. (This concept has been proposed for the design of delta-sigma modulators in general in [8]).
An attractive feature of this generation scheme is that the parameters of each sinusoid (amplitude, frequency and phase) can be set independently of the other sinusoid. This is very useful to control the crest factor of the complex sinusoid used to excite the analog circuit under test, so as to avoid saturation and other non-linear effects.
To illustrate this concept we consider the situation in which the analog-to-digital converter contained in a simple lowpass codec (shown in Fig. 20) must undergo a sinusoidal-input based test. In many instances the antialiasing filter (AAF) preceding the DAC-proper will be much less sensitive to high levels of high-frequency input-noise than the DAC, since it is designed to attenuate such inputs. High noise levels at some frequencies outside the signal band could trigger non-linear effects and corresponding responses of the DAC in the signal band, which would decrease the test accuracy.
VII. OVERSAMPLED BANDPASS OSCILLATORS The topology for a bandpass oversampled oscillator presented in [7] can be used with a high-order bandpass delta-sigma modulator to create a high-quality bandpass signal generator. The bandpass modulator can be obtained from a lowpass modulator by replacing each integrator by an appropriate biquad, based on a frequency transformation equation for discrete-time systems. The resulting modulator is of order 8, whereas the one used in [7] is of order 4.
Our strategy here is to match the noise spectrum of the signal source to the transfer function of the AAF, so that the DAC sees a uniform noise power spectrum in addition to the sine input. In effect, this kind of noiseshaping maximizes the dynamic range of the test stimu-
If the signal band is centered at exactly a quarter of the sampling rate Fs, these biquads do not require any multiplier, nor does the resonator loop. We mapped our 4th order low frequency oscillator into a bandpass one using this technique to get a multiplier-free bandpass resonator-modulator pair. Simulations over a billion samples indicate that this design is stable. The spectral plots of the output (Fig. 18 and Fig. 19) show an SNR. equal to 100 dB for a signal amplitude of 0.1. One
AAF
ADC
DSP
DAC
LPF
Fig. 20: Overall structure of a typical mixed-signal IC 8 IEEE International Test Conference, Washington, D.C., October 1995.
lus seen by the DAC by using the AAF as a lowpass filter.
XI. ACKNOWLEDGEMENTS
Work is presently under way extending our present work to include the ability to design delta-sigma oscillators with arbitrarily-shaped noise spectra.
The authors wish to acknowledge the FCAR Fund, the NSERC and Micronet for funding this research. A great many thanks to Ara Hajjar for implementing the FPGA prototypes.
IX. PROTOTYPING SOFTWARE
XII. REFERENCES
Just as digital testing was made applicable in industry by the adoption of testing methodologies and the use of computer-aided-design tools, the practical application of MADBIST schemes will require much automation of the design of their components.
[1] M. Toner and G. W. Roberts, “A BIST Scheme for a SNR, Gain Tracking, and Frequency Response Test of a Sigma-Delta ADC”, IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing, Vol. 42, No. 1, January 1995, pp. 1-15. [2] M. Toner and G. W. Roberts, “A BIST Scheme for an SNR Test of a Sigma-Delta ADC”, IEEE International Test Conference, Oct. 1993, pp. 805-814. [3] A. K. Lu and G. W. Roberts, “An OversampledBased Analog Multi-Tone Signal Generator”, IEEE International Test Conference, 1994. [4] M. W. Hauser, “Principles of Oversampling A/D Conversion”, J. Audio Eng. Soc., Vol. 39, No. 1/2, pp. 3-26, January/February 1991. [5] L. E. Turner, E. S. K. Liu and L. T. Bruton, “Digital LDI Ladder Design Using the Bilinear Transformation”, Proc. IEEE International Symposium on Circuits and Systems, pp. 1017-1020, May 1984. [6] A. H. Nuttall, “Some Windows with Very Good Sidelobe Behavior”, IEEE Trans. Acc. Speech Sig. Proc, Vol. ASSP-29, No. 1, February 1981. [7] B. R. Veillette and G. W. Roberts, “High-Frequency Sinusoidal Generation Using Delta-Sigma Modulation Techniques”, Proc. IEEE International Symposium on Circuits and Systems, pp. 637-640, May 1995. [8] S. Jantzi, C. Ouslis and A. Sedra, “Transfer Function Design for ∆Σ Converters”, Proc. IEEE ISCAS, May 1994. [9] M. F. Toner and G. W. Roberts, “A BIST Technique for a Frequency Response and Intermodulation Distortion Test of a Sigma-Delta ADC”, Proc. IEEE VLSI Test Symposium, pp. 60-65, April 1994.
Our work has led us to develop a set of software tools for the design, simulation and prototyping of the highquality oscillators presented herein. They are written in the ‘C’ language and in the Matlab language, making them highly portable. These tools work hand-in-hand to produce stable delta-sigma modulator and oscillator designs, to simulate them extensively and analyze the results, and to generate and test FPGA and DSP-based prototypes automatically. X. CONCLUSION High-order delta-sigma modulation-based analog signal generation has been shown to be feasible, both with respect to issues of stability and of hardware cost. The increased accuracy of high-order designs, which has been demonstrated by simulation results and experimental data, can be used to achieve various improvements in the quality and speed of on-chip testing of analog circuits. In particular, for a given signal bandwidth and digital clocking rate, high-order designs present two major improvements over lower-order designs previously presented: purer tones can be produced and more simultaneous tones of a given SNR can be produced. Also, the characteristics of the analog device being tested can be better matched so as to reduce unwanted non-linear responses to the out-of band noise associated with delta-sigma-modulation-based signal generation, which would degrade the test.
9 IEEE International Test Conference, Washington, D.C., October 1995.
