2. Outline. Introduction. ARM Cortex-M0 processor. Why processor bit width
doesn't matter. – Code size. – Performance. – Cost. Conclusions ...
Get Better Code Density than 8/16 bit MCU’s NXP LPC1100 Cortex M0 Oct 2009
Outline Introduction ARM Cortex-M0 processor Why processor bit width doesn’t matter – Code size – Performance – Cost
Conclusions
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ARM Cortex-M Processors Cortex-M family optimised for deeply embedded – Microcontroller and low-power applications
ARM Cortex-A Series: Applications processors for feature-rich OS and user applications
ARM Cortex-R Series: Embedded processors for real-time signal processing and control applications
ARM Cortex-M Series: Deeply embedded processors optimized for microcontroller and low-power applications
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ARM Cortex-M0 Processor 32-bit ARM RISC processor – Thumb 16-bit instruction set
Very power and area optimized – Designed for low cost, low power
Automatic state saving on interrupts and exceptions – Low software overhead on exception entry and exit
Deterministic instruction execution timing – Instructions always takes the same time to execute*
*Assumes deterministic memory system 4
Thumb instruction set 32-bit operations, 16-bit instructions – Introduced in ARM7TDMI (‘T’ stands for Thumb) – Supported in every ARM processor developed since – Smaller code footprint
Thumb-2 – All processor operations can all be handled in ‘Thumb’ state – Enables a performance optimised blend of 16/32-bit instructions – Supported in all Cortex processors
Thumb® ARM7
Thumb instruction set upwards compatibility ARM9
Cortex-M0
Cortex-M3
Cortex-R4
Cortex-A9
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Instruction set architecture Based on 16-bit Thumb ISA from ARM7TDMI – Just 56 instructions, all with guaranteed execution time – 8, 16 or 32-bit data transfers possible in one instruction Thumb
Thumb-2
User assembly code, compiler generated
System, OS
ADC
ADD
BIC
ADR BL
AND
ASR
B
NOP
BX
CMN
CMP
SEV
WFE
WFI
YIELD
EOR
LDM
LDR
LDRB
LDRH
LDRSB
LDRSH
LSL
LSR
MOV
MUL
MVN
DMB
ORR
POP
PUSH
ROR
RSB
SBC
DSB
STM
STR
STRB
STRH
SUB
SVC
ISB
TST
BKPT
BLX
CPS
REV
REV16
MRS
REVSH
SXTB
SXTH
UXTB
UXTH
MSR
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Program registers All registers are 32-bit wide – Instructions exist to support 8/16/32-bit data
13 general purpose registers – Registers r0 – r7 (Low registers) – Registers r8 – r12 (High registers)
3 registers with special meaning/usage – Stack Pointer (SP) – r13 – Link Register (LR) – r14 – Program Counter (PC) – r15
Special-purpose registers - xPSR
r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 (SP) r14 (LR) r15 (PC) xPSR
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Instruction behaviour Most instructions occupy 2 bytes of memory a = a * b;
C code
MUL r0, r1;
Assembler
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MUL
0
When executed, complete in a fixed time – Data processing (e.g. add, shift, logical OR) take 1 cycle – Data transfers (e.g. load, store) take 2 cycles – Branches, when taken, take 3 cycles
The instructions operate on 32-bit data values – Processor registers and ALU are 32-bit wide!
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Thumb instructions Cortex M0 requires instruction fetches to be half word aligned Thumb instructions are aligned on a two-byte boundaries
32 bit instructions are organized as 2 half words
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Nested Vectored Interrupt Controller NVIC enables efficient exception handling – Integrated within the processor - closely coupled with the core – Handles system exceptions & interrupts
The NVIC includes support for – Prioritization of exceptions – Tail-chaining & Late arriving interrupts
Fully deterministic exception handling timing behavior – Always takes the same number of cycles to handle an exception – Fixed at 16 clocks for no jitter – Register to trade off latency versus jitter
Everything can be written in C
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Interrupt behaviour r0 r1 r2 r3 r12
r13 (SP)
Push
Stack
r14 (LR) r15 (PC) xPSR
Growth Memory
On interrupt, hardware automatically stacks corruptible state Interrupt handlers can be written fully in C – Stack content supports C/C++ ARM Architecture Procedure Calling Standard
Processor fetches initial stack pointer from 0x0 on reset
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Writing interrupt handlers Traditional approach
ARM Cortex-M family
Exception table
NVIC automatically handles
– Fetch instruction to branch
– Saving corruptible registers – Exception prioritization – Exception nesting
Top-level handler – Routine handles re-entrancy IRQVECTOR LDR
PC, IRQHandler .
IRQHandler PROC STMFD sp!,{r0-r4,r12,lr} MOV r4,#0x80000000 LDR r0,[r4,#0] SUB sp,sp,#4 CMP r0,#1 BLEQ C_int_handler MOV r0,#0 STR r0,[r4,#4] ADD sp,sp,#4 LDMFD sp!,{r0-r4,r12,lr} SUBS pc,lr,#4 ENDP
ISR can be written directly in C .
– Pointer to C routine at vector – ISR is a C function
Faster interrupt response – With less software effort
WFI, sleep on exit
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Software support for sleep modes ARM Cortex-M family has architected support for sleep states – Enables ultra low-power standby operation – Critical for extended life battery based applications – Includes very low gate count Wake-Up Interrupt Controller (WIC) Power Management Unit
Sleep – CPU can be clock gated – NVIC remains sensitive to interrupts
Cortex-M0 Wake-up Deep
– WIC remains sensitive to selected interrupts – Cortex-M0 can be put into state retention
Sleep
NVIC
Deep sleep
WIC
WIC signals wake-up to PMU Wake-up
– Core can be woken almost instantaneously – React to critical external events
sensitive Interrupts
External interrupts 13
Instruction set comparison
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Code Size
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Code size of 32 bits versus 16/8bit MCU’s The instruction size of 8 bit MCU’s is not 8 bits – 8051 is 8 to 24 bits – PIC18 is 18 bits – PIC16 is 16 bits
The instruction size of 16 bit MCU’s is not 16 bits – MSP430 can be up to 32bits and the extended version can be up to 64 bits – PIC24 is 24 bits
The instruction size for M0 is mostly 16 bits
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Code size of 32 bits versus 16/8bit MCU’s
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16-bit multiply example Consider an device with a 10-bit ADC
– Basic filtering of data requires a 16-bit multiply operation – 16-bit multiply operation is compared below
8-bit example MOV MOV MUL MOV MOV MOV MOV MUL ADD MOV MOV ADDC MOV MOV MOV
A, XL ; 2 bytes B, YL ; 3 bytes AB; 1 byte R0, A; 1 byte R1, B; 3 bytes A, XL ; 2 bytes B, YH ; 3 bytes AB; 1 byte A, R1; 1 byte R1, A; 1 byte A, B ; 2 bytes A, #0 ; 2 bytes R2, A; 1 byte A, XH ; 2 bytes B, YL ; 3 bytes
MUL
AB; 1 byte
ADD
A, R1; 1 byte
MOV
R1, A; 1 byte
MOV
A, B ; 2 bytes
ADDC
A, R2 ; 1 bytes
MOV
R2, A; 1 byte
MOV
A, XH ; 2 bytes
MOV
B, YH ; 3 bytes
MUL
AB; 1 byte
ADD
A, R2; 1 byte
MOV
R2, A; 1 byte
MOV
A, B ; 2 bytes
ADDC
A, #0 ; 2 bytes
MOV
R3, A; 1 byte
Time: 48 clock cycles* Code size: 48 bytes
16-bit example
ARM Cortex-M0
MOV MOV MOV MOV
MULS r0,r1,r0
R1,&MulOp1 R2,&MulOp2 SumLo,R3 SumHi,R4
Time: 8 clock cycles Code size: 8 bytes
Time: 1 clock cycle Code size: 2 bytes
* 8051 need at least one cycle per instruction byte fetch as they only have an 8-bit interface 18
What about Data ? 8 bit microcontrollers do not just process 8 bit data – – – – –
Integers are 16 bits 8 bit microcontroller needs multiple instructions integers C libraries are inefficient Stack size increases Interrupt latency is affected
Pointers take multiple Bytes. M0 can handle Integers in one instruction M0 can efficiently process 8 and 16 bit data – Supports byte lanes – Instructions support half words and bytes. LDR, LDRH, LDRB
M0 has efficient Library support – Optimized for M0
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What about Data ? For 16 bit processors have issues with – Long integers – Floating point types – Data transfers between processor registers and memory
16 bit processors have 16 bit registers – Two registers required for 32 bit transfers – Increased stack requirements
M0 has 32 bit registers and 32 bit memories – Less cycles for long integers – Good floating point performance – Less cycles for data transfers
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What addressing modes? 16/8 bit processors are limited to 64K of space – Data memory limited and segmented – Requires banking or extensions to instruction set – Memory pointers are extended Require multiple instructions and registers
All cause increased code space M0 has a linear 1G address space – – – – –
32-bit pointers unsigned or signed 32-bit integers unsigned 16-bit or 8-bit integers signed 16-bit or 8-bit integers unsigned or signed 64-bit integers held in two registers.
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Code size increase due to paging
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Code size increase for large memory model (Extended program counter and Registers)
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Code Size Performance 2.50 2.00 1.50
HC08 M0 using microlib
1.00
rspeed
pntrch
iirflt
canrdr
bitmnp
aiifft
aifirf
a2time
0.00
puwmod
0.50
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Code Size Performance M0 code size is on average 10% smaller than best MSP430 average Code size for basic functions 350
MSP430
MSP430F5438 300
MSP430F5438 Large model
Cortex M0
Code Size (Bytes)
250
200
150
100
50
0 Switch16bit
Switch8bit
Matrixmult
Matrix2dim16
Matrix2dim8bit
Math32bit
Math16bit
Math8bit
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Code Size Performance M0 code size is 42% and 36% smaller than best MSP430 generic
Floating Point and Fir Filter Code Size 1200 1000 800
MathFloat Firfilter
600 400 200 Cortex-M0
MSP430F5438 large data model
MSP430F5438
0 Generic MSP430
Code Size(bytes)
1400
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Code Size Performance M0 code size is 30% smaller than MSP430F5438 Whet 7000
Code Size (Bytes)
6000 5000 4000 3000 2000 1000 0 Cortex-M0
MSP430F5438 large data model
MSP430F5438
Generic MSP430
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What is CoreMark? Simple, yet sophisticated – Easily ported in hours, if not minutes – Comprehensive documentation and run rules
Free, but not cheap – Open C code source download from EEMBC website – Robust CPU core functionality coverage
Dhrystone terminator – The benefits of Dhrystone without all the shortcomings • Free, small, easily portable • CoreMark does real work
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CoreMark Workload Features Matrix manipulation allows the use of MAC and common math ops Linked list manipulation exercises the common use of pointers State machine operation represents data dependent branches Cyclic Redundancy Check (CRC) is very common embedded function Testing for: – – – –
A processor’s basic pipeline structure Basic read/write operations Integer operations Control operations
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Code Size Performance (CoreMark) M0 code size is 16% smaller than generic MSP430 CoreMark Code size 18000
Code Size (Bytes)
16000 14000 12000 10000 8000 6000 4000 2000 0 Generic MSP430
M0
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Code Size Performance (CoreMark) M0 code size is 53% smaller than PIC24 CoreMark Code size 18000
Code Size (Bytes)
16000 14000 12000 10000 8000 6000 4000 2000 0 PIC24
M0
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Code Size Performance (CoreMark) M0 code size is 51% smaller than PIC18 CoreMark Code size 18000
Code Size (Bytes)
16000 14000 12000 10000 8000 6000 4000 2000 0 PIC18
M0
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Code Size Performance (CoreMark) M0 code size is 49% smaller than Atmel AVR8 CoreMark Code size 18000
Code Size (Bytes)
16000 14000 12000 10000 8000 6000 4000 2000 0 Atmel AVR8 Mega644
M0
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Code Size Performance (CoreMark) M0 code size is 44% smaller than Renesas H8 CoreMark Code size 18000
Code Size (Bytes)
16000 14000 12000 10000 8000 6000 4000 2000 0 Renesas(H8)
M0
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Peripheral code
Part AVR8 ATmega644 MSP430 M0 LPC11xx
Init Code (Bytes) Data rx 28 50 68
code (Bytes) 32 28 30
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Speed Optimization effects
12000
2.00
10000
1.50
8000 6000
1.00
4000
0.50
CoreMark Score Code Size
2000 0
0.00 t0
t1
t2
t3
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Size Optimization effects
1.30
12000
1.25
10000
1.20
8000
1.15
6000
1.10
4000
1.05
2000
1.00
0 s0
s1
s2
CoreMark Score Code Size
s3
37
Size Optimization effects
1.30
12000
1.25
10000
1.20
8000
1.15
6000
1.10
4000
1.05
2000
1.00
0 s0
s1
s2
CoreMark Score Code Size
s3
38
What About Libraries 33% reduction using optimized Libs NXP M0
Auto BM a2time aifftr aifirf aiifft basefp bitmnp canrdr idctrn iirflt matrix pntrch puwmod rspeed tblook ttsprk average (8)
MicroLib Compile Lib 4032 4552 4636 6712 3300 4500 4348 6636 3348 4668 4776 4412 3272 4412 4564 6884 4552 4540 6632 4872 3204 4512 3436 4500 2728 4540 3612 4864 5060 4540 3663
4496
Total 8584 11348 7800 10984 8016 9188 7684 11448 9092 11504 7716 7936 7268 8476 9600 8159
Standard Lib Compile Lib Total 4084 9364 13448 4708 12668 17376 3356 8388 11744 4402 12284 16686 3404 10460 13864 4828 8328 13156 3328 8328 11656 4616 13012 17628 4608 8388 12996 6684 10716 17400 3260 8412 11672 3492 8388 11880 2780 8328 11108 3668 10728 14396 5116 8388 13504 3717
8491 12208
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Performance
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Computation Performance
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uSec
Computation Performance
16 bit FIIR filter performance at 1MHz
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Computation Performance CoreMark Score
Coremark (Mark/sec)
1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 PIC18
Renesas (8 bit)
AVR8 ATMega644
MSP430
M0
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Cost
44
Does the core size matter? The M0 core is the smallest cortex core About 1/3 of the M3 for similar configuration Similar size to 8 bit cores
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Core Size Matters Normalized Cost As a Function of Flash Memory Size
Normalized Cost
2.50 2.00 1.50 1.00 0.50 0.00 32
64
128
256
512
Memory Size
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Tools
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MCU Tool Solutions
NXP’s Low cost Development Tool Chain Rapid Prototyping Online Tool
Traditional Feature Rich Tools (third party)
48
NXP’s FIRST Low Cost Toolchain
Eclipse-based IDE
Evaluation
LPCXpresso Starter Board
Product Development
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LPCXpresso LPCXpresso will provide end-to-end solution from evaluation all the way to product development Attractive upgrade options to full blown suites and development boards LPCXpresso will change the perception about NXP’s solution for tools Key competition: – Microchip MPLAB – Atmel AVR Studio
“LPCXpresso will change the Tool Landscape for NXP” 50
LPCXpresso Components NXP has created the first single perspective Eclipse IDE This offers the power and flexibility of Eclipse in combination with a simple and easy to learn user interface Supports all NXP products (currently up to 128k) LPC3154 HS USB download and debug engine LPC134x Target board
LPC3154
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Evaluation
LPC3154
The target board is very simple with one LED and a layout option for USB Traces between the two boards can be cut, to allow SWD connection to any customer target. (Eval target can be reconnected by jumpers)
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Exploration
LPC3154
LPC13xx Base board
Customers can upgrade to full version of Red Suite (Discount coupon) Customers can buy an add-on EA base board that connects a wide range of resources to the I/O and peripherals of the LPC13xx. Customers can also upgrade to other EA boards (Discount coupon)
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Development
LPC3154
Customer’s own board which will use JTAG
Traces can be cut and the LPC13xx target board will out of the picture Customers can then use the JTAG connection to download code into their own application board using the same existing IDE and JTAG connector Note: Customers can directly jump to this stage and use LPCXpresso for their complete application development without ever having to upgrade
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mbed LPC1768 Value Proposition New users start creating applications in 60 seconds Rapid Prototyping with LPC1700 series MCUs – Immediate connectivity to peripherals and modules for prototyping LPC1700-based system designs – Providing developers with the freedom to be more innovative & productive
mbed C/C++ Libraries provide API-driven approach to coding – High-level interfaces to peripherals enables rock-solid, compact code – Built on Cortex Microcontroller Software Interface Standard (CMSIS)
Download compiled binary by saving to the mbed hardware – Just like saving to a USB Flash Drive
Tools are online - there is nothing to configure, install or update, and everything works on Windows, Mac or Linux Hardware in a 40-pin 0.1" pitch DIP form-factor – Ideal for solderless breadboard, stripboard and through-hole PCBs 55
First Experience – Hassle-Free Evaluation
Remove board from the box
Plug it in…
Up pops a USB Disk linking to website
No Installation!
Save to the board and you’re up and running
“Hello World!” in 60 seconds
Compile a program online 56
mbed Technology USB Drag ‘n’ Drop Programming Interface ►
Nothing to Install: Program by saving binaries
►
Works on Windows, Linux, Mac, without drivers
►
Links through to mbed.org website
Online Compiler
#include “mbed.h”
►
Nothing to Install: Browser-based IDE
►
Best in class RealView Compiler in the back end
►
No code size or production limitations
High-level Peripheral Abstraction Libraries
Serial terminal(9,10); AnalogIn temp(19);
►
Instantly understandable APIs
►
Object-oriented hardware/software abstraction
►
Enables experimentation without knowing MCU details
int main() { if(temp > 0.8) terminal.printf(“Hot!”); }
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Example Beta Projects - Videos Rocket Launch –
http://www.youtube.com/watch?v=zyY451Rb-50&feature=PlayList&p=000FD2855BEA7E90&index=11
Billy Bass –
http://www.youtube.com/watch?v=Y6kECR7T4LY
Voltmeter –
http://www.youtube.com/watch?v=y_7WxhdLLVU&feature=PlayList&p=000FD2855BEA7E90&index=8
Knight Rider –
http://www.youtube.com/watch?v=tmfkLJY-1hc&feature=PlayList&p=000FD2855BEA7E90&index=4
Bluetooth Big Trak –
http://www.youtube.com/watch?v=RhC9AbJ_bu8&feature=PlayList&p=000FD2855BEA7E90&index=3
Scratch Pong –
http://www.youtube.com/watch?v=aUtYRguMX9g&feature=PlayList&p=000FD2855BEA7E90&index=5
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More information Available from NXP Distributors and eTools Boards cost $99 Learn More: http://www.standardics.nxp.com/support/development.hardware/mbed.lpc176x/ http://mbed.org
Featured Articles: – Circuit Cellar – Elektor
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Rapid Prototyping for Microcontrollers
60
What’s happening in Microcontrollers? Microcontrollers are getting cheap – 32-bit ARM Cortex-M3 Microcontrollers @ $1
Microcontrollers are getting powerful – Lots of processing, memory, I/O in one package
Microcontrollers are getting interactive – Internet connectivity, new sensors and actuators
Creates new opportunities for microcontrollers
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Rapid Prototyping Rapid Prototyping helps industries create new products – Control, communication and interaction increasingly define products – Development cycles for microelectronics have not kept pace
3D Moulding
3D Printing
2D/3D Design
Web Frameworks
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mbed Getting Started and Rapid Prototyping with ARM MCUs – Complete Targeted Hardware, Software and Web 2.0 Platform
Dedicated Developer Web Platform
Lightweight Online Compiler
Rapid Prototyping for Microcontrollers High-level Peripheral APIs
LPC Cortex-M MCU in a Prototyping Form-Factor
63
mbed Audience mbed’s focus on Rapid Prototyping has a broad appeal Designers new to embedded applications – Enables new designs where electronics is not the focus
Experienced embedded engineers – Enables fast proof-of-concepts to reduce risk and push boundaries
Marketing, distributors and application engineers – A consistent platform enables effective and efficient demonstration, support and evaluation of MCUs
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Conclusion LPC1100 Family Based on the Cortex-M0 core – There are many users of 8 and 16 bit microcontrollers that are reluctant to use 32 bit architectures citing either overkill or complexity. – The M0 is an architecture that makes this argument irrelevant. – The LPC ARM Cortex-M0 family provides a microcontroller that is very low power, has better real-time performance than microcontrollers of lower bit width and provides a bridge to the full spectrum of the LPC families.
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