1st Experiments: make mirror-. MOT and then ... Deposit gold mirror (Ti/Pt adhesion layer). ... Dielectric. Coatings. ~100 μm. Si. Cavity design. Chord = 33.9 μm.
Engineered high finesse micro optical cavities
Atom Chips at Sandia
Optimized fabrication gives smooth micro-optical cavity templates
K. Fortier, P. Schwindt, M. Blain, D. Stick, T. Loyd, M. Mangan, G. Bedermann, J. Hudgens
1 μm SiO2 aperture, 60 min F* chemical downstream etch, 100 μm SF6 plasma smoothing, 2 μm oxidation + strip
Sandia is a multiprogram laboratory operated by Sandia Corporation, a Lockheed Martin Company, for the United States Department of Energy’s National Nuclear Security Administration under Contract DEAC04-94AL85000.
JM Geremia, Univ. of New Mexico Hideo Mabuchi, Stanford University
Failure current [A]
Properties of current atom chip • Wire material: Al, 0.5% Cu • Substrate material: Si • Wire thickness: 2.5 μm • Distance from wire to mirror: 1.5 μm
Fiber Hemisphere R = 62.7 μm
Low resitivity Si Chord = 70.5 μm
Chord = 57.1 μm ~100 μm
Hemisphere R = 68.6 μm
Optical Field
Si M. Trupke, E.A. Hinds, S. Eriksson, E.A. Curtis, Z. Moktadir, E. Kukharenka, M. Kraft, Appl. Phys. Lett. 87, 211106 (2005).
Spherical mirror fabrication Deposit SiO2 and photo resist. Pattern photo resist. SiO2: 2 μm
Surface Roughness
AFM measurements at bottom of mirror
Strip SiO2 with HF. Smoothing etch with SF6 and Ar plasma.
Photoresist Si
Si
1st plasma etch
2nd plasma etch
Oxidation
Anneal
Wet etch
1
1.13
0.67
-
-
0.30 cavity 0.30 field
2
0.98
0.62
0.55
0.48 well 0.66 field
0.46 cavity 0.58 field
Yes
0.216 cavity 0.218 field
3
Thermal oxidation smoothing.
SiO2: 2 μm
Units: nmrms; 1 µm SiO2 aperture Wafer
Si
Plasma Etch SiO2 SiO2 Si
0.94
0.85
Post 1st plasma etch AFM scan, Wafer 1
0.48
Scattering loss v. surface roughness
Strip SiO2 with HF.
SiO2: 2 μm
Si
(
− 4πσ
Loss = 1 − e
-4
10
)
2
λ
Cavity Measurements
2
Thermal loading of chip 50
100
150
200
Al wire sidewall
Dielectric Mirror R @ 780 nm = 99.97%
Wire Optical Field
Gold Mirror R @ 780 nm = 99.92%
0.1
SiO2
Cross section of the atom chip across a wire bonding pad
SiO2: 200 nm
Chemical mechanical polish
Al: 2500 nm
Al: 2500 nm
SiO2: 200 nm Si
Deposit photo resist and pattern. Etch SiO2 for contact pads or vias.
SiO2: 200 nm
SiO2: 4000 nm
Al: 2500 nm
SiO2: 200 nm Si
Si
Deposit SiO2 and photo resist. Pattern photo resist. Photo resist Al: 2500 nm
After this step the process can be repeated to add another layer of wires.
SiO2: 5000 nm
Au: 200 nm
SiO2: 200 nm Si
Al: 2500 nm
Atom Chip
• Enable photon mediated interactions between atoms trapped in optical cavities.
• Trap atoms in a remote mirror-MOT and magnetically transport to the individual cavities.
• Atom chip testing apparatus assembly including vacuum chamber and laser systems is complete Laser • 1st Experiments: make mirror- Cooling MOT and then magnetically trap Beams atoms on the atom chip • Chamber has good optical access • Atom chip is mounted on a polyimide circuit board Atom chip mounted in a • Rapid changing of the atom chip spherical octagon with a modular design. • DFB lasers with frequency offset locking for the MOT.
Atom Chip
Macro U
SiO2: 5000 nm SiO2: 200 nm Si
Al: 2500 nm
Atom Chip
SiO2: 4000 nm SiO2: 200 nm Si
SiO2: 4000 nm SiO2: 200 nm Si
Polyimide Board
Multi Pin Connector
Atom Chip Assembly
Lift off resist Au: 200 nm
4
Optical Fiber Fiber Connection
Deposit photo resist and pattern. Deposit gold mirror (Ti/Pt adhesion layer).
Block out plasma etch Al: 2500 nm
SiO2: 4000 nm
Si
Cl plasma etch the aluminum
10 1
Atom
0.24 nm
Cavity Length
Patterned Conductor Fabrication
Al: 2500 nm
5
-6
10
Sandia Atom Chip Testing Apparatus
Photo resist
10 -5
10
Electrostatically actuated mirror
Expected at 780 nm: Measured at 852 nm: strong coupling regime Experimental Finesse = 4200 Finesse = 1750 g0 = 3.3 x 109 s-1 Cavity Length = 40 μm Expected Finesse = 2400 κ = 6.7 x 109 s-1 g02/κΓ = 100 Cavity Length = 15 μm 2 g0 /κΓ = 36 Q = 60,000
SEM image
Deposit Al (0.5% Cu) and photo resist. Pattern photo resist.
6
Integrated Opto-Atomic Circuit
Si
SiO2
Si
Prior to SiO2 and Au coating Caltech conductor pattern
10
Surface Roughness, σ [nmRMS]
4
0
Al
Chord = 70.5 μm
Si
Conductor width [μm] Ideal scaling of maximum current: Imax α wh1/2
Al
Hemisphere R = 68.6 μm
6
Au Au
Chord = 106 μm
Data Linear fit first three points
8
0
The atom chip
Dielectric Coatings
In vacuum
10
High resistivity Si
Chord = 33.9 μm
Cavity design
Chemical downstream etch with fluorine radicals
Failure current of Al wires
• High current carrying capability. • Low sidewall roughness • Multi layer capability • Top surface mirror for mirror-MOT as close to the conductors as possible
Before plasma etch 1 μm SiO2 aperture
Reflected power
Goals
Magnetic Micro Traps
Open access Fabry-Perot cavity Finesse > 10,000 Low mode volume Process compatible with Al wire process
Cavity Finesse
1. H. Mabuchi, M. Armen, B. Lev, M. Loncar, J. Vuckovic, H. J. Kimble, J. Preskill, M. Roukes, and A. Scherer, Quantum Information and Computation, 1, 7 (2001). 2. Y.-J. Wang, D. Z. Anderson, V. M. Bright, E. A. Cornell, Qu. Diot, T. Kishimoto, M. Prentiss, R. A. Saravanan, S. R. Segal and S. Wu, Phys. Rev. Lett. 94, 090405 (2005). T. Schumm, S. Hofferberth, L. M. Andersson, S. Wildermuth, S. Groth, I. Bar-Joseph, J. Schmiedmayer, P. Kruger, Nature Physics, 1, 57 (2005).
• • • •
Fractional Scattering Loss
Much like laser cooling in the 1990's, atom chip technology today is rapidly gaining popularity as a convenient and powerful approach to achieving precise control over an atom’s motion and internal state. While great success has been achieved in magnetically manipulating the atoms, integrating optical elements onto the atom chip is an active area of research. Premier applications for these “optoatomic circuits” can be foreseen in both quantum information science1 and in quantum sensors.2 At Sandia, our efforts are focused on developing atom chips for quantum information processing applications in collaboration with researchers at the University of New Mexico and California Institute of Technology. Our atom chips will contain patterned conductors forming magnetic traps and guides integrated with open access optical cavities. Although at first, the magnetic trapping chips and the optical cavities will be developed separately, later efforts will be focused on integrating the fabrication process.
Collaborators:
Silicon substrate type
Goals
First Atom Chip shipped to Mabuchi Group March 2008
Sandia is a multiprogram laboratory operated by Sandia Corporation a Lockheed Martin Company, for the United States Department of Energy’s National Nuclear Security Administration under Contract DE-AC04-94AL85000
