Automatic Generation of Error Control Codes for

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Automatic Generation of Error Control Codes for Computer Applications Franco Fummi #

Donatella Sciuto #

Cristina Silvano z

z

Politecnico di Milano Dip. di Elettronica e Informazione Milano, ITALY 20133

Universita di Brescia Dip. di Elettronica per l'Automazione Brescia, ITALY 25123

Abstract | This paper proposes a methodology, implemented in a tool, to automatically generate the main classes of Error Control Codes (ECCs) widely applied in computer memory systems to increase reliability and data integrity. New code construction techniques extending the features of previous Single Error Correcting (SEC) - Double Error Detecting (DED) - Single Byte Error Detecting (SBD) codes have been integrated in the tool. The proposed techniques construct systematic odd-weight-column SEC-DEDSBD codes with Odd-bit-per-byte Error Correcting (OBC) capabilities to enhance reliability in high speed memory systems organized as multiple-bit-per-chip or card. The proposed tool chooses the best suited error control code for the characteristics of the application and the design constraints and returns the VHDL description of the encoding/decoding circuits. The tool has been successfully applied for the design of a 64 data bit ECC contained in an ASIC designed for a multiprocessor system. Keywords | Computer Memory Systems, Error Control Codes, Memory Reliability, VLSI Architectures.

matrix, the VHDL description of the encoder/decoder and the related performances. The tool can be used in parallel to any VHDL-based commercial design ow, since the generated VHDL models can be considered as a set of models in the VHDL-based hierarchical design description at system level. The methodology allows the evaluation of architectural trade-o s according to prede ned optimization criteria such as area, clock frequency, power consumption and so on. Several codes with byte error control capabilities have been proposed in literature [2]. Single error correcting - single byte error detecting (SEC-SBD) codes (indicated also as SEC-SbED where b is the byte length) have been introduced in [3], [4]. Errors are corrected if they are single random errors, but the class of detectable errors includes also double random errors (SEC-DED-SBD) in [5] and, for byte lengths b greater than or equal to 5, in [3]. SEC-DEDSBD codes have been proposed also in [6] for b = 4, in [7] for b  5, in [4] for b  7 and in [8] for even byte length. Other approaches [9], [10], [11] have presented single byte error correcting - double byte error detecting (SBC-DBD) codes (indicated also as SbEC-DbED). However, the construction of optimal SEC-DED-SBD or SBC-DBD codes for the general case with the minimum number of check bits is still an open and challenging problem. To increase the reliability level of a computer memory system with respect to those systems employing conventional SEC-DED-SBD codes, the authors proposed new code construction techniques [12] providing systematic odd-weight-column SEC-DED-SBD codes in which the class of correctable errors also includes any odd weight error pattern in a single byte by adding redundancy. A few additional check bits (at most four) are required by the proposed codes with respect to SEC-DED-SBD codes in order to extend the protection including the correction of at least 50% of the possible multiple errors per byte. However such an overhead is reasonable with respect to the redundancy of SBC-DBD codes: the proposed codes require almost half of the redundant bits with respect to those required by SBC-DBD codes for b > 8. This paper extends the works presented in [13] and in [14], and shows also that the proposed codes are suitable for high performance VLSI implementations in computer applications, by using high speed encoding/decoding circuits and parallel data processing.

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I. Introduction

To meet the increasing requirements of system reliability and data integrity, Error Control Codes (ECCs) have been widely exploited in the design of computer memory subsystems [1]. The error correcting capabilities of a code represent an e ective mean of increasing fault tolerance in computer applications: the memory subsystem fails only when the errors exceed the error correcting capabilities of the code. On the other hand, error detecting capabilities of a code aim at avoiding data loss, thus the ECC should have the capability of detecting the most likely errors that are uncorrectable. The memory organization and the distribution of memory failure modes represent the major factors in de ning the best class of codes for a given application. Other factors, such as the number of redundant bits, the area and the speed required by encoding/decoding circuits, have to be considered during the choice of a code for a computer memory subsystem. This work aims at providing a methodology, implemented in a modular and ecient tool, to automaticallydesign ECCs and the corresponding encoding/decoding logic from the code speci cations. The proposed tool, called GECO (GEnerator of COdes), integrates the main classes of codes suitable for high performance computer applications, as identi ed in literature. However, its modularity allows an easy introduction of new classes of codes. In particular, the tool automatically generates the parity check

The paper is organized as follows. Section II proposes an overview of the methodology and the derived architecture of the software advisor, while the main strategies applied to implement the code classes considered in GECO are examined in Section III. The same section brie y describes the new codes construction techniques (a formal description of these techniques can be found in [12]), while Section IV shows the main advantages o ered by these codes and how these codes can be implemented as VLSI circuits. Finally, some application results are given in Section V. II. Automatic insertion of ECCs into VLSIs

The aim behind the use of the proposed tool GECO is to provide system designers with an easy-to-use software advisor to increase the design time during the development of ECCs and the corresponding logic. The user-friendly interactive interface allows the user to choose among the code classes and code parameters, mainly the number of data bits (k), the number of check bits (r) and the byte length (b). GECO has been developed by using the object oriented methodology and the C + + language. Figure 1 schematically represents the GECO architecture, which is composed of the following main modules: the User Interface, the Controller, the Generator, the Separator, the VHDL Translator and the Internal Functions Manager such as the Galois eld Manager. User Interface

Controller

Generator Separator

- SEC-DED codes - SEC-DED-SBD codes - SEC-DED-SBD-OBC codes - SBC-DBD codes - DEC-TED codes

Internal Functions Manager

Internal Functions Library

VHDL Translator

Parity Check Matrix

VHDL Models

To EDA Design Flow

Fig. 1. The architecture of the GECO system.

A. The Controller According to the object oriented approach, the Controller is a virtual class from which as many classes as the corresponding classes of codes have been derived. Each Controller class contains the knowledge on the parameter relations and possible code construction techniques. When the User Interface receives a request from the user to change the value of a code parameter, the Interface addresses the request to the Controller. First the Controller veri es if the request is in the allowed parameter range, then the relations among the code parameters are recomputed. When the parameter values satisfy the user, the

Controller calls the Generator to activate the corresponding optimal construction algorithm. B. The Generator The Generator module consists of a set of functions implementing the code construction algorithms for every code class and parameter con guration. Up to now, the ve classes of codes described in Section III are included in the Generator. Some algorithms use specialized objects to implement di erent algebras such as the Galois elds algebra. C. The Galois Field Manager The nite elds of 2m elements (m > 1), called Galois elds GF(2m ), play a primary role in algebraic coding theory [2], [15], thus a dedicated object has been developed to manage the GF(2m ). The object is based on the two di erent representations of the elements in GF(2m ): the power representation and the polynomial representation [15]. Using the power representation, each element in GF(2m ) is expressed as the two elements 0 and 1 or as some powers of a primitive element : the set 0; 1; ; 2; : : :; 2m?2 represents the Galois eld of 2m elements in power representation. From this representation, the polynomial expression corresponding to i for i = 0; 1; 2; : : :; 2m ? 2 can be obtained as in [15]: i = a0 + a1 + a2 2 + : : :+ am?1 m?1 , where each component ai is an element from the binary eld GF(2). Using the polynomial expression, the (2m ? 1) nonzero elements in GF(2m ) can be represented by (2m ?1) distinct nonzero polynomials of over GF(2), with degree (m ? 1) or less [15]. The power representation is useful for multiplication, since the product of two elements i and j can be performed by adding their exponents and considering that 2m ?1 = 1. On the contrary, the polynomial representation and its corresponding m-tuple representation is useful for addition, since the sum of two elements can be obtained by adding the corresponding components of each m-tuple representations, using the modulo-2 addition. The duality in the representation has been implemented in the GF(2m) Manager: the generic nonzero element of GF(2m ), by using the power representation, has been de ned by the integer i (i = 0; 1; 2; : : :; 2m ? 2) corresponding to the exponent of i. By de nition, the integer i = ?1 has been associated with the zero element, while i = 0 with the element 0 = 1. On the other hand, the generic nonzero element of GF(2m) using the m-tuple representation has been de ned as a string of m characters, where each character is 0 or 1. The physical representations of GF(2m ) for di erent values of m in the range 3 < m < 10 are stored in m les, being each le a stream of 0 or 1 characters. For each m, the minimal polynomial of has been used to generate the eld. The generic nonzero m-tuple corresponding to the element i is addressed in the stream le using as index i (by default the zero m-tuple is not stored in the stream le, in fact the index 0 addresses the 1 element). Any function included in GECO can interact with the GF(2m ) Manager, asking for elements of GF(2m ) and functions representing possible operations among the elements.

D. The Separator The Separator algorithm transforms a non-systematic code into a systematic or at least a separable code. This operation is always possible [3], [11], thus all code construction schemes generating non-systematic codes, call, as last operation, the Separator to derive the nal parity check matrix in systematic or, at least, separable form. As a matter of fact, the information bits appear unchanged in the codeword and it is not necessary that they appear in the leftmost (n ? r) positions of the codeword, as in the case of systematic codes. In any case the information bits are maintained separated from the check bits, so that the encoding/decoding and the data processing can be performed in parallel and all information bits read out of the memory appear unchanged. As basic de nition, a binary linear block code C can be described as the null space of a binary vector space generated by the row vectors of an (r  n) matrix called parity check matrix and indicated as H(rn), with n being the length of the codeword composed of k data bits and r check bits. A n-bit row vector X is a codeword in C if and only if HX T = 0, where X T denotes the transpose of X. When the H matrix is expressed as H = [BIr ], being B an (r  k) matrix and Ir the (r  r) identity matrix, then the code is called systematic. Given r, the Separator algorithm searches for a set of r columns of H(rn) in order to nd a submatrix of H, called A(rr) that is non-singular, thus invertible. Once the submatrix A is obtained, the inverse matrix A?1 is computed and nally the A?1H product is performed to obtain the parity check matrix in separable/systematic form. The algorithm can require a large amount of computation time for high values of n or r: in fact for a H(rn) it canrequire,  in the worst case, the computation of the rank n of r matrices of size (r  r). Thus, for some classes of codes some heuristic methods have been identi ed and implemented, such as in the case of SEC-DED-SBD codes proposed by Reddy in [3]. The method derives the columns of the A submatrix by selecting the b-columns of a generic byte of the parity check matrix H and every rst column of the other distinct bytes of H until r-columns have been identi ed. Then the method checks if the A matrix is invertible, otherwise the procedure is repeated with another group of b-columns and so on. E. The VHDL Translator Finally, the VHDL Translator reads the code characteristics and the parity check matrix and generates the VHDL hierarchical description of the basic blocks implementing the code: check bit generator, syndrome generator, syndrome decoder and error corrector. Two architecture bodies are de ned for each of these entities, to have both structural and behavioral descriptions. A deeper decomposition of these entities into lower level entities results in a hierarchy of design entities to be inserted in a system level VHDL description as ECC building blocks.

III. Implementation of code construction techniques

The main features of the ve classes of codes considered in GECO are examined in this section, to outline their application advantages and the implementation strategies adopted. In general, the overall complexity of the parity check circuits required by the given codes can be roughly estimated by examining the structure of the parity check matrix H. Basically, the global number of 1s in H determines the complexity of the hardware required: a lower number of 1s requires a less complex circuit [2]. In particular, in systematic codes the total number ti of 1s in the i-th row of H is related to the number of logic levels necessary to generate the corresponding check bit (Ci ) or syndrome (Si ), as described in [16]. Assuming the use of a v-inputs module 2 adder, the number of logic levels required to generate Ci and Si are respectively given by lCi = dlogv (ti ? 1)e and lSi = dlogv ti e, where dxe indicates the smallest integer greater than, or equal to, x. Therefore to obtain the fastest generation of check and syndrome bits, all ti for i = 1; 2; : : :; r should be minimum and equal, or as close as possible, to the average number given by the total number of 1s in H divided by the number of rows (r). A class of codes satisfying such criteria is called a minimum-equal-weight code [2]. Finally the n-modularized codes, whose encoding/decoding logic can be organized as n identical modules [10], have been preferred for their implementation advantages.

A. SEC-DED CODES The Hsiao codes [16] have been implemented, since they satisfy the criteria of minimum-equal-weight code, the H matrix is systematic and the code is an odd-weight-column code. A code C is said to be an odd-weight-column code [16] if there exists a parity check matrix for C composed entirely of column vectors of odd weight, where the weight of a vector is the number of its nonzero bits. The Hsiao codes represent the optimal minimum odd-weight-column SEC-DED codes. B. SEC-DED-SBD CODES SEC-DED-SBD codes are useful to maintain data integrity in byte-organized memories, where the probability of byte errors is high. Both Reddy codes [3] and Chen codes [5] can be generated by GECO. Being these codes non-systematic, the Separator is called to convert them into a separable form. For a given set of values (k; r; b), the construction technique of H(rn) for Reddy codes is based on the composition of as many submatrices Hi rb as the number of bytes in the codeword. Each submatrix Hi is composed of two submatrices following two techniques, for b even or odd respectively, as illustrated in [3]. Chen codes can be constructed following several techniques as described in [5]. In particular, the rst two techniques can be applied to a prede ned SEC-DED-SBD code to obtain a new code with the same properties, but with (r + 1) redundant bits and (b + 1) bits per byte respectively. (

)

C. SEC-DED-SBD-OBC CODES The new class of SEC-DED-SBD-OBC codes described in [12] has been included in GECO, since it extends the protection provided by SEC-DED-SBD codes by adding few redundant bits and o ering implementation advantages, as shown in Section IV. As in the Reddy codes, the construction technique of H(rn) is based on the composition of as many submatrices Hi rb as the number of bytes in the codeword. Depending on the values of (r; b), three techniques have been de ned to get the Hi as in [12]. In particular, the rst technique (C1) requires r = 2b, the second technique (C2) requires r > 2b and the third technique (C3) requires b + 2  r < 2b. In C1, the matrix B(rk) is de ned as: (

)

B(rk) = [B1 B2 : : : Bi : : : BK0 B10 B20 : : : Bi0 : : : BK0 0 ]

where Bi =

h

Hi Ib

i

for i 2 [1; 2; : : : K0 ]; Bi0 =

h

i Ib Hi for i 2 [1; 2; : : : K0 ]

and Ib denotes the (b  b) identity matrix, Hi is a (b  b) matrix having its column vectors equal to each other (the generic column of Hi is a nonzero b-tuple of even weight over GF(2)) and K = 2K0 . Let ci be the generic b-bit column vector of Hi and Sb?1 the (b?1)-dimensional subspace of the nite eld GF(2b) composed of the 2b?1 distinct btuples of even weight over GF(2), it is possible to de ne a set of (2b?1 ? 1) vectors ci and consequently a set of (2b?1 ? 1) matrices Hi corresponding to the (2b?1 ? 1) distinct nonzero b-tuples of Sb?1 . Hence the function K(r; b) is given by K(r; b) = 2b ? 2. For example, the C1 scheme can be applied to b = 4 to yield a systematic (64, 56) SECDED-SBD triple-bit-per-byte ECC represented by the following matrix:

i h H(864) = HI41 HI42 HI43 HI44 HI45 HI46 HI47 HI41 HI42 HI43 HI44 HI45 HI46 HI47 OI44 OI44

where: H1 =

"1 1 1 1# 1 1 1 1 0 0 0 0 0 0 0 0

H5 =

H2 =

"1 1 1 1# 0 0 0 0 1 1 1 1 0 0 0 0

"0 0 0 0# 1 1 1 1 0 0 0 0 1 1 1 1

H6 =

H3 =

"1 1 1 1 # 0 0 0 0 0 0 0 0 1 1 1 1

"0 0 0 0# 0 0 0 0 1 1 1 1 1 1 1 1

H7 =

H4 =

"0 0 0 0# 1 1 1 1 1 1 1 1 0 0 0 0

"1 1 1 1# 1 1 1 1 1 1 1 1 1 1 1 1

D. SBC-DBD CODES The Single Byte Error Correcting - Double Byte Error Detecting (SBC-DBD) codes implemented in GECO are based on the Reed-Solomon techniques [10] to get systematic codes. Extension techniques, de ned in [9], [10] and [11], are used to derive non-systematic codes with greater values of r and n. The construction of Reed-Solomon codes is based on the GF(2b), having as elements the power matrices (b  b) of a non-singular binary matrix T(b  b), called \companion matrix" of an irreducible polynomial of degree

b, with binary coecients. A dedicated object, Transformator, has been developed from the primitive polynomial of degree b. The elements of the GF(2b) are addressed by an integer i, representing the exponent ofb the matrix T i in 1 2 2b ?2 the eld ? = fOb; T ; T ; : : :; T ; T 2 ?1 = Ib g. First, a matrix of integer elements Hi is generated, where each integer i corresponds to an element of the GF(2b). Then the Transformator receives as input Hi and b and it returns a binary matrix H, by substituting each integer i of Hi with the corresponding binary matrix T i in the eld. A list of primitive polynomials [15] with the smallest number of terms (for b in the range from 3 to 24) are stored in a le as a string of bit representing the binary coecients of each polynomial g(x). From each g(x), the non singular companion matrix T(b  b) is derived from the binary coecients of g(x) as follows: : : : 0 g0 3 : : : 0 g1 6 01 : : : 0 g2 7 T(bb) = 6 : : : 0 g3 7 5 40 ::: ::: ::: ::: ::: ::: 0 0 0 : : : 1 gb?1 20

0 0 1 0

0 0 0 1

Then, the transformation process requires the computation of the power of the binary matrix T(bb) to obtain the eld ?. The nal parity check matrix H(rb) is: "I I : : : I : : : I b b b b H(rb) = Ib T 1 : : : T i : : : T 2bb?2 Ib T 2 : : : T 2i : : : T 2(2 ?2)

Ib Ob Ob # Ob Ib Ob Ob Ob Ib

E. DEC-TED CODES For a memory sub-system with large capacity or with a high rate of hard and soft errors, the use of a t Error Correcting - d Error Detecting (tEC-dED) code can be effective. However such a code requires high redundancy, thus in practical applications Double Error Correcting Triple Error Detecting (DEC-TED) codes are preferred. A class of DEC-TED codes can be constructed according to the theory of BCH codes [15] that, for a given set of parameter values (k, r and dmin ), can be obtained as cyclic codes from a table containing the corresponding generator polynomial. Then, the generator matrix G of the code can be derived in a straightforward manner, from which the parity check matrix can be computed by GH T = 0. To simplify the operation to get the parity check matrix, it is convenient to transform the G matrix in systematic form G(k  k) = [Ik P(k  r)]. In this case, it is possible to prove that the H matrix is in systematic form and it is given by H(r  n) = [P T (k  r)Ir ]. IV. VLSI implementation of the proposed codes

Coding for high performance computer systems requires design techniques aiming at not only high reliability, but also high speed encoding/decoding and correction circuits and parallel data manipulation to maintain high throughput. In this section, the main features of the proposed codes are examined to outline their advantages from the VLSI implementation point of view.

The implementation advantages o ered by the proposed codes mainly relate to the fact that the codes are systematic odd-weight-column SEC-DED codes with additional byte errors detection and partial correction capabilities and modular structure. Being systematic, the information bits are separated from the check bits, therefore the codes offer the advantage that the encoding/decoding and the data processing can be performed in parallel. The proposed codes do not satisfy the criteria of the minimum-equal-weight codes as the Hsiao codes [16]. However, whenever it is necessary to control a number of data bits lower than the maximum allowed for a given number of check bits, shortened codes [2] can be simply derived from the proposed H matrix by discarding some selected sub-matrices Bi with the purpose of maintaining all ti minimum and equal, thus satisfying the criteria of minimumequal-weight codes. Another class of codes, suitable for VLSI implementation, is the class of modularized codes, whose encoder/decoder can be partitioned into two or more identical modules. In n-modularized codes [10], the parity check matrix can be divided into n parts, called modules, composed of the same row vectors, but placed in di erent positions within the module. The n modules have the property that the same logic block can be applied, resulting in a great

exibility and simplicity during the VLSI implementation. In particular, the codes de ned by C1 are 2-modularized codes, in fact the H matrix: h i H = HIb1 :: :: :: HIbi :: :: :: HIKb 0 HIb1 :: :: :: HIbi :: :: :: HIKb OIbb OIbb 0

where the Ib denotes the (b  b) identity matrix and the matrices Hi (b  b) have been de ned in C1 , can be considered as composed of two modules, Module 0 (M0 ) and Module 1 (M1 ), as follows: h i H = HIb1 :: :: :: HIbi :: :: :: HIKb 0 OIbb HIb1 :: :: :: HIbi :: :: :: HIKb OIbb | {z }| {z 0 } M0

M1

where the (K0 +1)-th byte and the 2(K0 +1)-th byte are the check bytes. The rst b rows of M0 are equal to the last b rows of M1 and vice versa, thus the H matrix de ned by C1 has a 2-modularized organization. For example the above H(864) matrix can be seen as composed of two modules M0 and M1:

i h HM = HI41 HI42 HI43 HI44 HI45 HI46 HI47 OI44 HI41 HI42 HI43 HI44 HI45 HI46 HI47 OI44 {z }| {z } | M0

M1

The proposed high-speed parallel encoding-decoding logic consists of four main blocks: check bit generator, syndrome generator, syndrome decoder and error corrector. The check bit and syndrome generator blocks are constituted by trees of Exclusive-OR gates. The number of inputs for the Exclusive-OR tree for the generation of the i-th check bit corresponds to the number of 1's in the corresponding row of H minus 1, while the number of inputs for the Exclusive-OR tree for the generation of the i-th syndrome

bit corresponds to the number of 1's in the respective row of H. The syndrome decoder is constituted by two main blocks. The rst block, SYNDEC, decodes the syndromes to generate the correction patterns for the single-bit and odd-bitper-byte errors. The second block, SYNCNT, decodes the syndromes and counts the number of asserted syndrome bits. Due to the 2-modularized structure of the H matrix, the SYNDEC block can be described by instancing the same logic block twice. s0 s1 s2 s3

I0

s4 s5 s6 s7

I1

Byte Error Pointers

s0 s1 s2 s3

s4 s5 s6 s7

Single-bit Error Pointers Triple-bit-per-byte Error Pointers

..... Bit Dec.

Bit 0 Err. Pointer

Bit 31 Err. Pointer

Bit 32 Err. Pointer

.....

Bit 63 Err. Pointer

Fig. 2. The SYNDEC logic block for the HM matrix.

In the rst instance (I0 ), the syndromes Si (with i = 0; 1; : : :; b) are used to select the generic column of the matrix Hi and 0b, thus recognizing data and check byte errors (Byte Error Pointers). The syndromes Si (with i = b + 1; b + 2; : : :; r) are used to select each column of Ib , thus recognizing the single-bit errors (Single-bit Error Pointers), and to select each column of the syndrome con gurations related to the odd-bit-per-byte errors (Odd-bitper-byte Error Pointers). Receiving the related pointers as inputs, the same logic structure, called BITDEC, is used to compute the Bit Error Pointers for each data or check bits. The r syndromes received by the second instance (I1 ) are used in the opposite way: Si (with i = 0; 1; : : :; b) for Single-bit Error Pointers and Odd-bit-per-byte Error Pointers while Si (with i = b + 1; : : :; r) for Byte Error Pointers. Globally, I0 and I1 receive the r syndrome bits as inputs and generate the Bit Error Pointers related to M0 and M1 , respectively. The Bit Error Pointers are used by the error corrector block, that simply performs a bit per bit Exclusive-OR between each Bit Error Pointer and the related bit read out of the memory. Figure 2 shows an example of the SYNDEC block for the above HM matrix. The area required is 496 equivalent gates (2-input NAND gates), while the number of gates necessary to obtain each Bit Error Pointer is 7:75 equivalent gates. The propagation delay to obtain the Bit Error Pointers from the syndromes is four gate-levels. The gate count of the proposed code represents approximately a 6% decrease compared to a conventional decoding logic of a (64; 56) minimum oddweight-column SEC-DED code able to correct just single errors. The increase required by the proposed code, in terms of propagation delay, corresponds only to one gate level. Finally, the SYNCNT block receives as inputs the syndromes and recognizes the number of asserted syndrome bits. An example of the logic structure of the SYNCNT

block having four syndromes as inputs is shown in Fig- Corporation and its main characteristics are reported in ure 3. Five mutually exclusive output lines constitute the Figure 4. The ASIC successfully operated at full speed (75 block output, therefore when all syndromes are equal to MHz) at the rst run. zero, then just the output ZERO is active, when just one syndrome is equal to one, then just the output ONE is Process 0:7m DLM CMOS active and so on. Dimensions 11:82mm  11:82mm FOUR

THREE

TWO

Total Equivalent Gates 55000 Internal Nets 11500 Average Pin Per Net 3.9 Max. Operating Frequence 75 MHz Max. Power Dissipation 4 W @ 75 MHz Package 299 CPGA Logic Pins 202 Fig. 4. Main characteristics of the ASIC.

ONE

ZERO

s0

s1

s2

s3

Fig. 3. The SYNCNT logic block with four syndromes as inputs.

V. Application results and concluding remarks

Several classes of codes suitable for high performance computer applications have been examined and new coding schemes have been proposed to extend the protection provided by previous SEC-DED-SBD codes. The new techniques construct systematic odd-weight-column SEC-DEDSBD codes in which the class of correctable errors includes any odd weight error patterns within a single byte. The design of codes is supported by an automatic tool which generates, for a given set of code parameters, the parity check matrix and the VHDL description of the logic blocks implementing the code. This tool has been used to design a 64 data bit error control code1 inserted in an ASIC developed by Bull Information Systems in the R&D Labs of Pregnana (Italy) for a shared memory multiprocessor system [17] based on the PowerPC architecture. The ASIC implements the data cross bar architecture among the main memory, four data channels to processors and the I/O channel and it has been completely described using VHDL. The main logic blocks of the ASIC are the data path for data multiplexing, the control logic realized as a set of Finite State Machines, the ECC logic with 64 data bits and 8 redundant bits and the testability logic to support the standard JTAG IEEE 1149.1 and the ATPG. The simulation was executed at different abstraction levels: system, chip and internal blocks levels. The simulation patterns and the expected outputs for the logical veri cation of the device were completely written in VHDL; a set of patterns to verify the ECC logic was automatically generated and checked using a program written in C language. The ASIC was manufactured using the 0:7m gate array technology supplied by LSI Logic 1

- European Patent Application Number 938330254.4 (1993). - USA Dept. of Commerce, Patent and Trademark Oce, Patent Application Number 08/248140 (1994).

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