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AUTOMATIC LAYOUT DESIGN FOR POWER MODULE Puqi Ning1,3 IEEE Student Member 1

Oak Ridge National Laboratory Power Electronics & Electric Machinery Knoxville, TN 37932 USA

Fred Wang1,2 IEEE Fellow 2

Khai Ngo3 IEEE Senior Member

Department of Electrical Engineering and Computer Science The University of Tennessee Knoxville, TN 37996 USA

Abstract—The layout of power modules is one of the most important elements in power module design, especially for high power densities, where couplings are increased. In this paper, an automatic design process using a genetic algorithm is presented. Some practical considerations are introduced in the optimization of the layout design of the module. Abstract—Layout, genetic algorithms, parasitic parameters

3

Center for Power Electronics Systems Bradley Department of Electrical and Computer Engineering Virginia Polytechnic Institute and State University Blacksburg, VA 24061 USA

obtained from finite element analysis simulation tools or theoretical equation-based calculations [3–6]. According to a survey of the relevant literature, there is still no figure of merit that can be used to find the best layout design for minimum power loss. The fitness of a layout can only be determined based on overall evaluation of the parasitic parameters.

I. INTRODUCTION Parasitic parameters in a module have a detrimental effect on the switching loss and dynamic behavior [1]. They cause voltage overshoot, affect blocking voltage requirements of the power devices, and influence device switching losses. These phenomena are exaggerated when the density increases. In addition, power integration decreases distances, resulting in a bigger impact on the coupling of the current conduction path. To ensure high efficiency and high performance of a high-density power module, efforts are required in the layout design [2]. There are basically two important layout design considerations. First, when the switching frequency is high, large voltage spikes result due to the high di/dt. By reducing the parasitic parameters, the magnitude of these voltage spikes can be reduced [2]. Second, the parasitic parameters between paralleled devices need to be balanced. This helps to achieve equal current distribution in parallel devices, consequently affecting the performance of the whole module. As described in Fig.1, the layout design procedure is usually based on design iterations. Each cycle can generate a layout design result, which can then be compared with other design results. After several iterations the best layout can be chosen from the design candidates. Usually even the best layout candidate is not the best selection for the whole design space. The final selected result still requires a superior layout and will be beneficial in achieving power loss reduction. During the design iterations, devices and power terminals, which are the basic components in layout design, first are geometrically placed by considering the electrical connections. The second step is the routing process, in which the dies and the pads are connected with the copper traces and the wire bonds. Then the parasitic parameters in the designed layout can be

Figure 1. Layout design procedure.

The literature survey also showed that only manual layout designs for power modules have been demonstrated so far [1–9]. The main dissatisfactions with manual layout design are the design speed and the limited choice of candidates. Manual design is always an experience-based process which lacks consistency. Hence, automatic layout design is highly preferred during the iteration process. Using the automatic layout design strategy found in very large scale integration (VLSI) as a starting point, a strategy for automatic layout design of the power module is developed and presented in this paper. II. LAYOUT DESIGN ALGORITHM AND ITERATIONS There are a lot of similar design strategies that can be borrowed from VLSI design to better develop an automatic layout design for power modules. The purpose of VLSI design is to embed an abstract circuit description, such as a netlist, into silicon, creating a detailed geometric layout on a die [10, 11]. As semiconductor fabrication processes improved, automation was facilitated by an improvement in the speed of computers that was used to create a new generation of chips [12, 13]. The characteristics of VLSI design and power module design are compared in Table I.

TABLE I COMPARISON BETWEEN VLSI LAYOUT DESIGN AND POWER MODULE LAYOUT DESIGN VLSI layout design Power module layout design Components

Huge number of devices with regular dimensions

Small number of devices (usually fewer than 20) with irregular dimensions

Routing layer

Usually muitilayer

Usually single layer (wire bond degrade to components)

Steps

Clustering, floor plan, placement, routing

Placement and routing iterations

Routing requirement

Routable

Trace thickness and coupling

Fitness

Minimum footprint, total length (time delay)

Small parasitic parameters, balance between paralleled device, small footprint

Design process

Iterations

Iterations

As shown in Table I, the power module layout design is also an iteration-based comparison with a much smaller number of components and simpler placement and routing. However, unlike the fitness evaluation in the VLSI design, power module layout design requires a parasitic parameter extraction process. Based on these characteristics and the design practicality in VLSI design, the genetic algorithm (GA) is chosen as the automatic design algorithm for power module layout design. GAs are based on natural genetics and are a particular class of evolutionary algorithms that use techniques inspired by evolutionary biology such as inheritance, mutation, selection, and crossover [14]. The GA approach is categorized as a global search heuristic, and as such, GA is a search technique used in computing to find exact or approximate solutions to optimization and search problems. The GA is a stochastic search method that deals with the individuals composed of candidate solutions (population), each of which is generally encoded in a problem-independent representation. During the genetic process, new candidate solutions are evaluated by their fitness and reproduced using the genetic operators such as crossover and mutation [15]. The typical GA process is described in Fig. 2.

Figure 2. Typical genetic algorithm process.

In this paper, layout designs are represented in binary as “DNA” strings of 0s and 1s. Evolution starts from a population of randomly generated individuals and happens over generations. In each generation, the fitness of every individual in the population is evaluated and multiple individuals are stochastically selected from the current population based on their fitness and modified (recombined and possibly randomly mutated) to form a new population. The new population is then used in the next iteration of the algorithm. The algorithm terminates when either a maximum number of generations has been produced or a satisfactory fitness level has been reached for the population [16]. As shown in Fig. 3, there are two loops using GA in this automatic layout design process. The outer loop is the placement loop, in which the components are placed and evaluated based on the design results of the inner loop, which is the routing loop. At the same time, the outer loop also provides the positions of the components in the inner loop. With certain components positioned, the inner loop physically connects the components based on the electrical connection. The routing process is also implemented by GA, and an analytical equation-based parasitic parameter calculation method is used during the fitness evaluation step. After several iterations, the best individual routing result and its fitness are passed on to the outer loop to continue the outer loop iterations. The outer loop uses these routing results as the individual fitness in placement evaluation.

asymmetrically distributed while the lead frame connections are restricted by the mechanical limits or fabrication process, components in layout design should have orientations, and the orientations are always critical to parasitic parameter reduction and the balance between paralleled devices. The orientations are represented by two-digit binary numbers in this paper: 00 means facing up; 01 means facing right; 10 means facing down and 11 means facing left. Thus, the orientation of n components can be represented by a 2n digits string.

Figure 3. Automatic layout design for power module.

III. OUTER LOOP IMPLEMENTATION In the outer loop, a rectangle with a given height and width in real numbers can be substituted for individual components. Then GA can help to choose the best non-overlapping placement for the given components. One important key to solving the problem effectively is the representation of relative position. In [17], a sequence pair (SQ), which is particularly suitable for stochastic algorithms such as GA, has been proposed as the representation of a solution for this problem. The SQ is a pair of sequences of the n component names to present relative positions of n components (Fig. 4). An SQ imposes a horizontal/vertical (H/V) constraint for each pair of components. If two components have the same sequence in horizontal sequence and vertical sequence, it means one component is on the left of the other component because by definition the first component of the horizontal sequence is on the left of the second component of the horizontal sequence. If two components have a different sequence in horizontal sequence and vertical sequence, it means one component is on top of the other component because again, by definition, the first component of the horizontal sequence is on top of the second component of the horizontal sequence.

Figure 5. Sequence-pair representation.

In the components placement process, gaps are required between components. The gap here is defined as the distance from the bottom-left corner of the component to the left boundary or to the bottom boundary. In this report, the minimum distance between components, which is limited by the substrate fabrication process, is 1 mm, and the resolution of distance is also 1 mm. If the largest gap in the placement design is less than 2n mm, the gaps can be represented by an n-digit binary string, as shown in Fig. 6. In this report the horizontal gap string is listed before the vertical gap string.

Figure 6. Gaps for components.

By combining the relative position string, the orientation string, and the gap string, the whole DNA string with 10n digits can comprehensively represent the placement of n components, as shown in Fig. 7. Figure 4. Sequence-pair representation.

As shown in Fig. 4, SQ (123, 231) has three components, and the components have the following sequences: (12, 21), (13, 31) and (23, 23), which represent 1 above 2, 1 above 3, and 2 on the left of 3. With relative positions, the placement of three components is shown on the right part of Fig. 4. In the outer loop, gaps between components can be added without violating the relative positions. As shown in Fig. 5, because the pads on the die may be

Figure 7. DNA string in the outer loop.

For this paper, different numbers were tried for the initial population of the outer loop, and the size of the population was also adjusted based on the number of components. Finally after many attempts, 5n was selected for the population, where n is

the number of components. The fitness of individual placement is evaluated from the inner routing loops (Section IV). In the GA process, there are two important operators; one is crossover and the other one is mutation. One-point crossover and one-point mutation were used for this paper. Because the orientation and the gap placement were conventional binary strings and directly presented, conventional crossover and conventional mutation were used if the crossover point is selected at the last 8n digit of DNA for an n-components design. A conventional crossover means that all data beyond that point in either string are swapped between the two parent strings, and the resulting strings are two children. The conventional mutation means that an arbitrary bit in a genetic string will be changed from its original state. This means that an original 0 changes to 1, while an original 1 changes to 0. If the crossover point is selected at the first 2n digit (relative position genes), a special operation is implemented: common topology preserving crossover (CTPX), a crossover which preserves the common characteristics of the parents with respect to the relative position [18]. In CTPX, first the longest common subsequences (LCSs) of the parents’ SQ are found. Then components in the LCSs are preserved in the same sequence. Other components are exchanged so that the sequence of one offspring is the same as the sequence of one of the parents. One example is shown in Fig. 8.

IV. INNER LOOP IMPLEMENTATION To simplify the routing process, the wire bond routing can be degraded in the components because the wire bond is the largest contributor of the parasitic parameters. As shown in Fig. 10, the wire bond connection provides the length reduction of the wires and the decoupling between gate loop and power loop. The pads of the device are extended to the terminals of the newly defined power unit. This simplification saves placement time and routing time.

Figure 10. Simplification in routing.

Because of fabrication limits, the routing plane is simplified as a two-dimensional (2D) copper trace connection problem, so a 2D binary array, 1 mm × 1mm, can be substituted for the routing space. A 0 represents no copper trace while 1 means there is a copper trace. The 2D binary array needs to be converted to one dimension to obtain easy crossover and mutation operations. One example representation is shown in Fig. 11.

Figure 8. Common topology preserving crossover example.

In this example, the LCSs of the parents are (4765, 7645), and their position will not change in the crossover operation. The rest of the components in the SQ, which are (3281, 1382) and (8213, 8321), exchange position but keep the same sequence. Thus two children (48721653, 78634251) and (43276851, 76143825) are generated. If the mutation point is selected at the first 2n digit (relative position genes), another special operation [18] will be implemented. Compared with crossover operation, mutation is much simpler. Two components in the SQ are selected and exchange positions. An example is shown in Fig. 9.

Figure 11. Routing area representation.

The initial population is randomly generated and chosen from the candidates that follow the electrical connections. The size of the population is chosen as 3n if the rectangle area of placement is n mm2. The fitness evaluation requires considering the parasitic resistance, parasitic inductance, and footprint. In this report the fitness is expressed as

Figure 9. Mutation example.

After crossover and mutation operations, 5n parents will have 10n children. Including parents and children, 5n individuals with the greatest fitness will be kept as the new generation. To keep the diversity of the genes, same individuals will not exist in any generations.

F=

Lparasitc Rparasitc Afootprint

In the above equation, F is the fitness, Lparasitic is commutation path total parasitic inductance, Rparasitic is commutation path total parasitic resistance, and Afootprint is footprint area. The parasitic resistance is calculated from

(1)

the the the the

equations for Kirchhoff’s circuit laws (KCLs), while parasitic inductance is calculated based on the boundary element method to reduce the fitness evaluation time. To calculate parasitic parameters, first the current conduction paths (conductor nets) need to be identified based on the electrical connections as well as the physical routing results. If the current conduction paths don’t meet the requirement of the netlist, the individual fitness is directly defined as zero. Based on the literature, the external power terminals of the power module (lead frame connections to substrate) are assigned as the sink, while the terminals of the dies are assigned as the source. After the identification of the current conduction paths, in each conductor net the sink is applied with 2 V, one source is applied with 1 V, and all other sources included in other conductor nets are applied with 0 V. The routed copper traces are gridded as small squares, and each square is assumed to have an evenly distributed average voltage value. The circuit KCL equations can be determined for each square by assuming that current can only conduct from the top, bottom, right, and left adjacent squares. By solving the KCL equations, the current that goes through each square can be obtained. The total current can be found by adding up the current in all squares of the terminal region. In each conductor net, the calculation for current is implemented separately for each source. Every conductor net goes through this procedure to obtain all the currents. As introduced in [19], the parasitic resistance matrix can be calculated based on the voltages and the currents. One example is shown in Fig.12.

 V1   R11 V    R  2   12  V3   0

R12 R22 0

0   i1  0  i2  , R33  i3 

(3)

where R11, R22, and R33 are the self-resistance of each current path and R12 is the mutual resistance between path 1 and 2. Mutual resistance only applies to the current paths within the same conductor net. The parasitic resistance can be calculated with Equations (2) and (3). Next the system computes the magnetic vector potential, A, given by:

A

0 4

J

 r dV

.

(4)

V

In Equation (4), J is the current density, which can be calculated as above. The inductance matrix is then computed using the following relationship:

Lij   A  J j dV .

(5)

V

With the calculated parasitic resistance and inductance, the routing results can be evaluated, and the fitness can be used in GA iterations. As the DNA string in the inner loop is a conventional binary string, the crossover and mutation follow the conventional operation as introduced in Section III. In each generation, there are 3n individuals, and they will be used as parents. They are stochastically selected to generate 6n children. Including parents and children, 3n individuals with the greatest fitness will be selected as the new generation. To keep the diversity of the genes, same individuals will not exist in any generations. V. EXAMPLE OF AUTOMATIC LAYOUT DESIGN To better explain the GA used in the automatic layout design, one design example is shown in Fig. 13.

Figure 12. Resistance matrix calculation example.

Figure 13. Automatic layout design example

The voltage drops are given by:

 V1  i1 R11  i2 R12  V2  i2 R22  i1 R12 .  V  i R 3 3 33  This can be expressed in matrix form as:

(2)

The example focuses on a phase-leg power module that has two power switches and three terminals. No paralleled devices are considered in this simple case. In the outer loop, the switches and terminals are represented by rectangles with two orientations; all together is 5 components design. The size of the initial population of the outer loop was selected as 25, and the largest gap was set as 4 mm in this example. The best solution, depicted in Fig. 14, was found after 50 iterations.

[7]

[8] Figure14 Automatic layout design result [9]

This example was also designed manually. As it is a very simple case, the best solution found through manual design was similar to that found with automatic design; however, the design time was much longer. The design was also simulated with Ansoft Q3D. Compared with the other layout designs, the fitness of the automatic design results was better. This example proves the ability of automatic layout design. More detailed simulations and verifications for complex cases will be investigated in the future.

[10] [11]

[12]

[13]

VI. CONCLUSION This paper presents a process for automatic layout design for high power density modules. Detailed GA implementations are introduced both for outer loop and inner loop. As verified by a design example, the results of the automatic design process presented here are better than those from manual design and also better than the results from a popular design software. This automatic design procedure could be a major step toward improving the overall performance of future layout design.

[14] [15] [16] [17]

[18]

ACKNOWLEDGEMENT This paper also made use of Engineering Research Center Shared Facilities supported by the National Science Foundation under Award Number EEC-9731677. The authors would also like to acknowledge the help of Dr. Dushan Boroyevich from Center for Power Electronics Systems of Virginia Polytechnic Institute and State University. REFERENCES [1]

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