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Multiprocessor System Interconnects─. Hierarchical Bus and Time Shared bus
Systems and multi-port memory. Chapter 12: Multiprocessor Architectures ...
Chapter 12: Multiprocessor Architectures
Lesson 03: Multiprocessor System Interconnects─ Hierarchical Bus and Time Shared bus Systems and multi-port memory
Objective • To understand multiprocessor system interconnects using system, hierarchal and time shared buses • Use of SEND and RECEIVE functions and multiport memories
Simplest single network using a system-bus interconnection • A contention problem when more than one processor seeks bus access at the same time • Specialized design can solve the contention issue to large extent
Buses in a hierarchical tree-like design of multiprocessors • A root processor with two or more dedicated buses at each node • Each node─ an independent processor and memory
Buses in a hierarchical tree-like design of multiprocessors • Communication─ by message-passing • Each processor node executes a RECEIVE (buffer) operation, wait till SEND not completed • The sending processor executes its matching SEND (data, destination) operation before the RECEIVE operation executes
Buses in a hierarchical tree-like design of multiprocessors • RECEIVE─ a wait operation for taking message when a processor node A raises the need to receive data • SEND ─ message post operation by other processor node B presently using the bus • The processor A gets the needed bus for receiving the data after the SEND
Example of Time-shared System Bus • System bus shares the time slots between Processors, Input-Output Processors (IOPs) and Connects to PCI Bus for I/O Devices
Multiport Memory • A multi port memory has the cells in which there are two or more ports where write can be made to one, while two or more ports can be simultaneously addressed and read
Multiport memory • Supports simultaneous access, sometimes across different bus widths and voltages • When it imposes no delay on either port during a read or write operation, then its maximum performance exceeds the traditional multiplexed SRAMs by a factor of at least two
New synchronous dual-port memories • Collision detection logic support • Speeds up to 200 MHz • Bandwidth up to 1.75GB/s achieved for the multiprocessor systems
