The ASIC interface to an external RF front-end consists of three main modules: the I/Q separator, the decimator, and the AGC controller, as shown in Figure 1.
Rapid Direct P(Y)-Code Acquisition In a Hostile Environment Robert Wolfert, Steve Chen, Sanjai Kohli, Don Leimer, Software Technology and Systems Capt. James Lascody, Sensors Directorate, Air Force Research Laboratory
massively parallel correlator technology have made direct acquisition of the P(Y)-code possible. Difficulties still exist as even small time errors can lead to large search spaces for the P(Y)-code. Small errors in the user reference frequency compound the problem by requiring a frequency search since the long integration periods required to combat the effects of a hostile jamming environment necessitate narrower frequency coverage in each search pass. Using massively parallel correlator technology to implement a two-dimensional search, the STS Y-EXPRESS receiver can search 32,000 timefrequency bins in parallel to directly acquire the P(Y)code in a short time.
BIOGRAPHIES Robert Wolfert received his B.S.E.E. degree from Purdue University and his M.S.E.E. degree from the University of Southern California. Mr. Wolfert currently serves as a senior systems engineer for Software Technology and Systems, a company specializing in advanced GPS technologies and their application to military users. Steve Chen received his B.S.E.E. from the University of Pennsylvania and his M.S.E.E. from the University of Southern California. He is currently the ASIC Design Manager at Software Technology and Systems and has been involved in the implementation of advanced DSP algorithms for military and commercial applications of GPS since 1992.
This paper examines the problems encountered with the practical implementation of massively parallel correlator technology. Data collected in simulations of the Y-EXPRESS signal processor under benign conditions is extrapolated for signal acquisition at J/S values in excess of 50 dB. Data analysis shows both benefits and limitations of massively parallel correlator technology and the feasibility of implementing two-dimensional searches.
Sanjai Kohli is President of Software Technology and Systems. Don Leimer is serving in the capacity of Principal Engineer for Software Technology and Systems. Capt. James Lascody received his B.S.E.E. degree from the United States Air Force Academy, Colorado Springs, Colorado and his M.S.E.E. degree from the Air Force Institute of Technology. He is currently conducting research and development on communications and navigation technology for the Sensors Directorate, Air Force Research Laboratory.
INTRODUCTION The GPS P(Y)-code tolerates broadband and CW jamming better than the lower rate C/A-code. Additionally, when the anti-spoof mode of operation is enabled, the P(Y)-code is far less susceptible to intentional spoofing. For these reasons, direct acquisition of the P(Y)-code is desirable to users operating where these environments exist. The Y-EXPRESS chip was developed to enable direct acquisition of the P(Y)-code in a reasonable amount of time without the need to use the C/A-code for course acquisition. This ability requires the GPS receiver to be initialized prior to the attempted acquisition with sufficiently accurate estimates of user position, velocity, time, and reference oscillator frequency error as well as satellite almanac or ephemeris data. This data must be input to the receiver from an external source.
ABSTRACT Due to its higher tolerance to intentional jamming and spoofing compared to the C/A-code, direct acquisition of the GPS P(Y)-code is a desirable capability for military users. In the past, direct acquisition of the P(Y)-code was impractical due to insufficient user time source accuracy, resulting in lengthy code searches due to the large time errors. Recent advances in the transfer of user time and improvements in time maintenance using stable, low power time sources have eliminated much of the user time uncertainty. These advances, coupled with the use of
353
samples are each 90 degrees out of phase with respect to the previous sample. Therefore, the serial input stream contains interleaved samples from both the in-phase and quadrature portions of the signal. The ASIC executes the requisite sign correction and subsequently separates the data into its in-phase and quadrature components, as mentioned previously.
The uncertainty in the user position and time data define a total time uncertainty window over which a the receiver must search for the correct code phase. Uncertainties in the user velocity and in the reference oscillator frequency (including short term stability) define a total carrier frequency uncertainty window which the receiver must search as well. Combining the two uncertainties defines a two-dimensional time-frequency uncertainty region which the receiver must search to acquire each GPS signal. Conceptually, the two-dimensional search of the uncertainty region may be discretized into resolution cells, each with finite dimensions. Nominally each resolution cell would span one-half of a PN code chip in time and a frequency inversely proportional to the coherent integration period. The signal to be acquired would produce energy in several adjacent resolution cells, however the cell containing the most energy would correspond approximately to the “prompt” code phase and the discrete carrier Doppler offset nearest the true carrier Doppler. In the worst case, all resolution cells in the uncertainty region must be tested before the signal is detected, however under most conditions the search strategy can be tailored to test the most probable resolution cells first, thereby decreasing the average time to acquire.
AGC Controller
To L1 AGC
4
L1 Input from A/D
2
I
2
Q
2
Decimator
2
Decimator
2
I/Q Separator and Sign Correction
4
4:1 MUX AGC Controller
To L2 AGC
4
L2 Input from A/D
2
I
2
Q
2
Decimator
2
Decimator
2
I/Q Separator and Sign Correction
4
To Acquisition or Tracking Channel
4
Figure 1. ASIC Front-end Module Block Diagram The ASIC can independently control external automatic gain control (AGC) circuits for each of the two input ports. The AGC controller for each port has numerous, user-selectable control modes that determine how the AGC output is updated. The AGC outputs can be disabled (locked) independently. When disabled, the controlling software can adjust the output values directly via the microprocessor interface.
The Y-EXPRESS ASIC herein described implements multiple correlators to achieve the capability to search 511 time-domain resolution cells in a parallel fashion for acquisition purposes. The ASIC also implements a fast Fourier transform that extends the parallel testing to a maximum of 64 frequency-domain resolution cells for each time-domain cell. In effect, this massively parallel correlator structure allows the ASIC to search as many as 511 × 64 = 32704 time-frequency resolution cells in a single pass.
TRACKING CHANNEL CORRELATORS The Y-EXPRESS ASIC contains six tracking channels, each capable of independently tracking one frequency (L1 or L2) from a single satellite (it is feasible that several satellite signals could be tracked using the same tracking channel in a multiplexing scheme, but the ASIC has no special provisions to perform this function). Each channel operates independent of the others, but all are identically composed of several modules, as shown in Figure 2. In Figure 2, the modules outside the dotted line are portions of the ASIC front-end module, described in the previous section. They are shown in this block diagram only for clarifying the source of the tracking channel inputs. The front-end module is common to all tracking channels and the acquisition channel.
The design details and capabilities of the Y-EXPRESS ASIC are now presented. ASIC FRONT-END MODULE The ASIC interface to an external RF front-end consists of three main modules: the I/Q separator, the decimator, and the AGC controller, as shown in Figure 1. The purpose of the front-end is to accept sampled, quantized, serial data streams representing the L1 and L2 signals from an external RF chip or circuit, and preprocess the data by separating the in-phase and quadrature components. Additionally, the front-end module can decimate each data stream to twice the C/A-code chip rate, if C/A-code processing is desired. Any combination of the two input ports may be utilized to input data to the ASIC. Each port accepts 2-bit quantized data samples in sign/magnitude format. Numerous frequency plans can be accommodated, but the nominal sampling rate is four real samples per P(Y)-code chip. The ASIC design presumes that the signal sampling will occur at an intermediate frequency such that the real-valued input
Each channel can select the P(Y)-code signal or the decimated C/A-code signal from either input port (L1 or L2) as its input. The selected data stream, composed of in-phase and quadrature samples, is compensated for carrier Doppler by means of multiplication with a complex sinusoid of the appropriate frequency. Carrier Doppler compensation is accomplished by using a numerically controlled oscillator (NCO) to generate the compensation signal for each tracking channel. The software can independently set the initial phase and frequency of each of the carrier Doppler NCOs.
354
2 2
Decimator
I/Q Separator
4
Decimator
I/Q Separator
Register 3
3
3
3
Parallel Correlator
I/Q Separator
Decimator
Register 511 511 511 511
Carrier NCO 4×511
10
Correlator Code NCO
C/A Coder
P-Code (from Tracking Channel) Y-Code (external)
Y-Code (external)
511
Register
10
External 32k×16 RAM
P Coder
4
Q Integrator
Register
Doppler
Parallel
Internal 3×16 Latch
Code NCO
3
4
Q Integrator
C/A Coder
4
2
L2 Input
I Integrator
4×3
For Each Tracking Channel
4
I Integrator
Carrier NCO
L2 Input
Decimator
External 32k×16 RAM
2
Doppler
Internal 3×16 Latch
L1 Input
I/Q Separator
L1 Input
4
User-supplied 50 bps data
Figure 3. Coherent Integration Portion of Acquisition Correlator
Figure 2. Block Diagram of One Tracking Channel The output of each channel’s carrier Doppler compensation module is correlated with a locally generated PN code. Each tracking channel contains its own P-code and C/A-code generators that can be initialized to any code state for any of the available PN codes. Each tracking channel has a second NCO for the purpose of controlling the rate at which the local code is generated, thereby compensating for code Doppler. Again, the software can independently set the initial phase and frequency of each of the code NCOs. Each channel can select the P-code or C/A-code locally generated, or an externally generated Y-code for correlation.
The acquisition channel, like each tracking channel, has its own carrier Doppler compensation module. The initial phase and frequency of the corresponding NCO may be initialized independent of the tracking channel NCOs. The acquisition channel includes its own C/A-code generator, but does not contain its own P-code generator. In lieu of generating its own P-code, it can select the Pcode generated in any of the six tracking channels or the externally generated Y-code associated with any tracking channel. Therefore when using P-code or Y-code, only five of the six tracking channels may be used to track other signals while the acquisition correlator is in use.
Each tracking channel contains a complex-valued 3-tap correlator corresponding to early, punctual, and late code phase. The selected PN code is correlated with the data output from the Doppler module. The correlator output is coherently integrated over an integer number of milliseconds ranging from 1 to 20. The controlling software can independently specify the coherent integration period for each channel. The result of the coherent integration for each tap is stored in two 16-bit registers, one corresponding to the in-phase data and one corresponding to the quadrature data. The register contents are available to the controlling software upon completion of a coherent integration.
The correlator output is coherently integrated for a userspecified period, subject to the following constraints. The complete coherent integration period for the acquisition channel is divided into N equal sub-periods, where N is the number of points in each FFT computation. The value of N is software controlled and can take on the value 8, 16, 32, or 64. Each coherent integration sub-period must contain an integral number of 511-sample segments (the length of the acquisition correlator), up to 127. The ASIC is capable of extending the coherent integration period beyond the 20 millisecond GPS data bit period by “stripping” the navigation data from the received signal. This is accomplished by multiplying the reference PN code by a user-specified bit sequence prior to correlation. Due to hardware constraints in the ASIC, the longest possible coherent integration in this mode is 200 milliseconds. The data-stripping mode of coherent integration is only available for the acquisition channel.
ACQUISITION CHANNEL CORRELATOR The acquisition channel of the Y-EXPRESS ASIC follows the general format of a tracking channel through the coherent integration. The acquisition correlator, however, contains further processing after the coherent integration to obtain expanded frequency information from the signal using its FFT capability. A block diagram of the acquisition channel through the coherent integration portion is shown in Figure 3. As before, the front-end module components are replicated in Figure 3 only for clarifying the source of the acquisition channel inputs. The front-end module components are common to the tracking channels and the acquisition channel. Like each tracking channel, the acquisition channel can select either the P(Y)-code signal or the decimated C/A-code signal from either input port (L1 or L2) as its input.
The results (in-phase and quadrature) of each coherent integration sub-period are stored in external RAM. After completing the N coherent integration sub-periods, a frequency transform is computed using an FFT.
355
quadrature data separation) and supply this data to the remaining chips for further processing. A receiver could be composed of a single RF section and several cascaded Y-EXPRESS chips operating in parallel. This interface can therefore be used to further increase the effective size of the acquisition correlator or to allow the simultaneous tracking of more than six signals.
Figure 4 details the main components of the FFT and subsequent processing. While the FFT is computed for each correlator tap, the coherent integration process is suspended. This is done so the FFT can access the external RAM containing the coherent integration results. 16 External 32k×16 RAM
16
External 32k×16 RAM
32
External 32k×16 RAM
128
FFT Butterfly
32
The ASIC also contains a precise time and time interval (PTTI) interface. The ASIC has input and output pins for the time rollover pulse (1 PPS) and the time code data, as described in ICD-GPS-060 [1]. A time mark pulse output pin is also available from the ASIC, as described in ICDGPS-150 [2].
64 128
128
64 8×32 cosine/sine lookup table
|•|
128
64 16×128 FFT Input RAM
16
Peak Detection Circuitry
128-bit buffer (internal) 16
Non-coherent Sum
16
FFT Butterfly
16×128 FFT Output RAM
The ASIC contains input and output pins and internal logic implementing a universal, asynchronous receivertransmitter (UART). This allows the microprocessor to communicate serially with an external device via the ASIC.
128
64
32
SYSTEM LIMITATIONS
Figure 4. FFT and Non-coherent Summation Modules of Acquisition Channel
The following sections outline the receiver architecture design tradeoffs for the Y-EXPRESS ASIC and quantify the expected signal losses associated with them.
After the FFT computation is complete, the magnitude of the complex-valued result is computed. The resulting magnitude is then non-coherently accumulated in an external RAM bank (“non-coherent RAM”) for a userspecified number of iterations, up to 127.
SEQUENTIAL FFT COMPUTATION The original ASIC architecture called for computation of the FFT in parallel with the coherent integration. With the parallel design came the need for two sets of “coherent” RAM data banks, one to store data from the current coherent integration and a second to hold the data from the last coherent integration for use in the FFT computation. This required a total of five external 32k×16-bit RAM banks. Four of the five would be used in a ping-pong fashion between the coherent integration and the FFT computation. The coherent integration would use two banks for storing the in-phase and quadrature results from the current integration while the FFT would use the two banks containing data from the previous coherent integration as input and would store intermediate FFT results in the banks as well. At the end of a coherent integration, the RAM banks would be switched so the FFT could begin processing the data from the newly completed coherent integration. The fifth RAM bank required under the parallel architecture is used to store the non-coherently summed data after the FFT computation. Use of the parallel architecture would require separate address and data lines for each of the five RAM banks. In order to maintain a reasonable pin count for the final package, the decision was made to perform the FFT computation sequentially following each coherent integration during acquisition. The drawback of using the sequential architecture is that during the FFT computation, the coherent integration process is suspended. Upon completion of the FFT computation, the coherent integration process resumes.
The final result stored in the non-coherent RAM is up to 32704 data values representing the signal energy in 511 time offsets and up to 64 frequency offsets (for each time offset) from the user-selected reference point. As the ASIC is writing data from the final non-coherent summation iteration into the non-coherent RAM, a detection search is performed. The search is conducted in one of two user-selectable modes. In the first mode, the ASIC compares each value being written into the noncoherent RAM to a user-specified threshold. Up to the first six locations where the data value exceeds the threshold will be reported by the ASIC and a flag is set if more than six locations are found to exceed the threshold. In the second detection mode, the six (6) largest values in the entire data set written to non-coherent RAM are reported by the ASIC. The location (time offset and frequency offset) and value of each detected peak are available via the microprocessor interface. ADDITIONAL ASIC FEATURES The Y-EXPRESS ASIC is equipped with a microprocessor interface utilizing an 8-bit address bus and a 16-bit data bus. A microprocessor is required to coordinate the ASIC functions and process its data output. The ASIC was designed to allow multiple chips to operate in parallel using a single RF signal input. The multi-chip interface allows one ASIC to perform the initial signal pre-processing (sign correction and in-phase and
356
Table 2. Loss for Sequential FFT Computation
Table 1. Nominal FFT Computation Times Number of Points, N
Number of Points of Zero-padding, NZ
Compute Time (ms)
8
4
0.4496
8
0
0.6993
16
8
0.6993
16
0
0.9990
32
16
0.9990
32
0
1.3986
64
32
2.3977
64
0
3.1969
Loss (dB) TFFT (ms)
TCI + TFFT = 20 ms
TCI + TFFT = 10 ms
0.4496
0.10
0.20
0.6993
0.15
0.31
0.9990
0.22
0.46
1.3986
0.31
0.65
2.3977
0.55
1.19
3.1969
0.76
1.67
CORRELATOR INTEGRATE AND DUMP LOSS As with a conventional coherent integrate and dump correlator, any frequency error in the received signal will result in a rotation of the signal between the in-phase and quadrature components. This yields a power loss based on the amount of rotation occurring during the integration period. The relative power loss depends on the frequency error and the coherent integration period, as shown in equation 2.
The time period required for FFT computation depends on N, the number of data points in each FFT. Table 1 shows FFT compute times for a system clock of 81.84 MHz (the system clock is nominally 8 times the P-code chip rate). In addition to performing conventional FFT computations, the Y-EXPRESS ASIC is capable of “zeropadding” the data prior to computation to increase frequency resolution and mitigate losses associated with the output spectrum of the FFT. For the Y-EXPRESS ASIC and the purposes of this paper, zero-padding implies that the first N/2 FFT input samples contain data obtained from coherent integration sub-periods while the remaining N/2 input samples are zero valued. A more detailed description of zero-padding and its effects will be provided in subsequent sections.
L
T
CI (Eq. 1) + T FFT Equation 1 assumes that in the absence of the FFT computation, the period of coherent integration would be extended to include the FFT computation time. Table 2 shows the loss for each FFT mode for selected values of (TCI+TFFT). FFT
=
T
=
[sinc(π • f E •T CI )]
2
(Eq. 2)
In equation 2, sinc(x) is [sin(x)/(x)], fE is the frequency error, and TCI is the coherent integration period. Unlike a conventional integrate and dump correlator which dumps its data after the complete coherent integration, the Y-EXPRESS acquisition correlator dumps its data at the end of each coherent integration sub-period. Therefore, the loss for the Y-EXPRESS ASIC depends on the coherent integration sub-period, rather than the complete coherent integration period meaning that the TCI variable in Equation 2 actually represents the coherent integration sub-period. To limit the loss from this effect to 1 dB or less, the maximum searchable frequency span is bounded by the frequency error to be approximately [±1/(4•TSP)], where TSP is the coherent integration sub-period.
The loss associated with the suspension of coherent integration depends both on the FFT compute time and the complete coherent integration period. Equation 1 shows the computation for the relative power loss due to this effect where TCI is the complete coherent integration period and TFFT is the FFT compute time.
L
I &D
CI
FREQUENCIES BETWEEN DISCRETE FFT BINS The FFT, as it is applied in the architecture of the Y-EXPRESS ASIC, estimates signal levels at discrete points in a continuous frequency spectrum. If the frequency of the desired signal lies in between two of the discrete FFT frequencies, it will contribute a portion of its energy to each of the adjacent FFT bins (and to a much lesser degree, to all of the remaining frequency bins). The contribution to each bin depends on the difference between the center frequency of the bin in question and the frequency of the signal of interest, as shown in equation 3.
357
sin N • π = ( ) f LBIN ,i N • sin π
• •
f
i
f
i
−
f
−
f
• T SP • T SP
To restrict this loss to less than 1 dB, the code Doppler shift over the entire non-coherent integration period must be less than ±0.4 chips. This implies that the maximum allowable code Doppler is approximately (0.4/TNCI), where TNCI represents the non-coherent integration period. Since the code Doppler is directly proportional to the carrier Doppler, the code Doppler limitation imposes a secondary constraint on the allowable carrier frequency error. For the L1 carrier using the P(Y)-code, the carrier frequency error is bounded by this restriction to be approximately (±62/TNCI).
2
(Eq. 3)
In equation 3, fi represents the center frequency for bin i, f represents the frequency of the signal of interest, N is the number of actual data points in the FFT, and TSP is the coherent integration sub-period. In the absence of zeropadding, the frequency spacing of the FFT bins is (1/TCI), where TCI represents the complete coherent integration period. The worst case loss of 3.92 dB then occurs when the difference frequency (fi – f) = [1/(2•TCI)]. This loss is somewhat offset because a signal falling directly in between two frequency bins can be detected with equal probability in either adjacent bin. The effect of any such offset is ignored in this analysis because its effect depends on the signal-to-noise ratio of the signal in question. The loss indicated in Equation 3 can be averaged over the entire span of the FFT to yield an average loss of 1.1 dB.
ACQUISITION PERFORMANCE The acquisition performance was derived from the theory of non-coherently integrated radar pulses [3]. The reference analysis assumes square-law non-coherent combining, but it is assumed that the performance will be essentially the same for the linear envelope combining that the Y-EXPRESS architecture employs. The time period required to scan a time/frequency search space is equal to the number of non-coherent summations, M, times the nominal coherent integration time, TCI. M is a function of the probability of false alarm, PFA, probability of detection, PD, and the expected signal-to-noise ratio. Computation of M is an iterative process. For a given value of M, the detection threshold is adjusted for the desired probability of false alarm, PFA. The probability of detection, PD, is then computed. M is adjusted until the desired PD of > 0.9 is obtained.
This bin-spacing loss can be reduced by zero-padding the FFT computation. The effect of zero-padding is to reduce the frequency spacing of the FFT bins to [1/(2•TCI)] while maintaining the bandwidth of each bin. No real data has been added; the frequency bins introduced by zeropadding are interpolations of data from the FFT with no zero-padding. The additional frequency bins approximate the signal at frequencies half-way between each adjacent pair of bins in the unpadded FFT. With the zero-padded bin spacing described above, the worst case loss is reduced to 0.91 dB and occurs when (fi – f) = [1/(4•TCI)]. The loss averaged over the entire span of the zero-padded FFT is approximately 0.3 dB. In order to minimize unnecessary signal energy losses, zero-padding should always be used for the FFT computation.
For a specified coherent integration time and number of non-coherent summations in the total integration, Table 3 gives the minimum required C/N0 values to achieve a probability of detection of 0.9. Table 3 also states the maximum carrier frequency error that can be searched in a single pass based on the limitations imposed by the coherent integrate and dump and the code Doppler. The probability of false alarm was selected to ensure a probability of 0.999 that at least one tracking channel is available to verify potential detections and dismiss false alarms. Zero-padding is assumed for all FFT computations to minimize bin-spacing losses. Table 3 assumes a total implementation loss of 2.0 dB.
CODE DRIFT LOSS Under low signal-to-noise (or signal-to-interference) ratio conditions, the integration period must be extended to obtain a low probability of false alarm while still maintaining a high probability of detection. This extension, is generally accomplished by non-coherently summing the magnitude of the FFT result over several coherent integration periods. As the non-coherent integration period is extended, frequency errors begin to show up in a new form. Any carrier frequency error implies a proportional PN code rate error referred to as code Doppler. Code Doppler causes the local code phase to shift relative to the code phase of the received signal during the integration. This has the effect of causing the correlation peak to shift during the integration period. When the integration period is short, code Doppler is not a concern because the shift in the correlation peak is not substantial enough to produce a significant loss. The loss depends on the code Doppler of the signal in question and the non-coherent integration period.
Applying the data from Table 3, Figure 5 plots the computed worst case acquisition time assuming an initial time uncertainty of ±1 millisecond and a small carrier frequency error (within the maximum allowable range from Table 3). If carrier frequency error can be sufficiently suppressed, it is advantageous to use as long a coherent integration as possible to reduce the required C/N0. The points in Figure 5 labeled “coherent” represent nominal 5 ms, 10 ms, 20 ms, 40 ms, 80 ms, and 160 ms coherent integrations with no non-coherent summing. Assuming that the navigation data can be stripped off, the coherent integration is presumed to be extendible to 160 ms before non-coherent integration must be used to stretch the total integration period. The curve labeled
358
“160 ms” corresponds to scenarios where a 160 ms coherent integration is coupled with various numbers of non-coherent summations. When the navigation data bit values are unknown, the coherent integration must not exceed the bit duration of 20 ms, and non-coherent summing is necessary to stretch the total integration period. These points are represented by the “20 ms” curve.
SIMULATED ACQUISITION PERFORMANCE A simulation of the Y-EXPRESS receiver was created using the Signal Processing WorkSystem® (SPW™) software package to emulate the communications channel portion of the ASIC. The simulation emulates every mathematical operation that occurs in the ASIC so the simulation outputs exactly match the actual ASIC outputs given identical input signals. To emulate the RF/IF portion of the receiver, a Butterworth filter (N = 3, BT = 1.0) was used to filter the signal prior to the A/D conversion.
Table 3. Minimum Required C/N0 Values and Maximum Allowable Frequency Error Number of Noncoherent Summations
FFT Bins (before zeropadding)
1
Nominal Coherent Integration (TCI + TFFT) 20 ms
160 ms
32
31.5 dB-Hz ±476 Hz
22.1 dB-Hz ±53 Hz
2
32
29.1 dB-Hz ±476 Hz
19.7 dB-Hz ±53 Hz
4
32
26.9 dB-Hz ±476 Hz
17.5 dB-Hz ±53 Hz
8
16
24.5 dB-Hz ±223 Hz
15.3 dB-Hz ±26 Hz
16
8
22.3 dB-Hz ±110 Hz
13.1 dB-Hz ±13 Hz
32
4
20.2 dB-Hz ±55 Hz
11.0 dB-Hz ±6.6 Hz
64
4
18.4 dB-Hz ±51 Hz
9.2 dB-Hz ±6.2 Hz
For the purposes of the simulation, the AGC controller was omitted and the white noise power was adjusted to give the optimal A/D loss for 2-bit conversion [4]. The system included a single P-code signal source and an additive white Gaussian noise source. The P-code signal source was given a constant frequency error (both carrier and code). The P-code signal power was varied to achieve a range of C/N0 values. The ASIC was setup to compensate for all but 450 Hz of the frequency error in order to exercise the Doppler compensation module and also have uncompensated code and carrier Doppler values to be resolved by the FFT. The system was setup for 20 millisecond nominal coherent integration period (TCI + TFFT) with 5 noncoherent sums for a total integration period of 100 milliseconds. A 64-point FFT with 32-point zero-padding was used, leading to a searchable carrier frequency error of approximately ±476 Hz (the carrier frequency error sets the maximum searchable error for this case). For the purposes of simulation, data bits were not multiplied with the PN code. Since the FFT compute time is in excess of 2 milliseconds and the data bit edge relative to the P-code state is known, the bit transition can be forced to occur during the FFT computation and therefore the coherent integration will be unaffected by the transitions.
1000
±1 ms Time Uncertainty Small Frequency Uncertainty PD = 0.9 2.0 dB Implementation Loss Included
The simulation was run in excess of 100 times for each C/N0 value to collect statistics for probability of detection and probability of false alarm. For the specified parameters, a single-tap false alarm probability of approximately 5×10-5 ensures that the hardware capacity for peak detection is rarely exceeded. Table 4 shows the simulated probability of detection and probability of false alarm for selected values of C/N0. For simulation purposes, a known code offset was set between the received and locally generated codes allowing the signal to be acquired during the first pass of the search. Therefore the results presented in Table 4 reflect signal acquisition within the 100 millisecond total integration time of the simulation. This also means that the total time uncertainty searched is 511 half-chips of the code, or ±12.5 µs from the reference point. Acquisition times for larger time uncertainties can be determined by scaling the 100 ms acquisition time by the number of searches required to cover the complete time uncertainty.
100 Coherent
Acquisition Time (s)
160 ms 20 ms
10
1
0.1 8
13
18
23
28
33
38
43
C/No (dB-Hz)
Figure 5. Estimated Direct P(Y)-code Acquisition Time with Small Carrier Frequency Uncertainty (Single Satellite)
359
can be shortened to less than 250 seconds (for the same initial conditions) if the navigation data bit values are known, allowing the receiver to coherently integrate over data bit edges. In the absence of jamming, the P(Y)-code signal can be acquired using a single Y-EXPRESS ASIC in less than one second for the given initial conditions. The acquisition times decrease proportionally as the number of cascaded Y-EXPRESS chips used in the receiver increases.
Table 4. Simulated Y-EXPRESS Acquisition Performance C/N0 (dB-Hz)
PD
PFA
28.4
0.997
5.2×10-5
28.1
0.987
5.1×10-5
27.3
0.953
4.6×10-5
26.4
0.853
5.1×10-5 ACKNOWLEDGMENTS The authors acknowledge Major Anthony Romano, Air Force Research Laboratory, for his support and assistance in the development of the Y-EXPRESS ASIC. The authors would also like to thank the GPS Joint Program Office for their continued support of this technology.
An interpolation of the data from Table 4 shows that a C/N0 of approximately 27 dB-Hz can be acquired with a probability of detection of 0.9 given the outlined configuration. The results can be extended to cover a time uncertainty of ±1 ms by multiplying the 100 millisecond total integration time by 80 (1 ms / 12.5 µs), resulting in an acquisition time of 8 seconds. The result is in close agreement with the “20 ms” curve presented in Figure 5.
REFERENCES [1] “GPS User Equipment Precise Time And Time Interval (PTTI) Interface,” NAVSTAR GPS Phase III Interface Control Document ICD-GPS-060, 02 June 1986.
CURRENT STATUS
[2] “GPS User Equipment Interface Control Document for Instrumentation Port Data Link of the DoD Standard GPS UE Radio Receivers,” ICD-GPS-150, 15 August 1994.
The 240-pin Y-EXPRESS chip has been produced using 0.5 micron technology in both a quad flat pack (QFP) and as a surface mount core suitable for inclusion in a multi-chip module. The ASIC has successfully passed bring-up testing and has been integrated into a functional GPS demonstration receiver (L1 only) for further testing. Power consumption measurements of this test receiver (0.5 micron QFP packaging) have been taken and are shown below in Table 5.
[3] DiFranco, J. V. and Rubin, W. L., Radar Detection, Prentice-Hall, 1968, chapter 9, pp. 291-309. [4] Amoroso, Frank, “Adaptive A/D Converter to Suppress CW Interference in DSPN Spread-Spectrum Communications,” IEEE Transactions on Communications, Volume COM-31, No. 10, October 1983.
Table 5. Measured Y-EXPRESS Power Consumption Power (W) Y-EXPRESS Mode Acquisition and Tracking
2.0
Tracking Only
0.6
Work has begun on a second generation Y-EXPRESS ASIC that will enhance the tracking capability of the chip to 12 channels for all-in-view tracking. This will also enhance the acquisition capability slightly because a higher false alarm rate will be tolerable since twice as many channels will be available to dismiss preliminary signal detections. CONCLUSIONS The Y-EXPRESS ASIC is capable of rapid, direct acquisition of the GPS P(Y)-code using its massively parallel correlator technology coupled with an FFT to expand its single-pass frequency span. Based on performance estimations and simulations, a receiver using a single Y-EXPRESS chip could directly acquire the P(Y)code signal in less than 600 seconds for J/S in excess of 50 dB given initial conditions of ±1 millisecond user time error and ±0.2 ppm frequency error. The acquisition time
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