a degree in electrical engineering from the Polytechnic. School of Rotterdam in 1964. He received the B.SC. and M. SC. degrees in electrical engineering.
IEEE TRANSACTIONS
ON MICROWAVE
THEORY
AND
TECHNIQUES,
1985
MTT-33 , NO. 2, FEBRUARY
VOL.
129
Waiter J. Ghijsen
Peter M.
was born in Geldrop, The Netherlands, on June 24, 1958. He received the M. SC. degree in electrical engineering in 1983 from The Delft University of Technology, Delft, The Netherlands. He is currently working towards his Ph.D. degree in technical sciences at The Delft University of Technology.
van den Berg was born in Rotterdam, The Netherlands, on November 11, 1943. He received a degree in electrical engineering from the Polytechnic School of Rotterdam in 1964. He received the B. SC. and M. SC. degrees in electrical engineering from The Delft University of Technology, The Netherlands, in 1966 and 1968, re-
spectively, and the Ph.D. degree in technicaf sciences from The Delft University of Technology, in 1971. From 1967 to 1968, he was employed as a ‘
* Adrian
Research Engineer by the Dutch Patent Office. From 1968 until the present, he h;s been ~ member of the Scientific Staff of the Electromagnetic Research Group of The Delft University of Technology. During
Computer Calculation GaAs FET Amplifier
Abstract — A simple and efficient sis is presented. dynamic
model
inclnding
FET
is represented
taking
into
account
gate-drain
extraction
voltage
tion
routine
used
Newton-Raphson proposed
using
is rather
method
wave amplifier
the
are compared
using
GaAs
GHz
over wide ranges of bias voltage
T
HE
I. GaAs
tention
high-power
from
its efficiency
sources.
received
much
On
technique.
form,
As
the optimiza-
was replaced
calculated
by the
with the use of the
data taken for a micro-
unit.
Gad
agreement
at 9.5
and input power levels are observed.
continuously
designers Particularly,
device for use in microwave
with
balance
harmonic
INTRODUCTION
circuit
ble or even superior TWT
equations
FET
is receiving
applications.
attractive lators
FET
for are
harmonic
network
effects
procedure
with experimental
a 2SK273
nonlinear
in detail and examples
in its origirraf
Characteristics
anafy-
both
growing
in low-noise
atand
was born
in Cimahi,
In-
of Large-Signal Characteristics
AND TOMASZ
nordinear
response to a single-input
the piecewise
to solve
main
An identification
time-consuming
algorithm.
by its circuit-type
is described
of the arnplifkr
is performed
this teelnique
of GaAs FET amplifier
the device’s
breakdown.
of the model parameters
given. The cafcnlation signal
method
The
MATERKA
(M82)
School in Leeuwarden. He received the M. SC. and Ph.D. degrees in electrical engineering from The Delft University of Technology in 1968 and 1980, respectively. He is a senior staff member of the Electronic Instrumentation Laboratory of the Electncaf Engineering Department. He is currently responsible for research in SAW devices in silicon.
these years, he carried out research and taught classes in the area of wave propagation and scattering problems. During the academic year 1973–1974, he was a Visiting Lecturer in the Department of Mathematics, University of Dnndee, Scotland. During a three-month’s pefiod of 1980–1981, he was a Visiting Scientist at the Institute of Theoretical Physics, Goteborg, Sweden. He was appointed Professor at The Delft University of Technology in 1981.
ANDRZEJ
Venema
donesia, in 1932. He received the B. Sc. electrical engineering degree in 1954 from the Polytechnic
KACPRZAK
Some efforts GaAs tion tions
have been made to simulate
MESFET
performance
of the two-dimensional describing
numerical
the electron
results
the large-signal
based on the numerical nonlinear transport
[1] are very helpful
solu-
differential
equa-
in the channel. to understand
The
device
operation, but long computational time makes this approach impractical in circuit analysis and design programs. Recently,
Madjar
and Rcssenbaum
[2], [3] and Shur and
Eastman [4] developed approximate analytical theories to model the active region under the gate of the microwave GaAs FET. Although one of these theories has been applied to the analysis of a practical microwave FET oscillator [3], both of them are of limited use in circuit design practice because they utilize the FET physical parameters which
are
scarcely
available
to
the
circuit
designers.
the power FET is an
Willing,
amplifiers
device with a quasi-static approach by measuring small-signal scattering parameters at a number of operating points
and power performance
to the other commercial
and oscilcompara-
solid-state
the other
hand,
the power
less attention
from
researchers
FET than
or has its
low-noise counterpart and, still, there is a need for data on device RF characterization at large-signal drive levels. Manuscript received November 10, 1983; revised September 17, The authors are with the Technicaf University of Lodi, Electronics, Gdanska Street 176, 90-924 Lodi, Poland.
0018 -9480/85
Institute
1984. of
Rauscher,
to formulate
and de Santis [5] characterized
an equivalent
circuit,
an actual
some of whose elements
are bias-dependent. They use polynomial forms to approximate these dependence and a time-domain analysis program to calculate the large-signal device characteristics. The results obtained compare favorably with the experimentally determined characteristics, but the complexity of the equivalent circuit the model parameters
/0002-0129$01
.00 01985
IEEE
makes the identification rather laborious. Later,
technique Rauscher
of [6]
130
IEEE
proposed ity,
an FET macromodel
making
mum
it possible
large-signal
oscillator
with a “lumped”
to analytically
operating
circuit.
calculated
THEORY
AND
TECHNIQUES,
VOL.
MTT-33, NO. 2, FEBRUARY 1985
r..
the opti-
of the FET
of this approach
corresponds
ON MICROWAVE
nonlinear-
determine
conditions
A drawback
optimum
TRANSACTIONS
,D
in an
is that the
to a given combination
of
bias voltages. To achieve the circuit optimization over the entire range of the gate and drain voltages, one should perform a large number of measurements at elevated drive levels. An
alternative
zation
approach
of the microwave
to the large-signal
device properties
are governed
dc characteristics—an
that
primarily
assumption
dynamic
has been verified
model
proposed
in
this paper. The
general
analysis
input
impedances
power,
FET
procedure
amplifier
for defining
bias conditions,
that correspond
and
the
terminating
to the maximum
efficiency
or
power at a given frequency. This can be facilitated with the use of a computer and an appropriate
large-signal find
of the microwave
is to derive a systematic
optimum output greatly
problem
analysis program.
a periodic
work input
steady-state
The computational response
task is to
of a nonlinear
net-
(i.e., the FET and its embedding circuit) to a singleharmonic signal. The general-purpose time-domain
analysis
programs
are not
suitable
they are very time-consuming
for
this
when applied
aim because to microwave
appropriately
formulated work.
II.
It was assumed,
in
analysis
applied
by
oscillator
the most
Another
cially
changes in the drain–source
method,
Tajima
design
MESFET time-domain
cannot
analysis
be easily
programs
of the simple iteration
et al. [7] to the FET
but sometimes
at high-input
device,
conduc[10].
type, was
amplifier
and
it fails to converge,
espe-
levels [11]. It follows
analyzed by these methods is decomposed into a minimum number of linear and nonlinear subnetworks and only frequency domain solutions of the linear subnetworks are required. In the original work of Nakhla and Vlach [12], an optimization procedure was used to solve the networks equations; however, it appears to be time-consuming and exhibits convergence problems at the high number of variables in the optimization process [13]. Taking the above considerations nique together
into account, the harmonic with the Newton–Raphson
balance techmethod and
[14] are used
DYNAMIC GAAS MESFET MODEL
based on experimental
study
of arbi-
the equivalent the diode Df, gate-to-channel
3)
by voltage varithe drain current source id controlled ables Vg and Vd, D,, which represents the effect of the the diode
4)
gate–drain
gate-to-source
capacitance
ele-
1)
which represents junction,
breakdown.
the best
average
fit
are linear
their usual physical
gate-to-source
Cg, =cgo
obtained appear
in
parameters
are not
breakdown of this model
interpretation
capacitance
[16].
is given by
– 0.5
() l–g
,
for Vg0.8
with
circuit.
trarily selected transistors, that the main nonlinear ments of the model (see Fig. 1) are as follows [15]:
a straight
current
equivalent
network
LARGE-SIGNAL
age and the relevant tion
FET large-signal
in the present
circuits which typically consist of linear elements with a relatively small number of nonlinear ones. Additional difficulty arises from the fact that the time-delay effects as, e.g., the time difference between the changes in gate volt-
simulated
1.
by the transistor
which
the gate–drain region which is believed to have an impact on the FET gain saturation characteristics [9]. In order to take full advantage of the power capabilities of GaAs MESFET’S, the breakdown effect is taken into account in large-signal
Fig.
the large-signal
at least up to 10 GHz. The Tajima model does not represent, however, the voltage-breakdown phenomenon [8] in
the circuit-type
s~s
GaAs FET was used in the work
et al. [7]. They postulate
of Tajima
I
characteri-
with the model parameters 1, and a,. The voltage-controlled current source id is described the formulas
(2)
by
[17]
i~=I~,J
( ‘:)’ta%%d l—~
(3)
Vp = V*O + yv~
(4)
where Id,,, VPO, a, and y are the model parameters. In order to take into account the time delay between drain current and gate voltage, the instantaneous current id(t) is calculated from (3) with Ug = Ug( t – ~) and Ud = Vd (t ), where r is the model
parameter.
MATERKA
AND
KACPRZAK:
The gate–drain
breakdown
from
simulation
results
of
and
from
[18]
measured
SIGNAL
FET AMPLIFIER
CHARACTERISTICS
two-dimensional
dc breakdown of various
l.,
computer
characteristics
types, e.g., 2N6680
in the diode D, is given by
The current
&d
a,.
Lp G+
was
(5)
i,= I,, [exp (a.,u~g)–l] where
131
by means
of such an approach
the
for the transistors
and 2SK273.
GilAs
effect is modeled
D,. The validity
of the diode deduced
LARGE
are the model
parameters.
It should
be
any emphasized that the diode D, does not represent forward-biased p-n or Schottky-barrier junction connected between
the gate and drain
terminals.
in the diode
D, approximates
this
the parameters
reason,
different
voltages
negative
calculated
gate–source
from
III.
For
parameters
for small and moderate
(e.g., up to 5 V for low-power voltages,
(5) is negligibly
creases considerably
the
gate
small.
at larger gate–drain
FET’s)
current
However,
as
it in-
voltages.
DETERMINATION OF THE MODEL PARAMETERS model
is characterized
Some of them are calculated while
current.
in (5) are quite
in their values from the corresponding
gate-drain
The
a,,
others are fitted
The parasitic
by a set of 24 parameters. from simple dc measurements,
to dc &d
can be determined ments. R, is found the gate-source
by dc current by passing
junction
age at the floating
resistances
drain
R, and R~
and voltage
a forward
and measuring
measure-
current
1~ into
the resulting
volt-
with respect to the source [19]
AV~~ and A lG are the incremental
source voltage
R,
tance
and gate current,
depends
slightly
average value obtained used. Similarly, the gate–drain floating
on the
gate current
junction
R ~ is found and measuring
1~, the
by forward
can be biasing
the voltage
at the
1– V characteristic
from
of the gate-source
the mea-
real Schottky
drain-source
current
increases
(7)
where R is the series diode resistance and I,, a, are the i.e., for low parameters of (2). When IGR 30 mW) the forward
current
dominates
while for larger powers
conduction
is prevailing.
Newton–Raphson
and experiment
with
the harmonic
described
mV, depending
for V&=
power level. It takes about
min of the HP 9825A computer and ZLL that value of Pi. In
Fig.
match
characteristics obtained matching the transistor calculations
time to find values of Z~~
the simulated
5 are shown
10
amplifier
at a given
power
for the impedances at every given input
were performed
saturation
Z~~ and ZLL power Pi. The
for V~~ = 4 V and two values
of gate-source voltage: L&= – 0.75 V and V~~ = – 1.25 V. For input power P,> 5 mW, the decrease in the transistor power gain is accompanied by a dc gate current flow, as it is seen in Fig. 5. This current consists of two components.
power
is observed for the FET bias conditions
In Fig. 6 are shown the power
saturation
characteristics
– 0.75 V and three values of drain-source
voltage
V~~ = 3, V~~ = 4, and V~~ = 5 V. Some discrepancies tween
as
previously.
the calculated
and measured
V~~ = 5 V. These are attributed the calculated
In the
up to 40 mW, the dc gate current is negative. Also shown in Fig. 5 are the results of measurements obtained using a load-pull technique [23]. Good agreement between theory
balance method [14] req&es 4-10 iterations to calculate the amplifier voltage response with an error less than 1 on the input
of
– 0.75 V and
case of V~~ = – 1.25 V, in the whole range of input
combined
effect
conduction
the fundamental harmonic were used. However, this simplification does not generate a significant error, at least when the large-signal characteristics of an FET tuned amplifier are concerned, as can be seen later. The algorithm
char-
data are observed
to the simplified
befor
descrip-
tion of the breakdown phenomena in the FET model. Particularly, the dynamics of the breakdown mechanisms [24] must be included in the GaAs FET model. The mathematical model (5) is of an instantaneous nature, but in general the breakdown effects may have time delays associated with them. For every given value terminating
impedances
of P, there exists a set of FET that
corresponds
to a maximum
134
IEEE
TRANSACTIONS
ON MICROWAVE
THEORY
modification
AND
TECHNIQUES,
considerably
VOL.
MTT-33, NO. 2,
shortens
the
1985
FEBRUARY
calculation
time
and enables us to perform an analysis and design process on the desk computer. Since nonlinear device operations as either power amplifiers and oscillators is quite similar, the FET characterization technique developed above for amplifiers can be readily design needs as well.
carried
over to meet
oscillator
References [1]
[2]
[3]
[4]
[5]
Fig.
7.
Measured
(O O 0)
and predicted
( —)
contours
output power on the load impedance plane, ZL/50 V~~ = 4 V, VG~ = – 0.75 V, and 6 =20 mW.
of constant
Q, ~ = 9.5 GHz,
[6]
[7]
output power. Putting K in (10) less than this maximum value, one can calculate constant output power contours on the terminating cate
how
function
the
impedances output
power
of the load
These contours
the
FET
presented
varies
amp~fier
and oscillator of constant
circuits. output
Measured
power
as the
are shown in Fig. 7, for Pi= 20 mW,
VI. reasonably
dynamic
for The
CONCLUSIONS
simple
circuit-type
appropriate proposed.
and fairly
model
accurate
for a GaAs
use in circuit identification
of the model,
in which
[11] [12]
[13]
[14]
large-signal
MESFET
that is
[15]
design programs has been procedure of the model
parameters is based on the experimental characterization of the FET dc current-voltage relationship and the frequency dependent small-signal S-parameters. The computer analysis of a large-signal X-band FET amplifier and the measurements of its performance have confirmed the validity
[10]
amplifier
l’~~ = 4 V, V~~ = 0.75 V, and the impedance Z~ (Fig. 4(a)) matching the amplifier’s input. Considering the limited accuracy of impedance measurements at microwave frequencies, the agreement is very good.
The
[9]
practical
and predicted
of the FET
[8]
indi-
to it (see Fig.
is very useful in designing
contours
consideration
of
impedance
4(a)). This information
under
planes.
only
four
elements
[16]
[17]
[18]
were
as~umed to be nonlinear,, i.e., Cg,, D,, Df, and id (see Fig. 1). These elements predominantly represent the power gain
[19]
saturation of the transistor. The model has been used to calculate the large-signal FET characteristics in the amplifier circuit with the use of
[20]
a digital computer. The amplifier analysis method is based on the piecewise harmonic balance technique [12] with the originally recommended optimization procedure replaced by the Newton-Raphson
computational
scheme [14]. This
[21]
[22]
K. Yamaguchi, S. Asai, and K. Kodera, “ Two-dimensionaf numericaf aualvsis of stabifitv criteria of GaAs FET’s.” IEEE Trans. Electron ‘Devices, vol. ED-23, pp. 1283-1290, Dec. 1976. A. Madjar and F. J. Rosenbaum, “A potentiaf ac large-signaf model for GRAS microwave MESFET’S,” in 1979 Int. Microwave Symp. Dig., (Orlando, FL), May 1979, pp. 399-401. A. Madjar, “Analysis of a microwave FET oscillator using an efficient computer model for the device,” IEEE Trans. Microwave Theory Tech., vol. MTT-30; pp. 915-917, June 1982. M. S. Shur and L. F. Eastman, “Current-voltage characteristics, small-signal parameters, and switching times of GaAs FET’s,” IEEE Trans. Electron Devices, vol. ED-25, pp. 601-611, June 1978. H. A. Willing, C. Rauscher, and P. de Santis, “A technique for predicting large-signaf performance of a GaAs MESFETJ’ IEEE pp. 1017-1023, Dec. Trans. Microwaue Theory Tech., vol. M’IT-26,
1978. C. Rauscher,’
