CSE370 - XIX - Computer Organization. 1 .... Control state diagram (for each
diagram). ❑ reset ... separate data and instruction memory (Harvard architecture).
▫.
Autumn 2003. CSE370 - XI - Computer Organization. 1. Computer organization.
▫. Computer design – an application of digital logic design procedures. ▫.
Computer organization. ▫. Computer design – an application of digital logic
design procedures. ▫. Computer = processing unit + memory system. ▫.
Processing ...
Explain how the performance of a computer can be measured? What are the ... Represent the number 81234561 in 32-bit Big-
Adapted from Computer Organization and Design, Patterson & Hennessy, UCB.
ECE232: Hardware Organization and Design. Part 2: Datapath Design – Binary ...
Adapted from Computer Organization and Design, Patterson & Hennessy, UCB.
ECE232: Hardware Organization and Design. Part 5: MIPS Instructions I.
Structure of a computer. ▫ Block diagram view. CSE370 - Computer Organization
. 2 instruction unit œ instruction fetch and interpretation FSM execution unit.
David A. Patterson & John L. Hennessy,. Morgan Kaufmann, 1997 http://www.
mkp.com/cod2e.htm. Advanced Text: Computer Architecture : A Quantitative ...
Jan 27, 2014 ... It uses the top-down, layered, approach to design and also to improve .....
confusing for beginners of computer design : hardware vs. software, ...
They vary in number and purpose on different machines. • Buses –
communication pathways connecting different devices/components. 8086 Block
Diagram. CS.
Computer Organization. Memory. CPU. Input. Devices. Output. Devices. CPU.
Brains of the computer. ▫ Arithmetic calculations are performed using the.
Appendix B: Projects for Teaching Computer Organization and Architecture.
References. ... CPU-IO: Data may be transferred between CPU and an I/O
module.
W. Stallings, "Computer Organization and Architecture - Designing for.
Performance" ... Problem Statement ... essential to both their design and their
description.
Aug 19, 2012 ... Short Course Outline. Hardware Description using Verilog. A commonly used
language for designing digital hardware. Computer Arithmetic.
is often made between Computer Organization and Architecture, it is difficult to
give ..... another two signal lines to distinguish between four arithmatic operations
.
•(A stored program computer behaves as different machines by loading different
programs, i.e., sequences of instructions.) 5 Computer Organization. Slides for ...
The essentials of computer organization and architecture / Linda Null, Julia Lobur
.... that we feel is useful—if not essential—to your continuing computer science.
CPU organization ... Chapter 2 is a survey of the basics of computer systems:
CPU architecture and .... Diagram shows how this might work. So, if it takes 2 ns ...
Lesson 02: Functional units and components in a computer organization- Part 1:
Processor. Chapter 02: Computer Organization ...
Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson
Education, Inc. All rights reserved. 0-13-148521-0. Computer Systems ...
Fourth Semester B.E Degree Examination. (Common to CS and IS). Model Question Paper. 06CS46 Computer Organization. Note:
2.4 Memory â A Place to Store Data (and Other Things) . . . . . . . . . . . . . . . . . .... 7.2.3 The Additional Assembly Language Generated by the Compiler . ...... The user is prompted to enter an integer in decimal, and the user's response is r
Autumn 2006. CSE370 - X - Computer Organization. 3. LD asserted during a lo-to
-hi clock transition loads new data into FFs. OE asserted causes FF state to be.
Computer organization
Computer design – an application of digital logic design procedures Computer = processing unit + memory system Processing unit = control + datapath Control = finite state machine
inputs = machine instruction, datapath conditions outputs = register transfer control signals, ALU operation codes instruction interpretation = instruction fetch, decode, execute
Datapath = functional units + registers
functional units = ALU, multipliers, dividers, etc. registers = program counter, shifters, storage registers
Autumn 2006
1
CSE370 - X - Computer Organization
Structure of a computer
Block diagram view address Processor central processing unit (CPU)
Control
read/write data
control signals
Memory System
Data Path
data conditions
instruction unit – instruction fetch and interpretation FSM Autumn 2006
execution unit – functional units and registers CSE370 - X - Computer Organization
2
Registers
Selectively loaded – EN or LD input Output enable – OE input Multiple registers – group 4 or 8 in parallel
LD
OE
D7 D6 D5 D4 D3 D2 D1 D0
Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0
CLK
Autumn 2006
OE asserted causes FF state to be connected to output pins; otherwise they are left unconnected (high impedance) LD asserted during a lo-to-hi clock transition loads new data into FFs
3
CSE370 - X - Computer Organization
Register transfer
Point-to-point connection
MUX
MUX
MUX
MUX
R0
R1
R2
R3
R0
R1
R2
R3
R2
R3
Common input from multiplexer
dedicated wires muxes on inputs of each register
load enables for each register control signals for multiplexer
MUX
Common bus with output enables
output enables and load enables for each register
R0
R1 BUS
Autumn 2006
CSE370 - X - Computer Organization
4
Register files
Collections of registers in one package
two-dimensional array of FFs address used as index to a particular word can have separate read and write addresses so can do both at same time
4 by 4 register file
16 D-FFs organized as four words of four bits each write-enable (load) read-enable (output enable)
RE RB RA Q3 Q2 Q1 Q0
WE WB WA D3 D2 D1 D0 Autumn 2006
5
CSE370 - X - Computer Organization
Memories
Larger collections of storage elements
implemented not as FFs but as much more efficient latches high-density memories use 1 to 5 switches (transitors) per memory bit
Static RAM – 1024 words each 4 bits wide
once written, memory holds forever (not true for denser dynamic RAM) address lines to select word (10 lines for 1024 words) read enable
same as output enable often called chip select permits connection of many chips into larger array
write enable (same as load enable) bi-directional data lines
Autumn 2006
output when reading, input when writing
CSE370 - X - Computer Organization
RD
WR A9 A8 A7 A6 A5 A4 A3 A2 A2 A1 A0
IO3 IO2 IO1 IO0
6
Instruction sequencing
Example – an instruction to add the contents of two registers (Rx and Ry) and place result in a third register (Rz) Step 1: get the ADD instruction from memory into an instruction register Step 2: decode instruction
instruction in IR has the code of an ADD instruction register indices used to generate output enables for registers Rx and Ry register index used to generate load signal for register Rz
Step 3: execute instruction
enable Rx and Ry output and direct to ALU setup ALU to perform ADD operation direct result to Rz so that it can be loaded into register
conditional/unconditional branches in program flow subroutine call and return
Autumn 2006
CSE370 - X - Computer Organization
8
Elements of the control unit (aka instruction unit)
Standard FSM elements
Plus additional "control" registers
state register next-state logic output logic (datapath/control signalling) Moore or synchronous Mealy machine to avoid loops unbroken by FF instruction register (IR) program counter (PC)
Inputs/outputs
outputs control elements of data path inputs from data path used to alter flow of program (test if zero)
Autumn 2006
9
CSE370 - X - Computer Organization
Instruction execution
reset fetch instruction decode execute
Init
Instructions partitioned into three classes
Reset
Control state diagram (for each diagram)
branch load/store register-to-register
Different sequence through diagram for each instruction type
Autumn 2006
Branch
Branch Branch Taken Not Taken
CSE370 - X - Computer Organization
Initialize Machine
Fetch Instr.
Load/ Store
XEQ Instr.
Registerto-Register
Incr. PC 10
Data path (hierarchy)
Cin
Arithmetic circuits constructed in hierarchical and modular fashion
Ain Bin
each bit in datapath is functionally identical 4-bit, 8-bit, 16-bit, 32-bit datapaths
FA Cout
Ain
HA
Bin
HA
Cin
Autumn 2006
Sum
Sum Cout
11
CSE370 - X - Computer Organization
Data path (ALU)
ALU block diagram
input: data and operation to perform output: result of operation and status information
A
B 32
32 Operation 32 N
Autumn 2006
S
Z
CSE370 - X - Computer Organization
12
Data path (ALU + registers)
Accumulator
One-address instructions
special register one of the inputs to ALU output of ALU stored back in accumulator operation and address of one operand other operand and destination is accumulator register AC
