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IEEE ELECTRON DEVICE LETTERS, VOL. 33, NO. 4, APRIL 2012
Defect Loss: A New Concept for Reliability of MOSFETs M. Duan, J. F. Zhang, Z. Ji, W. Zhang, B. Kaczer, S. De Gendt, and G. Groeseneken
Abstract—Defect generation limits device lifetime and enhances its variability. Previous works mainly addressed the generation kinetics and process. The current understanding is that the microstructure responsible for defect can exist either as a precursor or as a charged defect. A precursor is converted into a defect during stresses, but a defect can return to its precursor status through recovery and/or anneal. This letter will introduce a new concept: defect loss. A lost defect will not return to the precursor status. When stressed again, the lost defect will not reappear. It is found that the defect loss is thermally activated and a reduction of the “permanent component” makes substantial contribution to the loss. This letter opens the way for improving device lifetime through maximizing defect loss. Index Terms—Charges, defects, degradation, hole traps, instability, interface states, lifetime, negative bias temperature instability, reliability.
I. I NTRODUCTION
A
S DEVICES are downscaled, defect generation not only shifts the average parameters such as threshold voltage Vth [1]–[4] but also increases their variability [5], [6] and, in turn, the difficulty in circuit design. This makes its suppression a pressing task. Previous works [1]–[8] were focused on defect generation process and kinetics. The current understanding is that the microstructure responsible for the defect can exist either as a precursor or as an electrically active defect. The precursors are transformed and charged during stresses, shifting Vth, as shown in Fig. 1. When the stress bias is removed and temperature is kept at the same level, some defects are neutralized and these are called “recovery,” whereas other defects will not neutralize and are often referred to as “permanent” [9], [10]. It should be pointed out that the term “permanent” has a relative nature and could contain some slowly recovering defects [11]. “Permanent” does not mean that it cannot be neutralized under any circumstances. By raising temperature, permanent defects can be neutralized and return to their precursors [12].
Manuscript received December 21, 2011; revised January 9, 2012; accepted January 12, 2012. Date of publication February 27, 2012; date of current version March 23, 2012. This work was supported by the Engineering and Physical Science Research Council of the U.K. under Grant EP/I012966/1. The review of this letter was arranged by Editor A. Ortiz-Conde. M. Duan, J. F. Zhang, Z. Ji, and W. Zhang are with the School of Engineering, Liverpool John Moores University, Liverpool L3 3AF, U.K. (e-mail:
[email protected]). B. Kaczer is with IMEC, 3001 Leuven, Belgium. S. De Gendt and G. Groeseneken are with IMEC, 3001 Leuven, Belgium, and also with KU Leuven, 3000 Leuven, Belgium. Color versions of one or more of the figures in this letter are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/LED.2012.2185033
Fig. 1. Typical stress–recovery–stress sequence at 125 ◦ C. The stress was at Vg = −2.5 V and a body bias of Vb = 2.8 V. For recovery, Vg = 0 V.
It was reported that some recoverable defects can be converted into permanent defects [13]. Some recoverable defects can disappear for some time and then reappear [14], [15]. The current understanding is that, in terms of reliability, the best that one can achieve is to make a stressed device as good as fresh [12]. When the device is stressed again, however, the defects are recharged/regenerated. The central objective of this letter is to introduce a new concept: defect loss. It will be shown that a lost defect will not return to its original precursor status and will not reappear during the subsequent stress. The loss is thermally driven and is substantially from permanent components. This results in lower degradation and opens the way for improving device lifetime. II. D EVICES AND E XPERIMENTS The pMOSFETs have a 2- or 2.3-nm plasma nitrided SiON layer and a p+ polygate. The typical channel length and width are 0.13 and 10 μm, respectively. As shown in Fig. 1, Vth was periodically monitored during both stress and recovery. Vth was extracted by extrapolating a quasi-dc Id–Vg from the maximum transconductance location [16]. The Vth measurement took 1 s, and the recovery component is effectively measured between this initial measuring delay of 1 s and a typical final recovery time of 100 s. Although this substantially underestimates the recoverable components [16]–[18], it is used here because the defect loss is dominated by the permanent components, as to be shown in Section III. The measurement was always at the same temperature in a test. III. R ESULTS AND D ISCUSSIONS Fig. 1 shows that the neutralized defects during recovery were recharged so that ΔVth at the end of second stress is not
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DUAN et al.: DEFECT LOSS: A NEW CONCEPT FOR RELIABILITY OF MOSFETs
Fig. 2. After stress (Vg = −3.5 V and Vb = 4.5 V) and recovery, a 350 ◦ C anneal with gate floating was used to enhance defect loss. The thermally accelerated loss can be clearly observed. R0 and P0 represent the recoverable and permanent components before the 350 ◦ C anneal, respectively, and R1 and P1 represent the recoverable and permanent components after the 350 ◦ C anneal, respectively.
Fig. 3. Comparison of defect losses with and without prestress anneal. One device (symbol “Δ”) was annealed at 400 ◦ C for 30 min before stresses, whereas the other was not. The stress was at Vg = −3.25 V and Vb = 4.5 V. The prestress anneal has little impact on defect losses.
lower than that at the end of first stress. As a result, defect losses are negligible under typical test conditions used in early works, explaining why defect losses were not reported. To show defect losses, we enhanced it by raising the temperature to 350 ◦ C after a recovery period in Fig. 2. ΔVth did not fully return to zero here, and there is a residual degradation at the end of anneal, which gave the high starting value for the subsequent stress. In spite of this higher starting value, Fig. 2 shows that ΔVth after the 350 ◦ C exposure could not reach the level before the exposure. This is caused by defect loss. The typical loss percentage is 20%–25% at the higher end of loss range (5%–25%) observable from the results of early work [12]. Figs. 1 and 2 show that defect loss is a thermally activated process. One question is whether it also occurs by annealing a fresh device. In Fig. 3, one fresh device was annealed at 400 ◦ C for 30 min before the stress, whereas the other was not. Since the difference in their degradation during the first stress is negligible, annealing a fresh device will not result in defect losses. Moreover, in Fig. 3, the two devices were also annealed after stress and there is little difference in their defect losses. Defects must be activated by electrical stresses before losses. To demonstrate that defect losses can also occur at a lower temperature, two devices were used in Fig. 4, i.e., one was continuously stressed and the other cycled the stress–recovery– anneal (250 ◦ C) sequence illustrated in Fig. 2 ten times. To facilitate the comparison of two devices, the recovery and anneal periods were removed in Fig. 4(a). After the last anneal, a long
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stress was carried out. Parallel lowering of ΔVth after 250 ◦ C cycling confirms that the lost defects were not recreatable. In Fig. 4(b), the time was reset to zero at the start of the last long stress in Fig. 4(a). Although defect losses cannot be observed at short restress time due to the effect of residual degradation at the end of anneal, it becomes clear at long restress time. The defect loss is observed here by comparing the degradation of two devices, and the contribution of sample variation to the loss is found to be insignificant. Results similar to Fig. 4(a) were reported by early work when applying a positive Vg during recovery [19]. An application of Vg > 0 enhances electron tunneling and neutralization of positive charges in dielectric. It, however, contributes little to losses since it does not give the required thermal energy for losses. Degradation has two components, namely, recoverable and permanent, as shown in Fig. 1. To investigate their relative contribution to the thermally driven loss, we measured them before the loss, labeled as R0 and P0 in Fig. 2, and after the loss (R1 and P1). (P0-P1)/Loss = 87% and (R0-R1)/Loss = 13% so that the permanent component makes substantial contribution to the loss. It should be pointed out that the recoverable component was measured between 1 and 100 s of recovery time here, and further investigation is needed to find how its contribution to loss depends on the recovery time used. We now discuss the defects responsible for the recoverable and permanent components. Defects can be created in the oxide and also at the oxide/Si interface. When measured by standard charge pumping, interface states are mainly “permanent” [18], [20]. In addition, it has been reported that antineutralization positive charges (ANPCs) can be created in the oxide [20]–[25]. ANPCs have energy levels above the silicon conduction band edge, i.e., Ec, making them difficult to neutralize and contributing to the “permanent” components [23]–[25]. As a result, the thermally accelerated loss is dominated by ANPCs and created interface states. On the recoverable components, asgrown hole traps have energy levels below the top edge of the silicon valence band [20]–[25], allowing them to be readily neutralized and contributing to the “recoverable” component. In addition, cyclic positive charges (CPCs) have energy levels near Ec and are also recoverable at the timescale used in Figs. 1–3 [23]–[25]. These two types of defects are not the main sources of defect losses. The physical mechanism for the loss is not known. One may speculate that, after a defect is generated, thermal energy during the subsequent anneal can change its microstructure so that it cannot be recharged. Finally, it should be pointed out that, although a substrate bias was applied in Figs. 1–4 to accelerate degradation, Fig. 5 shows that losses also occur without applying a substrate bias. IV. C ONCLUSION This letter has introduced a new concept: defect loss. The loss is thermally enhanced, substantially from “permanent” components, and different from the well-known recovery. The loss occurs only when the defects have been activated by stress. The loss leads to lower degradation and opens the way for improving device lifetime.
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Fig. 4. (a) At the end of cycling stress–recovery–anneal, a long stress was carried out. The stress was at Vg = −2.8 V and Vb = 4 V. When compared with a continuous stress, ΔVth was lowered in parallel and the gap does not close. The time is the accumulative stress time, and the recovery/anneal period is removed here. The two lines are parallel. ΔVth for these two devices were normalized at a stress time of 100 s. (b) The continuous stress and the last long stress in (a) are replotted, and the stress time was reset to zero at the point “Residue” marked in (a) for the last stress. The loss cannot be observed at short stress time due to the residual degradation, but it becomes clear at longer stress time.
Fig. 5. Defect losses when stressing a 2.3-nm SiON layer without applying a substrate bias. The oxide field is 9.6 and 11 MV/cm for Vg = −3 and − 3.5 V, respectively.
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