Defining the Optimal Architecture for Multi-Standard

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Defining the Optimal Architecture for Multi-Standard Radio Receivers Embedding Analog Signal Conditioning Silvian Spiridon1,2, Claudius Dan1 and Mircea Bodea1 1

“POLITEHNICA” University of Bucharest, Romania 2 Now with Broadcom, Bunnik, The Netherlands e-mail: [email protected], [email protected], [email protected] Abstract—This paper focuses on finding the optimal architecture for a multi-standard radio receiver embedding analog signal conditioning compatible with the major commercial wireless standards. By developing a standard independent methodology, the paper addresses systematically the large amount of information comprised in the envisaged standards. Based on the systematic approach, the multistandard receiver main electrical requirements are defined and their values determined. The presented results constitute the starting point in building a multi-standard wireless receiver. Keywords-software specifications.

I.

defined

radio;

receiver

electrical

INTRODUCTION

At the beginning of the mobile Internet age, it becomes clear there is a strong need of mobile equipment able to maximize its wireless connectivity. There are several reasons that make extremely attractive the usage of multi-standard radio transceivers to enable the wireless interoperation of such mobile equipment, [1,2]. Firstly, a multi-standard solution is efficient as only one design is required to handle the mobile device wireless communication. Thus, the number of different dedicated ICs or IP blocks inside a large SoC is reduced. This simplifies the overall communication platform integration. Secondly, since only one design is required to cover for all the targeted wireless standards all cost related to the IP development and testing are minimized. The ideal multi-standard receiver was proposed by Mitola in [3]. The Software Defined Radio Receiver (SDRR) shown in Fig. 1.a is the optimal choice from system level perspective, as it comprises only an ADC. In reality, due to practical implementation constrains, a multi-standard receiver requires a signal conditioning block in between the antenna and the ADC. The SDRR concept shown in Fig. 1.b relaxes the ADC specifications by ensuring additional selectivity and amplification for the wanted signal. First, the paper focuses on finding the optimal architecture for the SDRR signal conditioning block that enables its monolithic integration.

ADC

Signal Conditioning

a.

ADC

b.

Figure 1. a. Mitola SDRR Concept, b. SDRR embeding signal conditioning.

Based on a detailed overview of the key receiver architectures, Section II introduces the optimal architecture for a SDRR that targets compatibility to the major commercial wireless standards listed in Table I. Second, the paper pursues the identification of the SDRR key electrical requirements and their values. Based on a systematic approach, the paper introduces a standard independent methodology for evaluating the SDRR performance. Section III defines the SDRR receiver sensitivity, NF and gain requirements, while Section IV analyses the blocker and interferers impact on the SDRR linearity requirements. Section V concludes the paper. II.

INTRODUCING THE OPTIMAL ARCHITECUTRE OF THE SIGNAL CONDITIONING BLOCK

This Section covers one of the paper’s goals that is to find the optimal architecture for the SDRR signal conditioning block enabling its monolithic integration. In Section II.A, the key receiver architectures are analyzed, while Section II.B determines the quadrature direct conversion topology suits best the envisaged purpose. Section II.C overviews the architectural changes that make the homodyne receivers ready for monolithical integration. The presented solutions are realized without introducing particular analog tricks to satisfy the needs of only one of the standards, as the SDRR must represent “universal receivers”, and not be turned into a “multistandard ASICs”. A. Overview of Key Receiver Architectures First of all, one of the most popular receiver architectures is the heterodyne architecture. It was developed in 1918 by Edwin Armstrong as a viable alternative to the regenerative receiver with respect to the technical issues of vacuum tubes implementation, [4].

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TABLE I.

TARGETED MAJOR COMMERCIAL WIRELESS STANDARDS KEY SPECIFICATIONS

Frequency Plan [MHz]

Wireless Standard

GMSK

9

0.2

–102

–109

QPSK

−18 (@ 12.2kbps)

3.84 / 5

–117

–123

2402 ÷ 2480

GFSK

16

1

–70

–94

1880 ÷ 1980, 2010 ÷ 2035

GFSK

13

1.2 / 1.736

–83

–97

DBPSK / DQPSK

−4 / −2

–80

–104 / –102

Downlink

Uplink

GSM 850

869 ÷ 894.8

824 … 849.8

GSM 900

935 ÷ 960

890 … 915

DCS 1800

1805 ÷ 1880

1710 … 1785

PCS 1900

1930 ÷ 1990

1850 … 1910

I

2110 ÷ 2170

1920 ÷ 1980

II

1930 ÷ 1990

1850 ÷ 1910

III

1805 ÷ 1880

1710 ÷ 1785

Bluetooth, [7] DECT, [8] WLAN IEEE 802.11b (DSSS), [9]

1 / 2 Mbit/s 2400 ÷ 2485

14 / 5

5.5 / 11Mbit/s 6 / 9 Mbit/s

WLAN IEEE 802.11a,g (OFDM), [9]

12 / 18 Mbit/s

5150 ÷ 5350 & 5725 ÷ 5825 (a)

CCK

9 / 11

–76

–91 / –89

BPSK

4/5

–82 / –81

–95 / –94

QPSK

7/9

–79 / –77

–92 / –90

16.6 / 20 24 / 36 Mbit/s

2400 ÷ 2485 (g)

48 / 54 Mbit/s

The basic block schematic of this concept is depicted in Fig. 2. The original superheterodyne uses only one downconverter mixer (i. e., single conversion superheterodyne), and mixes the Radio Frequency, RF, input signal with the Local Oscillator, LO, signal. The resulting signal frequency is mixed down by the mixer (i. e., MIX in Fig. 2), to an Intermediate Frequency, IF, equal to the difference between the RF carrier and LO signal frequencies. Intrinsically the mixing process will render at the mixer output also the sum frequency component. For most applications this component represents an unwanted signal and is filtered by the band pass filter (i. e., BPF in Fig. 2) following the mixer and/or in the mixer output stage. The major issue of the heterodyne topology is the image frequency rejection. The issue is two symmetrical signals with frequencies spaced apart by twice the IF frequency are downconverted by LO mixing to the same IF frequency, as shown in Fig. 3. IRF

LNA

(off-chip)

(optional)

Sensitivity @ NFRX = 3 dB [dBm]

SNR0 [dB]

GSM, [5]

UMTS, [6]

RF Signal BW / Specified Channel Spacing Sensitivity [MHz] [dBm]

Modulation Type

MIX

BPF (off-chip)

RF

IF

LO Figure 2. Single Conversion Superheterodyne Receiver Block Schematic.

16QAM

12 / 16

–74 / –70

–87 / –83

64QAM

20 / 21

–66 / –65

–79 / –78

Generally, only one of the two sideband signals conveys useful information, while the other represents an unwanted image signal. Thus, for superheterodyne receivers image signal rejection is critical for a proper signal demodulation. The superheterodyne architecture solves the issue by filtering the image signal before it enters the mixer, or more precisely, immediately after the antenna in the external image reject filter (i. e., IRF in Fig. 2). The image rejection filter specifications depend on the IF value and they are more relaxed as the image frequency is larger, respectively as the distance between the RF carrier and its image is larger. Signal conditioning constraints, set by the channel selection filter located after the down conversion mixer (i. e., the second band pass filter of Fig. 2), prevent the choice of a very large IF. This toughens image filtering requirements. In practice, ceramic filters satisfy the constraints, but they possess two major drawbacks: they are quite expensive and by far not compatible with monolithic integration. Channel selection is also demanding, as for many applications channel bandwidth is fairly small compared with IF. In such context, bandpass Surface Acoustic Wave (SAW) filters are used for analog channel selection. But, these types of filters are unattractive to SoC ICs for the same two reasons as the ceramic antenna filters: incompatibility with monolithic integration and high cost. Basically, single conversion superheterodyne receiver design is driven by the trade-off between antenna and channel filtering, which imposes the optimum IF frequency.

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35

a.

b.

Figure 3. Down-conversion: a. without Image Rejection and b. with Image Rejection.

Second of all, so far, the design of superheterodyne receivers has been optimized to alleviate image rejection rather than optimizing RF performance. Thus, using an image rejection receiver that implements a complex mixer to cancel out the unwanted image signal, removes the lock on architecture enabling the RF performance optimization. The principle schematic of such a receiver is depicted in Fig. 4.a. The complex mixer is made out of two mixers which share the same RF input, while the LO port is controlled by two quadrature signals. By adding a 90 degrees delay line in one signal path, the down converted image signals will be inphase, while the useful signals will be 180 degrees delayed. Hence, by considering the difference between the two paths the image signal is cancelled, while the useful signal is added. The major advantage of this approach is the antenna filtering becomes less critical. Thus, the use of expensive and bulky, external (off-chip), ceramic filters are no longer required. On the other hand, the image rejection now depends on the quadrature accuracy of both gain and phase of the LO and IF paths. If the two LO signals exhibit exactly 90 degrees phase delay and have the same amplitude, while the gain of the two paths are perfectly matched, the unwanted image signal is completely rejected. Hence, image rejection receivers cancel out the image signals by subtracting two – potentially very large – signals, resulting in a difference that is theoretically equal to zero. −90º

−

However, any gain error or phase error between the two signal paths will determine an incomplete annihilation of the image signal. Thus the image rejection, IR, is given by, [10]:   1  Gain I Q err IR  20 log   tg Phase I Q err   2  Gain





−

IF

+

0º

0º

90º

90º

90º

LO #1

LO



Third of all, all receiver architectures presented so far have to fight image rejection. In direct conversion receivers also known as homodyne receivers, the IF frequency is zero, hence, the useful signal is its own image.

+

0º

  

where Gain represents the receiver’s gain, GainI-Qerr is the IQ gain mismatch and PhaseI-Qerr is the I-Q phase mismatch. Since accurate wide-band quadrature phase shifters are difficult to design, Weaver receivers of Fig. 4.b are preferred. To cancel the need for the 90 degrees phase shift on the signal path an extra pair of mixers and quadrature LO signals are required. Still, the LO signals quadrature accuracy, of both gain and phase, and the gain matching of the quadrature downconverted channels set the image rejection performance as described by (1).

RF

RF





a.

LO #2

b. Figure 4. a. Image Rejection Receiver and b. Weaver Receiver.

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IF

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36

I Baseband RF

I/Q LO Q Baseband

Figure 5. Quadrature Direct Conversion Receiver Block Schematic.

Therefore, in a homodyne receiver (see Fig. 5) the image signal has an amplitude comparable to the useful signal, and hence, image rejection requirements are relaxed. Furthermore, all baseband processing, like analogue filtering, analog-to-digital conversion and the digital demodulation, take place at the lowest possible frequency. These features make the homodyne receiver an ideal candidate for monolithic integration and open the possibility of creating an “universal” receiver, compatible with all wireless standards, [4]. However, although direct conversion receivers monolithic integration seems straight forward there are several drawbacks to this approach. The second major issue of direct conversion architecture is that even order distortions generate a signal dependent DC offset. Another issue of such architecture is self-mixing. Basically, the LO signal, which in most cases is orders of magnitude larger than the RF signal, leaks to the RF port of the mixer and it will be mixed down to baseband. If the LO leaking signal is phase shifted with respect to the real LO, this almost always being the case in practice, the DC offset caused by self-mixing may dominate the mixer output.

RF

I/Q LO

Active Poly Phase Filters

Finally, although direct conversion architecture has relaxed image rejection specifications, it has to fight with DC offset, 1/f noise and self-mixing. Hence, the low-IF architectures (see Fig. 6) become attractive. Essentially, the RF signal will now be downconverted to a low IF frequency (i. e., up to a few hundred kHz) and thus, the issues of direct conversion receivers are alleviated. But, the image rejection requirements are again tight. This stresses the implementation of the active poly-phase filter that follows the mixer and is used for image rejection and channel selection. I Baseband

Q Baseband

Figure 6. Low-IF Conversion Receiver Block Schematic.

B. SDRR Architecture Choice: Heterodyne vs. Homodyne The main features of a SDRR must be a versatile architecture and the ability to be reconfigured on-the-fly as the communication burst requires. From the perspective of SoCs, the optimization of the chip power dissipation and die area is mandatory. As the SDRR will be a part of a SoC, this trade-off must be the main guideline in sizing the SDRR design, as well as in choosing its architecture, as a first and, very important, starting point. From area perspective the cumbersome image rejection filters of superheterodyne topology are not so attractive for monolithic integration. On the other hand, for direct conversion architecture the image rejection requirements are much smaller than for any other receiver architecture. Furthermore, the IF selection for superheterodyne architectures is fairly cumbersome and cannot be extrapolated in a systematic way to all standards, as it would be required for a true SDRR, [11]. The IF should be chosen to avoid the in-band downconversion of strong interferers. In most applications the nearest strong interferers is located three channels apart from the RF carrier, [12]. As the channel bandwidth differs even within the same wireless standard, it is not possible to select intermediate frequencies which will lead to reuse of same image filters for a multi-standard environment compatible receiver. Similarly, it is difficult to design an accurate wide-band 90° phase shift block for the image rejection receiver of Fig. 4.a, as imposed by a multi-standard application. Also, the fact the Weaver receiver from Fig. 4.b requires a cascade of two complex mixers increases the overall receiver area and power consumption, while it is also constraining its image rejection capabilities. From power consumption perspective the homodyne topology has even more advantages. First of all, the baseband signal processing takes place at the lowest possible frequency. Secondly, this topology is not tributary to the 3 dB noise penalty of superheterodyne architectures, [11]. Hence, the SDRR architectures of choice are superheterodyne, homodyne or low-IF. Table II summarizes the advantages and disadvantages of the three architectures with respect to monolithic integration in a SDR SoC. Given the overview presented in Table II, it becomes clear the direct conversion receivers represent the optimal choice for satisfying the requirements of a true SDRR. This has been validated through several circuit implementations in CMOS processes, [1, 13-15]. As noted, zero-IF receivers are susceptible to multiple issues (e. g., DC offset, 1/f noise, the self-mixing process), which make their monolithic integration quite a challenging task. All these aspects will be discussed in the following subsection.

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TABLE II. PROs  Well known

SUPERHETERODYNE, HOMODYNE AND LOW-IF RECEIVERS FOR SOC INTEGRATION – PROS AND CONS

Superheterodyne CONs  Requires off-chip components Ceramic antenna filter SAW Filter

Homodyne PROs  Less external components No ceramic antenna filter No SAW Filter

 IF selection Difficult to mitigate the multistandard environment

 Image is wanted signal mirror Mirror signal is not a strong interferer

 Power consumption BB signal conditioning is done at IF

 Power consumption BB signal conditioning is done at lowest frequency

 3 dB noise penalty, [10] Image frequency band degrades receiver SNR by 3 dB

 No 3 dB noise penalty Quadrature receiver

C. Making the Homodyne Architecture Ready for Monolithical Integration As detailed in the previous sub-section and in-depth analyzed in [16], due to intrinsic operation of homodyne systems, they exhibit a large sensitivity to DC offset, either static or dynamic, and 1/f noise. Also, self-mixing issues can dramatically reduce performance of receivers implemented with direct conversion architectures. First of all, homodyne architecture is extremely sensitive to static DC offsets and 1/f noise. As for some wireless standards a large part of the signal energy is found at low frequencies (e. g., GSM), the down-converter mixer output is DC coupled to the anti-alias LPF. Thus, the receiver output risks of being overloaded even for small values of the DC offset, in the order of a few hundreds μV given the large VGA gain, usually larger than 60 dB, [17]. Regular AC coupling will not solve the issue, as receiver settling will be severely affected by a low cut−off frequency in the order of a few hundred Hz.

I Frequency Synthesizer

Low-IF CONs  DC Offset

PROs  no DC Offset

 1/f noise

 reduced 1/f noise

 self-mixing

 reduced self-mixing

CONs  High image rejection requirement

Hence, the receiver must embed an offset calibration loop. One possibility is to use the correlated double sampling offset compensation technique, [18]. This is preferred to chopper stabilization, [19], as there is no risk of spurs overwhelming the receiver output spectrum. The receiver block schematic embedding offset calibration is shown in Fig. 7, redrawn from [16]. In the first phase (i. e., Offset_meas control signal is “High” – switches closed) the baseband chain DC offset is sampled on a capacitor, via the additional transimpedance amplifier, while the antenna input is shorted to ground, [10]. During normal operation, the second phase (i. e., Offset_meas is “Low” – switches open), the RF input is connected back to the antenna and the signal flows through the receiver, while the DC offset is inherently cancelled out. The static DC offset compensation loop will also reduce the 1/f noise level. The Fig. 7 receiver embeds multiple LNAs to mitigate the multi-standard frequency plan requirements from Table I.

Q

LO Divider

Offset_meas Figure 7. Low-IF Conversion Receiver Block Schematic.

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38 The second major issue of the homodyne receiver architecture is the signal dependent DC offset generation due to even order distortions. the received input power can change dynamically, since other transmitters may start to communicate, a dynamic offset component is generated due to the receiver second order non-linearity. Therefore, dynamic offset compensation, to the extent required by almost all commercial wireless standards, implies the usage of a differential architecture for the whole receiver chain, starting with its LNA. Thirdly, the self mixing process, determined by the LO mixing with the LO signal leaking the VCO to the receiver input, can generate a large DC offset overloading the receiver output. Hence, the VCO must not oscillate at the same frequency with the RF carrier frequency. Hence, the quadrature LO signals driving the downconverter mixer must be obtained by dividing down the VCO frequency in the LO divider block from Fig. 7 (e. g., [20]). Moreover, very good isolation between RF and LO mixer ports is required for good receiver performance. III.

DEFINING THE SDR SENSITIVITY, NOISE FIGURE AND GAIN REQUIREMENTS

A. Introducing the Minimum Signal-to-Noise Ratio Required for Proper Signal Demodulation, SNR0 The front-end must be able to downconvert the useful signal without hampering its electrical properties, such as the baseband processor is able to demodulate the information within a specified Bit Error Rate (BER). Basically there is a minimum SNR at the receiver output, SNRout, required for the digital demodulator to properly demodulate the useful signal. This minimum SNRout value is further on denoted as SNR0. As expected, higher SNRs are required to demodulate the signal within the same BER as the modulation number of bits per symbol increases. Increasing the SNR requirements is achieved at the cost of higher power consumption, by increasing the signal power, or at the cost of lowering the bandwidth. In any case, there is a trade-off between power consumption and BitRate (BR). This can be mathematically expressed as follows:

From (3) results there is a minimum amount of signal energy required to transmit a bit: 

Eb  N 0

2 BR BW  1  BR BW



As (4) shows, the minimum Eb only depends on N0 and on the coding scheme, through the BR/BW ratio. There are two extreme cases depending on the BR/BW ratio value. Firstly, if BR/BW is very low (i. e., a large BW is used for a small BR) the limit from (4) is: 

Eb  N 0 ln 2 



This case is exploited by spread spectrum systems. Basically, the SNR0 has a negative value for UMTS and WLAN 802-11 standards, as it accounts the processing gain, [21]. Secondly, for large BR/BW (e. g., for 64QAM), the limit from (4) becomes: 

Eb  N 0

2 BR BW  BR BW



Hence, the SNR0 in this case is: 

SNR0 

BR  Eb  2 BR BW  N 0

BW





As an example the SNR from (7) translates to 18 dB SNR0 for 64QAM. Of course, this theoretical limit translates to a few dB higher value in practical implementation. Based on the analysis presented in [22], the SNR0 as a function of the BER has been determined for the basic modulation schemes. Table I notes the targeted standards signal modulation and the corresponding SNR0 values. The usage of the concept “SNR0” facilitates the finding of the multi-standard receiver key electrical parameters by enabling a standard independent approach.

B. Sensitivity and Noise Figure One of the most important parameters of a wireless   receiver is its sensitivity, SRX. The sensitivity is defined as the minimum input signal the receiver must be able to demodulate within the specified BER. where S, respectively N, is the receiver input signal, Thus, the Signal-to-Noise Ratio at the RX output, SNRout, respectively noise, power, Eb is the energy per bit, N0 is the has to be above SNR0. As each standard specifies a noise power density at the receiver input; in practice, sensitivity level, given the useful signal RF bandwidth, N0 = kBT∙F – where F is the receiver noise factor. BWRF, the receiver NF, NFRX, is calculated as: Given (2), the maximum bit-rate from can be written as, [2]: NFRX  S RX  10 log BWRF  SNR0  N 0     BR  Eb  S     where N = k T = −174 dBm/Hz represents the noise power  BR  BW log 2 1    BW log 2 1  0 B N BW  N 0     spectral density at the antenna output for T = 290 °K. S  BR  Eb ,   N  BW  N 0

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39 In practice, an overhead to SNR0 should be considered in (8), since the overall receiver SNR is degraded by multiple factors, not only by noise (e. g., imperfect impedance matching, multipath channel). The receiver NF specifications for all the wireless standards can be calculated with (8) by accounting the specified sensitivity levels from Table I. A NF as the one derived by (8) can be obtained at the expense of larger power consumption of thy receiver. In order to maximize the link budget, most commercially available dedicated receivers push their sensitivity level towards smaller and smaller values by decreasing NFRX. Hence, a true re-configurable multi-standard solution must embed a receiver with a small NF (typically < 3 dB) in order to be able to achieve a low enough sensitivity for all the targeted standards. Table I also comprises the required sensitivity levels, assuming NFRX = 3 dB, for all the envisaged wireless standards. C. Maximum gain requirements In general, the receiver signal conditioning path gain is constraint by the received signal strength. Any wireless receiver with an analog signal conditioning path embeds at least one variable gain block. Thus, for each communication burst an Automated Gain Control loop (AGC) measures the Receiver Signal Strength Indicator (RSSI) and changes the receiver gain accordingly, in order to avoid the ADC overloading and to optimally load it. The receiver maximum gain requirements are constraint by the ADC full scale level, FSADC, and the specified receiver sensitivity. In order to optimally load the ADC, the receiver signal conditioning path maximum gain, GRX, is given by:

For a multi-standard receiver embedding analog signal conditioning (see Fig. 1.c), k is set by the Variable Gain Amplifier (VGA) gain step (e. g., 6 dB, [14]). Equation (9) assumes all interferes and blockers have been totally filtered out before the ADC. This corresponds to the case of complete analog channel selection. Table III presents the receiver signal conditioning path maximum gain requirement for all the envisaged standards calculated based on equation (9) for a 1 V FS ADC and for a receiver matched to 100 Ω with k = 0.9; the NFRX of the receiver was assumed to be 3 dB. For direct sequence spread spectrum systems (e. g., WLAN 802.11b) the gain requirement is smaller, as in practice other signals will be present as well inside the received bandwidth. Nonetheless, we can conclude, based on Table II data, that the low sensitivity levels of the targeted wireless standards require a large maximum gain for the multistandard receiver. IV. BLOCKERS AND INTERFERERS IMPACT ON THE MULTI-STANDARD RECEIVER CHARACTERISTICS

Besides the useful signal, other interferers and blockers can be present at the antenna input. The list comprising all interferes and blockers under which influence the receiver must still be able to properly demodulate the wanted signal represents the receiver blocker diagram. For each wireless standard such a receiver blocker diagram is specified. Based on the envisaged wireless standards blocker diagram analysis, in [12] a receiver generic blockers diagram has been constructed. This newly introduced tool enables the designer to handle efficiently the large amount of information comprised in the targeted radio standards. Thus, based on the receiver generic blockers diagram analysis it results immediately there are two major issues due to blockers and interferes:  the receiver output clipping, due to the large receiver k  FS ADC gain requirements and to the large difference between the GRX     useful signal and the blocker levels (i. e., typically > S RX +40 dBc);  intermodulation distortions that fall in-band, due to the where k < 1 accounts the head room taken to avoid the ADC receiver not perfectly linear transfer characteristic. overloading. The receiver output clipping can be handled (i) by making the LNA and VGA blocks gain variable and (ii) by TABLE III. THE MULTI-STANDARD RECEIVER MAXIMUM GAIN allowing the receiver high frequency part noise and linearity REQUIREMENTS performance to adjust with the RF front-end gain. This has Wireless Standard GRX [dB] analysed in-depth in [23]. GSM 115 On the other hand intermodulation distortions are unwanted products that potentially fall in-band and cannot be UMTS 129 disseminated from the useful signal. Thus the wanted signal Bluetooth 100 demodulation is affected due to the SNR degradation. DECT 103 Further on the analysis presented in this Section focuses on finding the values for the Figures of Merit (FOMs) used in WLAN IEEE 802.11 b,g 1 / 2 / 5.5 / 11 Mbit/s 110 / 108 / 97 / 95 evaluating the radio receiver linearity performance: the IIP2 (DSSS) and IIP3. WLAN IEEE 802.11 a,g (OFDM)

6 / 9 / 12 /18 24 /36 /48 /54 Mbit/s

101 / 100 / 98 / 96 93 / 89 / 85 / 84

A. Finding the SDR IIP2 While receiving the RF input power may change significantly because of the reception of unwanted blockers/interferers. Due to the receiver even order

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40 distortions, the received signal DC offset component will change. This dynamic offset effect upsets the received signal demodulation, especially if the envisaged modulation concentrates a large part of the symbol spectral power at low frequencies. This is the case for older standards like GSM, as the latest wireless standards use modulation schemes that do not carry information at low frequencies. The figure of merit quantizing the analog front-end second order distortions is the second order intercept point, IP2. The SDRR input referred IP2, IIP2RX, is given by, [10]:

Given (11), the receiver IIP3, IIP3RX, must meet the condition specified by the equation: 

IIP 3RX  Pinterferer 

Pinterferer  PIM 3  2



where Pinterferer is the power per interferer of two interferers that cause the in-band third order distortion. A special case is represented by OFDM Signals. An OFDM signal comprises frequency orthogonal sub-carriers, [19]. Receiver non-linearity leads to formation of bogus   signals in-band due to sub-carrier intermodulation. The iIP2 RX  2  Pblocker  Pin  SNR0  figure of merit in evaluating the third order intermodulation where Pblocker is the blocker level and Pin is the wanted signal products thus formed is the Composite Triple Beat (CTB). level. As is pointed out in [24] the worst case for the CTB Based on the targeted standards analysis, it results the products level is found in the centre band of the OFDM worst case scenario is met for the GSM standard that requires signal spectrum: IIP2RX = +46 dBm, [2].   CTB [dB]  2IIP 3RX  Pin   1.74  B. Finding the SDR IIP3 For most wireless receivers, given the fully differential circuit implementation, the dominant non-linear contribution comes from the third order coefficient of power series expansion of their transfer characteristic. The maximum inband level of the third-order intermodulation product, PIM3, must be smaller than the useful RF signal level with SNR0: 

 

PIM 3  Pin  SNR0 

In practice, a supplementary head room to SNR0 should be considered, since the overall receiver SNR is degraded by multiple factors, not only by the down-converted spurs. TABLE IV. Standard

MULTI-STANDARD RECEIVER IIP3 REQUIREMENTS Intermodulation conditions

Eq.

Value

Pinterferer @ −49 dBm, Pin @ −99 dBm

(12)

−19

UMTS

Pinterferer @ −46 dBm, Pin @ −114 dBm

(12)

−21

Bluetooth

Pinterferer @ −39 dBm, Pin @ −64 dBm

(12)

−18.5

DECT

Pinterferer @ −47 dBm, Pin @ −80 dBm

(12)

−24

WLAN Pinterferer @ −35 dBm, Pin @ −70 dBm IEEE 802.11b,g CCK – 11 Mbit/s (DSSS)

(12)

−12

Interferer intermodulation: Pinterferer @ Sensitivity, Pin @ +32…+15 dBc (6…54 Mbit/s)

(12)

−32

Blocker intermodulation: Pblocker @ −10 dBm, Pin @ −42 dBm, BPSK – 6 Mbit/s

(12)

+8.5

Sub-carrier intermodulation: Pin @ −20 dBm, N = 52 64QAM – 54 Mbit/s

(15)

+10

W-LAN IEEE 802.11a (OFDM @ 5 GHz)

carriers,

Sub-carrier intermodulation: Pin @ −30 dBm, N = 52 carriers, 64QAM – 54 Mbit/s

CTB  Pin  10 log N  SNR0 



where N represents the number of OFDM sub-carriers. In (14) SNR0 represents the corresponding SNR headroom of the OFDM sub-carrier modulation. Given (13) and (14), it results that in order to avoid destructive inter-carrier intermodulation, the IIP3RX must meet the following condition:

RX IIP3[dBm]

GSM

W-LAN IEEE 802.11g (OFDM @ 2.4 GHz)

where Pin is the OFDM signal power in all the carriers. Hence, in order for the digital back-end to be able to still demodulate properly the wanted signal, the CTB level must be smaller than the useful RF signal level per carrier with SNR0:

(15)

+5



IIP 3RX 

1 Pin  10 log N  SNR0  1.74  2



Each wireless standard specifies a set of particular intermodulation conditions. Table IV summarises the power per interferer of two interferers that cause the in-band distortion and the input signal power. By analysing all the targeted standards, the receiver IIP3 specifications were derived using (12) or (15) and noted in Table IV. The large variations in the IIP3 requirements are a reflection of the extreme reception conditions specific to the wireless environment. In [23] it is shown a versatile receiver is able to mitigate all presented scenarios, by adjusted dynamically its linearity and noise performance with the received power. V.

CONCLUSIONS AND FUTURE WORK

This paper conducted an analysis for finding the optimal architecture for a SDRR embedding analog signal conditioning and targeting compatibility with the major commercial wireless standards (see Table I).

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International Journal on Advances in Telecommunications, vol 5 no 1 & 2, year 2012, http://www.iariajournals.org/telecommunications/

41 Based on the analysis of the key receiver architectures, the homodyne receiver is found to suit best a monolithic implementation of a SDRR. By enhancing the classical homodyne architecture through the inclusion of an offset cancelation loop and quadrature LO generators the SDRR monolithic integration is made possible. The presented solutions are realized without introducing particular analog tricks to satisfy the needs of only one of the standards, as the SDRR must represent “universal receivers”, and not be turned into “multi-standard ASICs”. Further on, the minimum SNR at the receiver output, SNR0, required for a proper signal demodulation was calculated for all the envisaged standards. The usage of the concept “SNR0” facilitates the finding of the multi-standard receiver key electrical parameters by enabling a standard independent approach. Thanks to the standard independent systematic approach the presented analysis found the values for the key SDRR electrical specifications (i. e., NFRX, IIP2RX and IIP3RX) that ensure its compatibility with the envisaged standards. Of course, a true SDRR has to be versatile and robust, such as it can adjust dynamically its performance (e. g., NFRX, IIP3RX) depending on the communication burst particularities. Nonetheless if a SDRR targets compatibility with the standards from Table I, it must meet the electrical specifications determined in this analysis. So, the presented analysis constitutes the starting point in building the SDRR. Further on, the SDRR electrical specifications must be partitioned over its building blocks. The optimal specification partitioning must account the limitations due to the physical implementation (i. e., CMOS process) for each of the SDRR building blocks.

[6] [7] [8]

[9] [10] [11]

[12]

[13]

[14]

[15]

[16]

[17]

[18] [19]

ACKNOWLEDGMENT The authors would like to express their acknowledgment to Dr. F. Op’t Eynde for the fruitful discussions on the topic.

[20]

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2012, © Copyright by authors, Published under agreement with IARIA - www.iaria.org