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Degradation of Memory Retention Characteristics in DRAM Chip by Si Thinning for 3-D Integration Kangwook Lee, Senior Member, IEEE, Seiya Tanikawa, Mariappine Murugesan, Hideki Naganuma, Haro Shimamoto, Takafumi Fukushima, Member, IEEE, Tetsu Tanaka, Member, IEEE, and Mitsumasa Koyanagi, Fellow, IEEE
Abstract— The Young’s modulus (E) of Si substrate begin to noticeably decrease below 50-µm thickness. The Young’s modulus in 30-µm thick Si substrate decreased by 30% compared to the modulus of 50-µm thickness. In 30-µm thick Si substrate, the lattice structure of Si atom is highly distorted. Large distortion of the lattice structure induces the Young‘s modulus reduction, consequently weakens the mechanical strength. A DRAM chip of 200-µm thickness is bonded to a Si interposer and thinned down to 50/40/30/20-µm thickness, respectively. The retention characteristics of DRAM cell are degraded depending on the decreasing of the chip thickness, especially dramatically degraded below 50-µm thickness. The retention time of DRAM cell in the 20-µm thick chip is shortened by ∼40% compared to the 50-µm thick chip, regardless of the well structure (triple-well, twin-well). The distortion of the lattice structure in the thin chip effects carrier recombination rates, consequently a shortening retention time of DRAM cell. Index Terms— 3-D DRAM, mechanical strength, retention time, Si Young’s modulus.
I. I NTRODUCTION
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EMAND for high performance and highly integrated system have been significantly increasing in correspondence to future needs. To meet these requirements, 3-D integration technology has attracted attention because it vertically stacks multiple LSI chips such as processor, memory, logic, analog, and power ICs into one stacked chip with through-silicon vias (TSVs) [1], [2]. To realize a compact-sized 3-D LSI, each functional wafer should be thinned to 10∼–50-μm thickness. However, the ultrathin nature of Si substrate leads to several problems such as weak mechanical strength, warping, and local deformation in the stacked die [3], [4]. Moreover, the weak mechanical strength of the extremely thin die/wafer has a potential concern leading to die breaking for 3-D IC integration, because thin LSI chip with high-density TSVs is highly fragile and more easily damaged. Hence, it is important
Manuscript received March 26, 2013; revised May 20, 2013; accepted May 27, 2013. This work was supported in part by NEDO "Development of Functionally Innovative 3-D-Integrated Circuit (Dream Chip) Technology" project. The review of this letter was arranged by Editor D. Ha. K. Lee, M. Murugesan, T. Fukushima, and M. Koyanagi are with New Industry Creation Hatchery Center, Tohoku University, Sendai 980-8579, Japan (e-mail:
[email protected]). S. Tanikawa, H. Naganuma, and T. Tanaka are with the Department of Bioengineering and Robotics, Tohoku University, Sendai, 980-8579 Japan. H. Shimamoto is with the 3-D-Integration Technology Research Department, Association of Super-Advanced Electronics Technology, Chuo-ku 10433, Japan. Color versions of one or more of the figures in this letter are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/LED.2013.2265336
Fig. 1.
Dependency of Young’s modulus with Si substrate thickness.
to understand the impact of chip’s mechanical strength on device reliabilities decreasing die thickness, especially below 50-μm thickness. In this letter, the influence of thinning of Si substrate on memory retention characteristics in DRAM chip for 3-D DRAM integration is electrically characterized. II. M ODULUS C HARACTERISTICS IN T HIN S I S UBSTRATE To basically understand the mechanical property of thin Si substrate, the Young’s modulus (E) of Si substrate is evaluated by nano-indenter method. The relationship among the crack length, the maximum load, and material parameters is described by Lawn et al. [5] that K C = α(E/H )1/2 P/c3/2 , where E, H , and K C are Young’s modulus, hardness, and fracture toughness of the indented material, respectively, P is the maximum load, c is the length of the radial crack trace on the surface after the indenter is totally unloaded, α is a constant depending on the type of indenter. The nano-indenter tip of pyramid geometry is projected into the surface of thin Si substrate. The load is continuously increased to a designated maximum value. Next, holding segment is introduced to allow the material to relax before unloading. The process is repeated four times at relatively low applied load of 24 mN, and the position of the indenter tip on the surface is monitored with a capacitance meter. In this letter, we evaluate the Young’s modulus of Si substrates with different thickness varying from 100, 50, and 30 μm, where the backside surfaces of each substrate are chemical-mechanical polishing (CMP) processed after mechanical grinding. The Young’s modulus of Si substrate is decreased depending on the reduction of the Si substrate thickness as shown in Fig. 1. The Young’s modulus
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(a) 100-µm Si thickness
(b) 30-µm Si thickness
Fig. 2. Reciprocal lattice images obtained by microdiffraction method with (a) 100- and (b) 30-µm Si substrate thickness.
values of Si substrates of 100- and 50-μm thicknesses are 180 GPa and 171 GPa, respectively. These values are similar to the Young’s modulus of bulk Si (188 GPa) [6]. However, the Young’s modulus of 30-μm-thick Si substrate noticeably decreased by ∼30% (120 GPa) compared to the modulus of 50-μm-thick Si substrate. It indicates that the Si substrate with 50-μm thickness has enough mechanical strength to achieve the high-reliable 3-D LSI, because the mechanical property does not degrade compare to a bulk Si substrate. However, below 50-μm thickness, it has potential reliability challenges because the mechanical property is noticeably deteriorated. To characterize the deterioration of mechanical property in the thin Si substrate, the lattice structure of Si atoms is evaluated. Fig. 2 shows the reciprocal lattice images of 100-μm and 30-μm-thick Si substrates obtained by microdiffraction method using synchrotron radiation at SPring8, using 200-nm beam size. In case of 100-μm-thick Si substrate, the spread in qx (which is closely related to the lattice tilt in Si crystal) and the spread in qz (which is correlated to the d-spacing in Si lattice) are ∼0.025 and 0.02 rad. In case of 30-μm thick Si substrate, q x and qz values are ∼0.15 and 0.08 rad. The larger q x and qz values mean that Si atomic lattice is more distorted. The lattice structure of Si atom is highly distorted in the 30-μm thick substrate compared to the 100-μm thick Si substrate. We assume that the large distortion of the lattice structure induces the reduction of Young‘s modulus and consequently weakens the mechanical strength of thin Si substrate. III. I MPACT OF M ECHANICAL S TRENGTH ON R ETENTION C HARACTERISTICS IN T HIN DRAM C HIP DRAM stores electronic charges as information data. The control of the retention time (refresh) for the stored charge is a key issue for realizing reliable 3-D DRAM. This requirement derives from needs to keep the refresh interval constant even if the thin memory chips stack vertically to achieve 3-D DRAM. Therefore, one of the most critical reliability issues for high-reliable 3-D DRAM is the data retention characteristics attributed to the electron leakage in the storage capacitor. The electron leakage is induced by several mechanisms. One of the critical origins for the electron leakage is mechanical stress and damages introduced by the wafer thinning in the 3-D integration process. To achieve high-density memory, it is
(a) Twin well
(b) Triple well
Fig. 3. Failure rate of DRAM cell array (W/L = 3.50/0.30 μm) fabricated in (a) twin-well and (b)triple-well as a function of retention time measured after chip bonding (200 μm thickness) and chip thinning to 50/40/30/20 μm thicknesses, respectively.
required to stack many number of chip with thin thickness as possible because of the height limitation of a package. Therefore, it is more challenging to achieve high-density DRAM module such as higher memory cube (HMC) by thinner thickness DRAM chip. The influence of thinning of Si substrate on device reliabilities in thinned DRAM chip for high-reliable 3-D DRAM is electrically characterized. A DRAM TEG chip comprising NMOS cell arrays is fabricated using 90-nm CMOS technology. DRAM is organized by 20 macros and each macro is composed of a memory cell array, a decoder, a sense amplifier, and buffer circuits. A planar-type cell is employed as a DRAM memory cell. The memory chip is fabricated using a p/p- Si substrate with twinwell and triple-well (introduced by deep n-well) structures to compare the well structure effect from the mechanical damage. At first, the memory chip of 720-μm thickness is thinned down to 200-μm thickness by mechanical grinding to fabricate Cu/Sn bumps on the chip surface. The chip is face-up bonded temporarily on a supporting wafer at 200 °C. A TEOS layer of 200-nm thick is deposited at 300 °C for 2 min and patterned by dry etching process. After sputtering Ta barrier and Cu seed layers on the chip surface, the photoresist is spin-coated and patterned to form metal bumps on metal pads. Metal bumps of 3-μm thick Cu and 2-μm thick Sn layers are formed on metal pads by electroplating process in a die-level. After removing the resist, Ta barrier and Cu seed layers are etched except for those underneath the metal bump. The chip is debonded from the supporting wafer. Then, the memory chip is face-down bonded to a Si interposer chip through Cu/Sn bumps by thermo-compression bonding method for 2 min at 260 °C. The epoxy material filled the gap between two chips in a vacuum atmosphere and annealed for 30 min at 200 °C to endurance during the wafer thinning process. The retention time of DRAM cell is characterized as a reference. To electrically characterize the influence of thinning of Si substrate on device reliabilities, the DRAM chip is thinned down to 50-μm thickness by mechanical grinding and following CMP process. The retention time of DRAM cell is evaluated. After evaluation, the DRAM chip is thinned down to 40, 30, and 20 μm thicknesses by plasma Si etching to avoid abundant mechanical-induced stress. The retention time of DRAM cell is evaluated at each chip thickness to characterize the dependence of the chip thickness. Fig. 3 shows
This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination. LEE et al.: DEGRADATION OF MEMORY RETENTION CHARACTERISTICS IN DRAM CHIP BY SI THINNING FOR 3-D INTEGRATION
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and band-gap energy level. The reduction of Young‘s modulus induces the deterioration of the mechanical strength. The shift of band-gap energy level impacts carrier recombination rates, consequently a shortening retention time of DRAM cell. From these results, we have concern that the retention characteristics of the DRAM cell could be affected by the chip thickness below 50-μm thickness in addition to metal impurities. It will be potential reliability challenge to achieve high-reliable and high-density 3-D memories comprising many number of thin Si substrate with below 50-μm thickness. Fig. 4. Median retention time of DRAM cell array at 50% failure versus the Young‘s modulus depending on the chip thickness.
the failure rate of the DRAM cell array (W/L = 3.50/0.30 μm) fabricated in (a) twin-well and (b) triple-well as a function of static retention time at 24 °C measured after chip bonding (200 μm thickness) and chip thinning to 50/40/30/20 μm thicknesses for the comparison, respectively. To avoid another path for storage capacitor charge from leaking out, the retention time is measured at 24 °C and 0.8 VDD without substrate bias. In case of twin-well, the DRAM cell array shows 50% failure at 3601, 3253, 2370, 2027, and 1842 msec at 200/50/40/30/20-μm thickness conditions, respectively. In case of triple-well, the DRAM cell array shows 50% failure at 3688, 3219, 2580, 1946, and 1918 at 200/50/40/30/20 μm thickness conditions, respectively. As seen in the figure, the retention characteristics of DRAM cell are degraded depending on the reduction of the chip thickness. Especially, below 50-μm chip thickness, the retention characteristics of DRAM cell are noticeably degraded regardless of the well structure (triple-well, twin-well) in the Si substrate. The retention time of DRAM cell in the 20-μm thick chip is dramatically shorted by ∼40% compared to the 50-μm-thick chip. Fig. 4 shows the correlation of the median retention time of DRAM cell array at 50% failure versus the Young‘s modulus of Si substrate depending on the chip thickness. Below 50-μm thickness, DRAM retention characteristics and Young‘s modulus of Si substrate begin to decrease abruptly. From the figure, we assume that the distortion of the lattice structure of Si atoms in the thin Si substrate is the primary factor in Young‘s modulus reduction and the refresh degradation of DRAM cell. In case of 200-μm chip thickness, the DRAM cell in triplewell shows relatively good retention characteristics compared to the DRAM cell in twin-well. However, below 30 μm chip thickness, the DRAM retention characteristics show severe degradation regardless of the well structure in the substrate. We assume that below 50-μm thickness, the lattice structure of thin Si substrate is severely distorted; hence it causes an impact on fundamental properties such as Young‘s modulus
IV. C ONCLUSION The Young‘s modulus (E) of Si substrate began to noticeably decrease below 50-μm thickness. The Young‘s modulus in 30-μm thick Si substrate decreased by ∼30% compared to the modulus of 50-μm thickness. In 30-μm thick Si substrate, the lattice structure of Si atom was highly distorted. Large distortion of the lattice structure in the thin Si substrate induced Young‘s modulus reduction, which consequently deteriorated the mechanical strength. The retention characteristics of DRAM cell degraded depending on the decreasing of the chip thickness, and are and were especially dramatically degraded below 50-μm thickness. The retention time of DRAM cell in the 20-μm thick chip was dramatically shortened by ∼40% compared with the 50-μm thick chip, regardless of the well structure. We assumed that the band-gap energy level in the thin chip is affected by the distortion of the lattice structure, hence affecting carrier recombination rates, consequently shortening retention time of DRAM cell. V. ACKNOWLEDGMENT The authors would like to thank Y. Imai and H. Kimura for their kind help in carrying out microdiffraction experiment at SPring-8. R EFERENCES [1] M. Koyanagi, H. Kurino, K-W. Lee, et al., “Future system-on-silicon LSI chips,” IEEE Micro, vol. 18, no. 4, pp. 17–22, Jul.–Aug. 1998. [2] M. Koyanagi, T. Nakamura, Y. Yamada, et al., “Three-dimensional integration technology based on wafer bonding with vertical buried interconnections,” IEEE Trans. Electron Devices, vol. 53, no. 11, pp. 2799–2808, Nov. 2006. [3] M. Murugesan, H. Kino, H. Nohira, et al., “Wafer thinning, bonding, and interconnects induced local strain/stress in 3D-LSIs with fine-pitch high-density microbumps and through-Si vias,” in Proc. IEEE IEDM, Dec. 2010, pp. 1–4. [4] M. Murugesan, H. Kobayashi, H. Shimamoto, et al., “Minimizing the local deformation induced around Cu-TSVs and CuSn/InAumicrobumps in high-density 3D-LSIs,” in Proc. IEEE IEDM, Dec. 2012, pp. 1–4. [5] P. Chantikul, G. R. Anstis, B. R. Lawn, et al., “A critical evaluation of indentation techniques for measuring fracture toughness: I, strength method,” J. Amer. Ceramic Soc., vol. 94, no. 9, pp. 539–543, Sep. 1981. [6] M. A. Hopcroft, W. D. Nix, and T. W. Kenny, “What is the Young’s modulus of silicon?” J. Microelectromech. Syst., vol. 19, no. 2, pp. 229–238, Apr. 2010.
