DTS-insensitive, the path from the ingress router to one of the external buffers will be computed. The external buffer will monitor the status of its connected router.
Delay-Differentiated Routing Algorithm to Enhance Delay Performance of WOBAN Xiuzhong Chen, Abu (Sayeem) Reaz, Lei Shi, Pulak Chowdhury, Yi Zhang, Rui Wang, and Biswanath Mukherjee University of California, Davis, USA Email: {xzchen, areaz, pchowdhury, leishi, eezhang, rwang, bmukherjee}@ucdavis.edu Abstract Delay is an important metric in Wireless-Optical Broadband Access Network (WOBAN). We introduce external buffer and design Delay-Differentiated Routing Algorithm (DDRA) for WOBAN. We show that delay performance of WOBAN can be improved by DDRA. 1 Introduction Wireless-Optical Broadband Access Network (WOBAN) is as an economical, high-bandwidth, and untethered solution for broadband access network [1]. It consists of a wireless network in the front end, and an optical network as a backhaul. In a typical WOBAN, an Optical Line Terminal (OLT) connects to several Optical Network Units (ONU). The wireless part of WOBAN typically is a wireless mesh network, which may employ standard technologies, e.g., WiFi or WiMAX. Wireless front end has several gateways which connect to the ONUs of the optical backhaul. In WOBAN, the delay of traffic depends mostly on the wireless part. When load becomes higher, delay increases because of interference and limited capacity of wireless channels [2].
Routing Algorithm (DARA) is proposed as a proactive routing scheme in our prior work [3, 4]. These works mainly focused on decreasing delay through load balancing in different links, but when traffic load becomes higher, system delay will still increase. By defining DTS (Delay-To-Server) as the time from the end system to the server for upstream data, we can divide traffic into two types: DTS-sensitive and DTS-insensitive. In order to prioritize the transmission of DTS-sensitive data to server quickly, we introduce external buffer in the wireless mesh front end of WOBAN (Fig. 1) to store DTS-insensitive data temporarily under overload. The external buffers can store DTS-insensitive data when links are congested and forward them when the link to gateway is available. DDRA is designed to compute both DTS-sensitive path (path for DTS-sensitive packet such as from F to G in Fig. 1) and DTS-insensitive path (path for DTS-insensitive packet such as path from F to B in Fig. 1) for traffic flows and improve the delay performance. The rest of the paper is organized as follows. Section 2 discusses flow shaping and external buffer issues. DDRA is analyzed in Section 3. Section 4 shows the performance improvement through illustrative numerical examples. Section 5 concludes the paper. 2 Flow Shaping and External Buffer Design
Fig.1.
Buffer-based delay minimization setup in WOBAN.
Many research efforts have been directed towards improving the performance of WOBAN. Delay-Aware
In our study, the external buffer is introduced to store temporarily special types of traffic flows. External buffer can be attached to a router/gateway. Here, the external buffer is similar to a router’s internal buffer. However, the size of internal buffer cannot be changed after deployment of a router (typically 16 Mbytes according to the rule of bandwidth-delay product (BDP)). In WOBAN, study [4] shows that a significant proportion of path delay occurs at the links between gateways and their adjacent routers, namely gateway links. Hence, for maximum performance gain, we incorporate external buffers in routers which
have directs link with gateways (e.g., routers A/B/C in Fig. 1). However, efficient buffer placement is an independent, interesting, and open research problem. Most traffic from mobile devices is DTS-sensitive, e.g., mobile IPTV, mobile VoIP and mobile Instant Messaging, etc. Some traffic is DTS-insensitive, such as large files uploaded to a server. If delay requirements of traffic flows are known a priori from applications, we can organize the flows into two categories by comparing with a DTS threshold. Any DTS value above the threshold is treated as DTS-sensitive. It can be set based on traffic type and network status. If the traffic is DTS-sensitive, the path from the ingress router to the gateway will be computed to transmit the flow. If the traffic is DTS-insensitive, the path from the ingress router to one of the external buffers will be computed. The external buffer will monitor the status of its connected router. When the gateway link is available, stored data in the external buffer will be forwarded to the server. So, some of the traffic will be stored in the buffers when traffic load is high, and they will be transmitted when the load on gateway links decreases. This priority mechanism creates balances the load (queue size) of DTS-sensitive traffic at gateway links over time (see Fig. 2).
Fig.2.
links by temporarily storing the DTS-insensitive flows in external buffers. If packet arrival rate at each router in '' WOBAN is λ , the total arrival rate at all gateway links '' ' will be βλ , where β =| R | / | E | is the WOBAN’s aggregation factor, R is the set of wireless routers, and E ' is the set of gateway links. The delay on all wireless links i – except gateway links – is given by:
Qi = 1/ μCi + 1/ 2μCi + λi / μCi ( μCi − λi ) . The delay of a gateway link i is given by:
Qi' = 1/ μ Ci + 1/ 2 μ Ci + βλi / μ Ci ( μ Ci − βλi ) where λi is rate of packet arrivals at link i , i ∈ ⎣⎡1, E ⎦⎤ , Ci is capacity of link i , i ∈ ⎡⎣1, E ⎤⎦ , and 1 / μ is the average size of a packet. In WOBAN with external buffer near the gateways, the delay of gateway links is given by:
Qi' = 1/ μCi + 1/ 2μCi + (1 − α )βλi / μCi (μCi − (1 − α )βλi ) where α is the fraction of DTS-insensitive traffic in total traffic flows. We set the weight of link i as wi = Qi or wi = Qi' . The delay for the entire path can be calculated as: D j = ∑ wi ∗ Bij . i∈[1, E ]
Load balancing of DTS-sensitive traffic at a gateway link.
3 Delay Differentiated Routing Algorithm (DDRA) Packet delay in the wireless mesh of WOBAN consists of four components: (1) Propagation delay, (2) Transmission delay, (3) Slot-synchronization delay, and (4) Queuing delay [3, 4]. Propagation delay is negligible because the distances between mesh routers are small. Transmission delay and slot-synchronization delay are related with the capacity of links and the average size of packets. Queuing delay depends on the arrival and service rates at a wireless link. When load at each router increases, load at gateway link will accumulatively increase because all the upstream traffic to the OLT will pass through one of the gateways. So, queuing delay in the gateway links forms a major portion of the total path delay. DDRA decreases the queuing delay of higher-load
Fig.3.
Topology studied for illustrative examples.
Bij will be 1 when path j includes link i , and it will be 0 when path j excludes link i . DDRA computes K shortest paths according to the link weights. The path to a gateway will be chosen according to the delay of each path, while the path to an external buffer will be chosen by combining both the path delay and the queue size of the external buffer. When delay of paths to external buffer is less than DTS requirement, DDRA selects the external buffer with minimum queue size as the destination.
4 Illustrative Numerical Examples We apply DDRA on a 43-node wireless network with three gateways in the Wildhorse area of Davis, CA, as shown in Fig. 3. Three gateways are co-located with three ONUs which connect to an OLT at the central office. Each router is equipped with one radio of capacity 54 Mbps (IEEE 802.11g). Each node has traffic load which includes two parts: one part is upstream flow which comes from mobile devices, and the other part is downstream flow which is destined for mobile devices. We assume that 30% of the load at each node is upstream traffic. We set K = 3 for K shortest path computation. We compare the performance of DDRA, DARA, and Shortest-Path Routing Algorithm (SPRA), where the link metric is inversely proportional to the link capacity. Figure 4 shows the system DTS for SPRA, DARA, and DDRA when α =0.1.
Additional performance results are not shown here due to space limitations, but they will be included in the conference presentation. 5 Conclusion WOBAN can provide broadband wireless access in a cost-effective way. But multi-hop wireless part of WOBAN introduces delay, especially in gateway links under high load. Introducing external buffer to store some DTS-insensitive flows can reduce system delay in WOBAN. DDRA has been designed to find different paths for flows with different delay requirements. Results show that the delay performance of WOBAN can be improved using DDRA under high load.
Fig.5.
System delay for different α values..
References [1] S. Fig.4.
System DTS for different routing algorithms.
For DTS-sensitive flows, DDRA performs almost similar with DARA and SPRA when load is less than 2.5 Mbps at each node. When load increases, DDRA outperforms both DARA and SPRA; in fact, DDRA can support nearly 1.2 times the maximum load which DARA and SPRA can handle. System DTS of DTS-insensitive flow is a little higher than DARA/SPRA under low load, because DTS-insensitive flow will be stored in external buffer and will be forwarded to a gateway after detecting that the gateway link is available. Under higher load of about 5 Mbps, the delay performances of DARA and SPRA become unacceptable while DDRA still provides reasonable delay. We also investigate the performance of the network for different values of α as shown in Fig. 5, where 10%, 30%, and 70% of upstream load is DTS-insensitive flow. We find that the more DTS-insensitive flow we have, the better is the performance that can be achieved by DDRA.
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