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Design and Development of VHDL Based Tunable Sine Wave Generator Using DDS Technique: Extension to FPGA Implementation B. K. Upadhyaya Tripura Institute of Technology, Narsingarh, Tripura(W), Pin 799009 Email: {
[email protected]}
Abstract- In this work we have experimentally implemented Field Programmable Gate Array (FPGA) based sine wave generation technique using the Direct Digital Synthesis (DDS) principle based on LUT. A Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL) based ROM is designed using embedded RAM of the Xilinx Spartan - 3 FPGA chip. A VHDL based counter is also designed which works as address generator to continuously supply the address of ROM to read the stored sample values from the LUT. The sample values are converted into a continuous sinusoid using a Digital to Analog Converter (DAC). The VHDL program is downloaded into FPGA chip using Xilinx Integrated Software Environment (ISE) tool. The simulation result of VHDL based ROM with address generator is shown in the form timing diagram obtained using ModelSim software. Experimental result of generation of sinusoidal waveform is also presented. Estimated power consumption of the FPGA based design excluding the DAC is found to be 245mW.
I. INTRODUCTION
II. BLOCK RAM IN SPARTAN – 3 FPGA Xilinx Spartan-3 FPGA offers internal storage which is embedded inside the chip for potential applications like local storage, FIFO, buffers, stack etc. This internal storage known as Block RAM (BRAM) and offers advantages [4] over off-chip memory like: i) Number of chips required to implement a system fully is reduced and thus system cost is also lowered. ii) Faster clock rate is possible as external pins and PCB tracks are need not be driven with each memory access. iii) Saving of pins of the chip, as no external address or data bus is required. Fig. 1 shows the block diagram of the single Port BRAM with all interface signals.
WE EN SSR CLK ADDR [10:0]
RAM 16_S9
Control of output waveform with analog circuitry becomes increasingly more difficult in the purview of more complex phase continuous wave modulation techniques. Moreover performance of analog circuit degrades due to aging and environmental changes. A non-linear digital design technique is the right choice in such situation. DDS is a Look-up Table (LUT) based technique to generate analog waveform using stored digital samples [1]. The LUT contains digital data of a sinusoidal wave form. A sinusoid is synthesized when the LUT containing digital data is scanned and delivered to the input of a Digital to Analog Converter (DAC). This paper describes the implementation details of DDS technique on FPGA platform. Similar implementations in different platforms like digital signal processors [2] are available, however implementations based on FPGA offers many fold advantages over others. FPGA, due to its reconfigurable feature, is proving to be the most popular target technology to implement prototypes and to test newer algorithms [3]. A VHDL program for ROM is developed with defined set of data required to make sine LUT. The VHDL program utilizes the embedded RAM called Block RAM (BRAM) of the Xilinx Spartan-3 FPGA
(Device XC3S400) to model the ROM. Without embedded memory, modeling of RAM/ROM may consume a significant portion of FPGA logic resource (LUTs). The program is downloaded on FPGA using Xilinx ISE. An 8bit DAC (DAC 0808) is used to convert the samples into a sinusoid. DDS finds application in the area of communication, underwater signal processing, control, music synthesis, instrumentation etc.
DOP
DO [7:0]
DI [7:0] DIP
Fig. 1: Block diagram of Single Port BRAM of size 2K X 8 bit
NCC 2009, January 16-18, IIT Guwahati Table 1 lists all the interface signals of a single port BRAM, their designation and direction of signal flow. Table 1: Single Port BRAM Interface Signals Signal Description Data Input Bus Parity Data Input Bus Data Output Bus Parity Data Output Address Bus Write Enable Clock Enable Synchronous Set/Rest Clock
Designation DI DIP DO DOP ADDR WE EN SSR CLK
Direction Input Input Output Output Input Input Input Input Input
346 scaled to suit design requirement to maximize the synthesizer's output dynamic range. In this experiment an 8-bit digital to analog converter, DAC 0808 is used. In order to keep its output span in positive side between 0V to 5V, (1) need to be modified as follows:
LUT ( n ) =
A A 2Π + ∗ sin ∗i 2 2 L
(5 )
Using (5) we have calculated the sample values of the LUT and stored in ROM designed using VHDL. For DAC 0808, A = 25510 = FFH. The LUT calculated using (5) with L = 64 are shown in the Table 2. Table 2: Sine LUT with length, L = 64
In this paper we have utilized a 2K X 8 bit single port BRAM as LUT to store digital samples of sinusoid. The parity feature of BRAM is not used for simplicity. In our present experiment maximum LUT length is chosen to be 64. But for high-speed DAC, LUT length of 2K is justified. III. SINE LOOK-UP TABLE An LUT is a set of memory locations which contains some precalculated value. The memory locations of a sine LUT store binary value which are calculated using the following relation at different angle θ
LUT ( n ) = A ∗ sin θ
(1 )
where n is memory word length used for LUT and determines the resolution of the synthesizer. The angular resolution ∆θ for an LUT with memory words equal to L is given by [2]
∆θ = θ(i) − θ(i − 1) =
2Π L
( 2)
where i varies from 0 to L-1. When input clock frequency is fixed, varying L produces sinusoid of different frequency. Angle θ at any sample instance can be expressed as
θ(i) = ∆θ ∗ i
(3)
Substituting θ(i) into (1), we get
LUT ( n ) = A ∗ sin
2Π ∗i L
(4)
As n and bit size of DAC is fixed for an experimental setup, the resolution can be varied by changing L. The amplitude of output waveform depends on ‘A’ of (1). ‘A’ can be selected and
Sl. No. 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Address (Hex) 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F
LUT Data (Hex) 80 8B 99 A5 B1 BC C7 D1 DA E2 EA F0 F6 F9 FD FE FF FE FD F9 F6 F0 EA E2 DA D1 C7 BC B1 A5 99 8B
Sl. No. 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
Address (Hex) 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F
LUT Data (Hex) 80 73 67 5A 4F 43 39 2F 26 1D 16 0F 0A 06 03 01 00 01 03 06 01 0F 16 1D 26 2F 39 44 4F 5B 67 73
NCC 2009, January 16-18, IIT Guwahati IV. VHDL MODEL OF ROM A VHDL program for modeling the 64 X 8 bit ROM using BRAM of Xilinx Spartan-3 FPGA is described in the form of flow chart in Fig. 2. This model also includes a 6-bit counter required to generate the addresses for reading the ROM. Provision for resetting the counter is also provided. As the counter progresses, the ROM sends the stored data one after another to the input of DAC 0808. The speed of data delivery is dependent on the clock speed of the counter and ROM. In order to ensure distortion free sinusoid at the output of the DAC, clock speed should not be higher than a limiting value that causes DAC output to exceed its slew rate. In the program, ADDR is actually an intermediate vector signal, but declared as inout port [5] in the entity so that address supplied to ROM for reading purpose can be observed in the timing diagram. Start Declare entity as CLK and RESET as input port; ADDR[5:0] as inout and DATA_OUT as output port Declare ADD[5:0] as intermediate signal Read CLK and RESET
addresses are shown in Fig. 3(b). ADDR gets incremented with each positive edge of the clock and the contents of the corresponding ROM location is retrieved and delivered to the output at DATA_OUT. Fig. 3(a) also shows the effect of making RESET = 1. VI. EXPERIMENTAL RESULT The experimental results in the form of voltage waveforms are obtained at the output of the DAC. These waveforms are observed and measured using a Digital Storage Oscilloscope (DSO) and are shown in Fig. 4(a) and (b). As evident from (5), the memory requirement increases with the length of the LUT (L). Increasing L causes increased number of digital samples and the time required to read the LUTs will also be increased. As a result the output sinusoid frequency will decrease. The system is tuned to different sinusoidal frequency by varying L. This feature of DDS can be used to generate different types of modulated signals like Amplitude Shift Keying (ASK), Binary Phase Shift Keying (BPSK), Quadrature Phase Shift Keying (QPSK) etc [6] without involving into complexity of generation of varying frequency sinusoid. Fig. 4(a) shows a sinusoid with frequency 2.5 KHz obtained using L= 64. Similarly Fig. 4(b) is obtained retrieving the alternate sample values from the LUT. Thus effective length of LUT in this case is 32 and the corresponding sinusoid frequency is 5 KHz. The sinusoid frequency f is equal to fclk/L, where fclk is the clock frequency with which the FPGA works.
Yes
Is RESET= 1? No
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VII. FPGA IMPLEMENTATION Clear flip-flops of counter
ADD = ADDR + 1 No Is CLK event? Yes ADDR = ADD RAM 16_S9_inst Send DATA_OUT[7:0] to DAC input
The VHDL program is downloaded on Xilinx Spartan-3 (device XC3S400) FPGA chip using Xilinx ISE tool. The BRAM, inside FPGA is initialized with requisite data during this period of time. The device utilization report of the said model is presented in Table 4. Table 4: Device Utilization Report Sl. No. 1 2 3 4 5 6
Description
Resources used
Number of Slices Number of Slice Flip Flops Number of 4 input LUTs Number of bonded IOBs Number of BRAM Number of GCLKs
4 out of 3584 6 out of 7168 6 out of 7168 15 out of 141 1 out of 16 1 out of 8
% Used 0.11% 0.08% 0.08% 10.64% 6.25% 12.50%
Fig. 2: Flow chart for modeling a 64X8 bit ROM using BRAM V. SIMULATION RESULT The simulation result of the VHDL model of ROM including the address generator is presented in Fig. 3(a) and (b) in the form of timing diagram obtained using ModelSim XE-III. Fig. 3(a) shows generation of ROM addresses from 00H to 1FH while rest
The estimated power consumption of the FPGA based ROM and the address generator together is found to be 245mW using Xilinx XPower Software. Table 4 and power data suggest that the area occupancy and power consumption of the device is very low. As a result it can be easily integrated with other circuitry required in the transmitter section of a communication system.
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Fig. 3(a): Simulation waveform with ROM address (ADDR) between 00-1FH
Fig. 3(b): Simulation waveform with ROM address (ADDR) between 20-3FH VIII. CONCLUSION
Fig. 4(a): Sinusoid with L= 64 (f = 2.5 KHz)
In this paper we have described the Direct Digital Synthesis technique to generate good quality (distortion free) sinusoidal waveform. The technique is implemented and tested on FPGA kit in the laboratory environment using VHDL. The ROM required for construction of LUT is made by embedded RAM of FPGA (BRAM). The use of BRAM for this purpose makes the design more compact as far as utilization of FPGA logic resources and power consumption is concerned. The prototype may be used to generate high frequency sinusoid using DAC with better slew rate. REFERENCES [1] [2]
[3]
[4]
Fig. 4(b): Sinusoid with L= 32 (f = 5 KHz)
[5] [6]
J.Tierney, C.M.Rader, and B.Gold, "A digital frequency synthesizer," IEEE Trans. on Audio Electroacoustics, vol. AU-19, pp. 48-57, 1971. S.S.Prasad and S.K.Sanyal, "A Novel Direct Digital Synthesis Technique to Generate Low Frequency Acoustic Signal for Underwater Signal Processing using Digital Signal Processor," in Proc. of Symposium on Ocean Electronics- 2005,Cochin, India, pp. 170-175, Dec 2005. J. Rose, A. El Gamal, & A. Sangiovannic-Vincentelli, “Architecture of Field Programmable Gate Array,” Proceedings of IEEE, Vol. 81, no. 7, pp. 1013-1029, July, 1993. Spartan-3 FPGA Family: Complete Data Sheet, Xilinx Corporation, 2006, available at www.xilinx.com. Douglas L. Perry, VHDL: Programming by Example, Tata McGrawHill, New Delhi, 2002. B. Sklar, Digital Communications: Fundamental and Applications, 2/e, Pearson Education, New Delhi, 2001.
