multiplication. This paper focusing on design of Modified Booth. Multiplier which performs both signed and unsigned multiplication. Here used Carry Select ...
2015 Online International Conference on Green Engineering and Technologies (IC-GET)
Design and Implementation of 16x16 Modified Booth Multiplier Manjunath,Venama Harikiran,Kopparapu Manikanta,Sivanantham S*, Sivasankaran K School of Electronics Engineering, VIT University, Vellore, India
Abstract— The Modified Booth multiplier is attractive to many multimedia and digital signal processing systems. This paper presents the design of 16*16 Modified Booth multiplier .The multipliers such as Braun array multiplier and Array multiplier are used for unsigned multiplication. This paper focusing on design of Modified Booth Multiplier which performs both signed and unsigned multiplication. Here used Carry Select Adder it increases the speed of multiplier operation. Booth encoder multiplier with Carry select Adder utilizes the minimum hardware, reduced chip area, low power dissipation and reduced the cost of the system.
select adders have been considered as a compromise solution between RCAs & CLAs because they offer a good tradeoff between the compact area of RCAs and the short delays of CLAs. II. MODIFIED BOOTH MULTIPLIER Modified Booth Multiplier is used to reduce the number of partial products compare to basic booth multiplier. Modified Booth Multiplier performs both signed and unsigned multiplications. Signed numbers are represented in 2’s complement form consider two N-bit numbers X and Y.
Keywords— Modified Booth encoder, Booth decode, Wallace tree
I.
N −2
INTRODUCTION
X = − x N −1 2 N − 1 +
In most high speed Digital Signal Processing (DSP) and multimedia applications, the multiplier [1] plays an important role because it dominates the chip power consumption and operation speed. In many Digital Signal Processing application (DSP) and multimedia application the output data has directed bearing to the accumulation of a series of products over a single multiplication operation. In those cases, truncation errors result in large output error, which can be countered by performing additional compensation, which is again dependent on different applications needs different compensation.
(1)
i ∗2i
i =0
N −2
Y = − y N −1 2 N − 1 +
∑y
(2)
i∗2i
i =0
Xi and Yi denotes the ith bit of the multiplicand and multiplier respectively. In this paper both X and Y is 16 bits. If Negative Number taken than it is represented in 2’s complement and if Positive Number given it will keep as it is. Here MSB bit represents the Sign of the Number Result of 16*16 Booth multiplication is of 31 bits; Bit P[31] represents the Sign of the Result.
Any multiplier can be divided into three stages: Partial products generation stage, partial products addition stage, and the final addition stage. The speed of multiplication [2] can be increased by reducing the number of partial products. Many high-performance algorithms and architectures have been proposed to accelerate multiplication. Various multiplication algorithms such as Booth, Modified Booth, Braun, and BaughWoolley have been proposed. The modified Booth algorithm [3] reduces the number of partial products to be generated and is known as the fastest multiplication algorithm. Wallace Tree Carry Save Adder structures have been used to sum the partial products in reduced time. Our goal is to reduce computation time by using Booth's algorithm for multiplication and to reduce chip area by using Carry Save Adders arranged in a Wallace tree Structure. In the last stages the two-row outputs of the tree are added using any high-speed adder .Ripple Carry Adder (RCAs) have the most compact design among all types of adders. Carry Look Ahead Adders (CLAs) are the fastest adders, but they are worst from the area point of view. Carry
978-1-4673-8625-8
∑X
TABLE I.
MODIFIED BOOTH ENCODING TECHNIQUE
0
TWO i 0
ONE i 0
0
0
1
X
0
0
1
Xj
0
1
0
Xj-1
Xi+1
Xi
Xi-1
0
0
0
ACTI ON 0
0
0
1
X
0
1
0
NEG
Pij 0 Xj
0
1
1
2X
1
0
0
-2X
1
1
0
Xj-1
1
0
1
-X
1
0
1
XJ
1
1
0
-X
1
0
1
Xj
1
0
0
0
0
0
1
1
The modified encoded table is realized as shown in the TABLE-1. The three bits of multiplier are scanned once and based on it negi, twoi, onei, zeroi and bits are calculated where 0 ≤ i ≤ (N/2-1). neg bit is used to indicate the multiplicand is
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2015 Online International Conference on Green Engineering and Technologies (IC-GET) multiplied with negative weight. zeroi indicates the zero needs to be set as partial product. One shows the multiplicand can be used directly and twoi the multiplicand has to be left shifted. III. BOOTH ENCODER Booths algorithm involves encoding of multiplier bits and partial product generation as shown in Fig 2. Different modified booths algorithms have been proposed according to how many number of bits are used to encode multiplier. Modified booth algorithm [4] reduces the number of partial products [5]. Radix 2, radix 4, radix 8 [6], radix 16, radix 32 are the different modified booth algorithms. NxN bit multiplication involves N partial products but modified Radix 2r produces N/r partial [7] [8] [9]. In the proposed modified Radix -4 Booth Algorithm, multiplier has been divided in groups of 3 bits and is the error bias that needs to be added to the partial product matrix. Each group of 3 bits have been considered according to modified Booth Algorithm for generation of partial products 0, ±1A, and ±2A. In first group, first bit is taken zero and other bits are least significant two bit of multiplier operand. In second group, first bit is most significant bit of first group and other bits are next two bit of multiplier operand. In third group, first bit is most significant bit of second group and other bits are next two bit of multiplier operand. This process is carried on. Partial product is generated using multiplicand operand A. For n bit multiplier there is n/2 or [n/2 + 1] groups and partial products .for 16X16 bit multiplication 8 partial products are generated. So it reduces the number of partial products in comparison to Booth algorithm (radix-2) improves the computational efficiency of multiplier, reduce the calculation delay. The Bits generated
Fig. 2. Modified Booth Encoder and Decoder Logic Diagram
The Bits generated from Modified Booth Encoder fed to the partial product generator and partial product generates the partial product PPI for each triplet The Table 2 shows the 7 partial
from Modified Booth Encoder fed to the partial product generator and partial product generates the partial product PPI for each triplet
products results P00[i] to P7[i]. The numbers in the above table represents the bit positions of the partial products. And P[i] is the final Product from P[0] to P[15]. Similarly The table 3 Shows the remaining bits of Partial products and Final Product Bits from P[16] to P[30].In table ∆ represents the sign Extension of the Corresponding Partial Products .By adding all Partial products bits in the column wise will get final product result. IV. WALLACE TREE STRCTURE Wallace Tree Structure can be made by using compressors, full adders and various other techniques. But in this paper the structure is made of unit adders instead of full adders as shown in Fig 4. The unit adders or carry save adders reduce the number of partial products and sum rows. The carry save adder increases the speed of Booth Multiplier structure. As in this the partial products are added sequentially. In this A+B+C+D= (A+B) + (C+D). That is A and B, C and D are added in parallel. And then they are added together. They require only two full adder delays whereas A+B+C+D require three full adder delays.
Fig. 1. Partial Product Generator Logic
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2015 Online International Conference on Green Engineering and Technologies (IC-GET)
TABLE II.
15
14
MODIFIED PARTIAL PRODUCT MATRIX-LOWER 16-BIT RESULT OF (P[0]-P[15])
13
12
10
9
8
7
6
5
4
3
2 1
13
12
11
10
9
8
7
6
5
4
3
2
11
10
9
8
7
6
5
4
3
2
1
0
9
8
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
5
4
3
2
1
0
3
2
1
0
1
0
15
14
1
0
0
P00[i] P01[i] P02[i] P03[i] P04[i] P05[i] P06[i] P7[i]
13
12
11
10
9
8
7
6
5
4
3
2
1
P[i]
MODIFIED PARTIAL PRODUCT MATRIX-REMAINING 16-BIT RESULT OF (P[16]-P[30])
TABLE III. 15
14
13
12
11
10
9
8
7
6
5
4
3
2
13
12
11
10
9
8
7
6
5
4
3
2
1
0
11
10
9
8
7
6
5
4
3
2
1
0
9
8
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
5
4
3
2
1
0
3
2
1
0
1
0
15
14
1
0
P00[i] P01[i] P02[i] P03[i] P04[i] P05[i] P06[i] P7[i]
13
12
11
10
9
8
7
68
6
5
4
3
2
1
0
P[i]
2015 Online International Conference on Green Engineering and Technologies (IC-GET) Wallace tree is a summation method and it used in conjunction with fixed-width booth multiplier to increase the computation speed. The Wallace tree algorithm to compute 16x16 multiplier.
Fig. 4. Wallace Tree Multiplier
V. RESULTS & CONCLUSION The modified booth multiplier has been designed and verified by simulation. The multiplication results shown in table 4. This multiplier design is synthesized using Cadence RTL Complier. TABLE IV.
RESULT OF 16X16 MULTIPLICATION
X
Y
P
3
3
9
3083
3083
3585529
-4093
-4093
-1976919
-1989
-1989
34252577
REFERENCES [1]
[2] [3]
[4] [5] Fig. 3. RTL view of Wallace Tree Multiplier [6]
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Ramya Muralidharan, Chip-Hong Chang,” Radix-4 and Radix-8 Booth Encoded Multi-Modulus Multipliers”, IEEE Trans on Circuits And System,vol. 60(11), Nov 2013. MacSorley O.L, “High speed arithmetic in binary computers,” Int Proc. IRE, vol. 49, pp 67-69, Jan 1961. Jiun-Ping Wang, Shiann-Rong Kuang,Shish-Chang Liang, “High-Accuracy Fixed-Width Modified Booth Multipliers for Lossy Applications” IEEE Transaction on VLSI system, vol. 19 (1), Jan 2011. MacSorley O.L, “High speed arithmetic in binary computers,” Int Proc. IRE, vol. 49, pp 67-69, Jan 1961. Sivanantham, S. “Design of low power floating point multiplier with reduced switching activity in deep submicron technology,” Int J of Applied Engineering Research, 8 (7), pp. 851-859. 2013. Praveen Kumar, M.V., Sivanantham, S., Balamurugan, S., Mallick, P.S.“Low power reconfigurable multiplier with reordering of partial products,” Int Conf on Signal Processing, Communication, Computing and Networking Technologies, ICSCCN-2011, pp. 532-536.
2015 Online International Conference on Green Engineering and Technologies (IC-GET) S. Sivanantham, K. Jagannadha Naidu, S. Balamurugan, D. Bhuvana Phaneendra,“Low power floating point computation sharing multiplier for signal processing applications,” Int J of Engineering and Technology, 5 (2), pp. 979-985. 2013 [8] A. Rakesh Babu, R. Saikiran, S. Sivanantham, “Design of floating point multiplier for signal processing applications,” Int J of Applied Engineering Research, 8 (6), pp. 715-722. 2013 [9] Honglan Jiang, Jie Han, Fei Qiao,Fabrizio Lombardi,”Approximate Radix-8 Booth Multipliers for LowPower and High-Performance Operation”, IEEE Transac on Computers,pp 1-1,vol.99,2015. [7]
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