Design and Implementation of DVB-S2 Transport Stream for Onboard Processing Satellite Rangwani Varsha*1, Rajat Arora#2, TVS RAM#3, Amit Patel*4 *Chandubhai. S. Patel Institute of Technology CHARUSAT University, Gujarat, India 1 4
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[email protected] [email protected]
Onboard Signal Processing Division, Space Applications Centre (SAC) Ahmedabad, Gujarat, India-380015 2
[email protected] 3
[email protected]
Abstract— Digital Video Broadcasting (DVB-S2) is a digital television broadcast standard which is introduced as a successor for the DVB-S system. This standard is compatible with multiple input protocols (IP, MPEG-2, MPEG-4) which are either encapsulated in transport stream or generic stream. This encapsulation feature makes it possible to support voice, video as well as data known as the triple play. This protocol is also an open standard, which leads to interoperability among different service providers. This protocol is highly suitable for on-board processing satellite as different class of users can be serviced through a single system as well as low cost ground receiver are available. The design described here implements DVB-S2 frame structure for transport stream, single input with constant code rate of 1/2 and QPSK modulation, with a roll-off of 0.20. A Xilinx Virtex®-5 FPGA is used to implement this design as this FPGA is also available in radiation tolerant version. Keywords-ACM,DVB-S2, FPGA,MODCOD,RRC.
I. INTRODUCTION Today, the new market demands for HDTV/3DTV (large Bandwidth) and IPTV (more traffic) is spreading rapidly. There is need for better compression and framing protocols. Optimized channel coding and modulation schemes are required that utilizes bandwidth efficiently which is a highly scarce resource for satellite based communication system. Here, one Solution emerges that satisfies all these demands i.e. DVB-S2 protocol [1] which is introduced as a successor of DVB-S protocol for satellite broadcasting. The main DVB-S2 feature is its adaptive air interface, where coding and modulation techniques are flexibly varied to maximize performance and coverage. This document addresses the design of the entire DVB-S2 protocol for downlink, considering practical challenges for baseband framing, coding and modulation. DVB-S2 standard defines downlink protocol for satellite video broadcasting and interactive services [1]. It covers data link layer and physical layer implementation of OSI model. This paper presents a physical layer implementation of this protocol.
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DVB-S used motion picture expert group-2 transport stream (MPEG-2 TS) format for video transmission and had fixed coding and modulation scheme. All video and data used to be encapsulated in Transport Stream. MPEG-2 has fixed packet size of 188 bytes. For IP data, the overhead due to TS and MPE was typically 5 to 15% [2]. DVB-S2 introduces a new flexible generic stream encapsulation [2] which can be a packetized stream of variable length or continuous bit stream. It is compatible with any type of data (MPEG-2, MPEG-4, IP, ATM etc.).It doesn't need transport stream overhead. DVB-S2 introduces the concept of variable coding and modulation (VCM) and Adaptive coding and modulation (ACM). In VCM different receivers can work on different modulation and coding schemes depending on their location, whereas in ACM modulation and coding scheme can change on frame by frame basis based on channel conditions. This feature optimizes transponder resources under varying conditions, such as rain fade and geographically diverse locations. It also can be made to work on a fixed modulation and coding schemes considering worst case scenarios, which is called constant coding and modulation (CCM) [1]. Analysis of the bandwidth efficiency of DVB-S2 in a typical data distribution network by Dirk Breynaert, and Maximilien d’Oreye de Lantremange, Newtec in 2005 [3] , shows that DVB-S2 allows an increase of satellite transmission capacity of 29% for CCM, 66% for VCM and 130% for ACM. For implementation of ACM mode, the physical layer needs to be adaptive. There are many algorithm proposed for physical layer selection, that is selecting from available MODCODs for optimized performance. The study of BER for various MODCODS is shown by B. Azarbad in 2011 [4] which can be used for Estimating correct MODCOD for ACM. Another Study carried by INTECH presents a DVBS2 MATLAB model, its issues and impairments. It also proposes an algorithm for ACM mode. ACM algorithm included in this model is based on the standard required Es/No by ETSI to support a Quasi Error Free transmission.
It depicts that for all MODCOD there is a required level of Es/No. To make decisions among MODCODs threshold offsets are provided as equidistance thresholds between adjacent MODCODs. The SNR of received signal at the receiver will be sent to ACM block to be used for next frame mode of transmission [5]. The DVB-S2 standard specifies the physical layer as well as the interfaces with higher layer and the carriage of broadcast services [1]. The Adaptive Physical layer implementation guidelines is been presented and its performance is evaluated by GIANNI ALBERTAZZI in 2005[6]. The entire DVB-S2 transmission chain has been simulated using a purposefully developed C++ software tool. This paper, presents a detail design of FPGA implementation of entire physical layer implementation of DVB-S2 frame structure for a transport stream input for a single MODCOD fully compatible with the ETSI standard. The design presented here can be easily upgraded to implement multiple MODCOD to achieve an Adaptive physical layer. II.
DVB-S2 STANDARD
Figure.1 shows a functional block diagram of DVB-S2 System as given by ETSI Standard for Downlink [1]. DVB-S2 standard specifies two levels of framing: baseband framing and physical layer framing. The system designed gets encapsulated transport stream as input. As specified by the ETSI standard baseband frame structure is implemented along with baseband header insertion. For CCM and single input TS, mode adaptation shall consist of input interface and Cyclic Redundancy Check (CRC-8) coding. A baseband header is appended before the data field, which notifies the receiver of the input stream format and mode adaptation type. The stream adaptation is applied to provide padding to complete a Base-Band Frame and Base-Band Scrambling. After Baseband framing the frame is scrambled so that long 1’s and 0’s are removed from the frame, which is then followed by FEC Encoder. Encoding shall be carried out by the concatenation of BCH (Bose Chaudhuri Hocquenghem) outer codes and LDPC (Low Density Parity Check) inner codes (rates 1/4, 1/3, 2/5, 1/2, 3/5, 2/3, 3/4, 4/5, 5/6, 8/9, 9/10). Depending on the application area, the FEC coded block shall have length of 64 800 bits or 16 200 bits. The resultant frame is called FECFRAME .When VCM and ACM is used, FEC and modulation mode may be changed in different frames, but remains constant within a frame. Bit interleaving shall be applied to FEC coded bits for 8PSK, 16APSK and 32APSK. Then the system implements bit mapping and a complex frame of form I + jQ is created. Each FECFRAME (which is a sequence of 64800 bits for normal FECFRAME, or 16200 bits for short FECFRAME), is serial-to-parallel converted (ηMOD = 2 for QPSK, 3 for 8PSK, 4 for 16APSK, 5 for 32APSK) the MSB of the FECFRAME is mapped into the MSB of the first parallel sequence. Each parallel sequence shall be mapped into constellation, generating a (I, Q) frame
Figure 1 Functional Block Diagram of DVB-S2 System [1]
of variable length depending on the selected modulation efficiency ηMOD. The input to this block is FECFRAME and output is a complex frame called XFECFRAME. BitMapping into QPSK, 8PSK, 16APSK and 32APSK constellations can be applied, depending on the application area. Finally the system goes through second level of framing and scrambling called the physical layer. The System provides a regular physical layer framing structure, based on SLOTs of M = 90 modulated symbols, allowing reliable receiver synchronization on the FEC block structure. A slot is devoted to physical layer signalling, including Start-of-Frame delimitation and transmission mode definition. The physical layer framing sub-system generates a physical layer frame (named PLFRAME) by performing the following processes: 1. Dummy PLFRAME [1] generation when no XFECFRAME is ready to be processed and transmitted. 2. XFECFRAME slicing into an integer number (S) of constant length SLOTs (length: M = 90 symbols each). Number of slots S depends on Modulation scheme. 3. PLHEADER generation and insertion before the XFECFRAME for receiver configuration. PLHEADER occupies exactly one SLOT (length: M = 90 Symbols). 4. Pilot Block insertion (for modes requiring pilots) every 16 SLOTS, to help receiver synchronization. The Pilot Block shall be composed of P = 36 pilot symbols. 5. Randomization of the (I, Q) modulated symbols by means of a physical layer scrambler.
The input stream of the sub-system shall be a FECFRAME and the output a scrambled PLFRAME. This mechanism is suitable also for VCM and ACM modes. Carrier recovery in the receivers may be facilitated by the insertion of a regular raster of pilot symbols (P = 36 pilot symbols every 16 SLOTs of 90 symbols), while a pilot-less transmission mode is also available, offering an additional 2, 4 % useful capacity.After framing the stream goes through Root-raised Cosine Filter (RRC) to avoid Inter symbol interference (ISI).The standard supports three different roll-off factors 0.20, 0.25 and 0.35 which can also vary on frame-by-frame basis. III. DESIGN OVERVIEW
B. Baseband Framing As shown in Figure.13, this module reads from both FIFOdata and FIFO-Crc, to create data field of length DFL=kbch80, generates 80 bits of header which contains Matype-1, Matype-2, UPL, DFL, SYNC, Syncd, and crc of header. Syncd Field specifies the number of bits after which a new packets starts from the beginning of data field. When data field length (DFL) is integral multiple of User packet length (UPL) the value for syncd filed is 0000 hex. The Baseband header called the “BBHEADER” is appended to data field and a baseband frame is formed. The resulted frame is buffered in a FIFO. Figure.5 depicts hardware result for generated baseband header and user packets.
This design implements digital framing and encoding as described by the protocol [1] in Xilinx Virtex®-5 FPGA. Figure.13 Shows the Architectural block diagram of DVBS2 framing for transport Stream. The entire design is divided into 8 functional blocks as described below: A. Input interface and CRC The input to this block is serial data coming from demodulator/Input Switch. The Input data rate i.e. clk_Ext is different from system clock clk. Figure 2 shows the circuit used for synchronization, it generates an enable signal which is used to sample input data on system clock.
Figure 2 Synchronizer
Synchronized data is then packetized into user packets of length UPL (188 bytes for transport Stream). This block converts input data stream into transport stream user packets (UP) of 188 bytes. The transport stream starts with a Sync byte (47hex) which is detected by the unique word detection block as shown in Figure.13. The rest of the 187 bytes of data is packetized and buffered. Then CRC is calculated for each User packet (UP) and Buffers the UP as well its CRC. The computed CRC-8 shall replace the syncbyte of the next UP as shown in Figure 3.The hardware result of CRC of a user packet is shown in figure 4.
Figure 5 FPGA result of Baseband Header
C. Stream Adaptation In this block baseband frame size is made equal to Kbch as that is input requirement for FEC encoder. The frame size is determined from code rate which is fixed for CCM. This block performs Padding and Scrambling. For transport stream zero padding is not needed as DFL = Kbch-80. Hence baseband frame size is already equal to Kbch. The scrambling sequence generated by the feed-back shift register. The polynomial for the Pseudo Random Binary Sequence (PRBS) generator is: 1+X14 +X15. Loading of the initialization sequence into the PRBS register, is initiated at the start of every BBFRAME. The input to this scrambler is from baseband frame buffer which also converts the frame from 8-bit parallel to serial. The scrambled serial stream of BBFRAME is verified through descrambler. The descrambler output matches the serial Baseband frame obtained before scrambling, as shown in Figure.6.
Figure 3 CRC-8 Implementation
Figure 6 Baseband Descrambling Figure 4 FPGA result for CRC of a User Packet
D. FEC Encoder XILINX IPCORE – DVB-S.2 FEC Encoder [7] is used to implement this block.
Figure 7 FEC Encoder
This sub-system performs outer coding (BCH), Inner Coding (LDPC) and Bit interleaving. Each BBFRAME (Kbch bits) is processed by the FEC coding subsystem, to generate a FECFRAME (nldpc bits). The core provides with controls signals like ND and RFD for Handshaking with previous block. The Core asserts RFD signal when it is ready for input data. On receiving RFD the Baseband frame buffer (FIFO_out) is read-out by the scrambler and ND signal is asserted by the scrambler when valid scrambled data is available for the encoder. The core also provides with control signals like RDY (Ready) and CTS (Clear to Send). The core asserts RDY when FECFRAME is ready. The FECFRAME is buffered by the core until it receives CTS Signal. E. Bit mapping QPSK bit mapping is implemented as per standard [1]. Hence every two bit has to be represented by 1 symbol. The FECFRAME is a sequence of bits. It is to be converted into bunch of 2 bits by serial to parallel block. Each bunch of 2 bits needs to be mapped to a complex number. For QPSK, the I component is MSB and Q component is LSB. The I and Q components are buffered in FIFO_I and FIFO_Q respectively as shown in Figure.13. Figure.8 shows the simulink verified constellation diagram of the resultant PLFRAME
Figure 8 Baseband Constellation of QPSK
F. Physical layer framing This module performs second level of framing after bit mapping. The frame generated is called PLFRAME. This frame consists of header and slots of data. Each slot contains 90 symbols. It generates PLHEADER of one slot as specified by the DVB-S2 protocol [1]. PLHEADER will contain a Start Of frame Field (SOF) which is used to detect
DVB-S2 frame on receiver side. SOF consists of 26 symbols. SOF is followed by a plscode which consists of 7 bits of MODCOD (5 bits) and Type (2 bits) field. These 7 bits are linear block coded into 64 bits and scrambled as specified by the protocol [1]. Header goes through BPSK modulation. After generating header this module appends 360 slots of QPSK modulated data which is read from FIFO_I and FIFO_Q as shown in Figure.13. If a frame is not available from buffers then dummy frame is send. Dummy frame consist of 36 slots of un-modulated carrier. Header of dummy frame is also BPSK modulated. G. Physical layer scrambling Prior to modulation, each PLFRAME, excluding the PLHEADER, shall be randomized for energy dispersal by multiplying the (I + jQ) samples by a complex randomization sequence (CI + jCQ) [1]: ISCRAMBLED = [I CI - Q CQ]
(1)
QSCRAMBLED = (I CQ + Q CI) (2) The randomization sequence rate corresponds to the I-Q PLFRAME symbol rate, thus it has no impact on the occupied signal bandwidth. The randomization sequence is reinitialized at the end of each PLHEADER. The scrambling code sequences is constructed by combining two real msequences (generated by means of two generator polynomials of degree 18) into a complex sequence. The resulting sequences thus constitute segments of a set of Gold sequences. Figure.9 shows the implementation of PLSCRAMBLER. The scrambler generates Rn sequence for broadcast mode as per standard. Iscrambled and Qscrambled are obtained from Rn using a look-up table described by the standard.
Figure 9 Physical Layer Scrambler
Physical layer scrambling is enabled at the beginning of each PLFRAME excluding PLHEADER. The state machine, as shown in Figure.13 enables PLFRAME when a useful frame is ready else it enables the dummy frame. H. RRC Filter This module is a square-root raised cosine filter in order to avoid inter-symbol-interference.RRC filter is designed using
a MATLAB's FDATOOL [8]. The table below shows the parameters used to design the filter. Table I FDATOOL Parameters
Type order window Fs Fc Roll-off factor
Raised Cosine 20 Hamming 64MHz 16MHz 0.20
FDATOOL provides filter coefficients which are then normalized and scaled. These coefficients are then rounded to integer values and are used to implement FIR structure in Xilinx Virtex-5 FPGA. Figure.10 shows the impulse response of the filter.
Figure 10 RRC filter impulse response
The input to this block is PLFRAME including PLHEADER. This PLFRAME is up-sampled and passed through the RRC filter designed in FPGA using above coefficients. Figure.11 shows, the time domain result of RRC of I component of PLFRAME captured on logic analyzer.
Figure 12 Output Spectrum of DVB-S2 frame
IV. CONCLUSION This system implements DVB-S2 frame structure as given by ETSI EN 302307 Standard in a Xilinx Virtex-5 FPGA. It performs baseband framing along with scrambling. The system implements FEC encoder using Xilinx IPCORE. The IPCORE encodes Baseband Frame with 1/2 code rate and FECFRAME is generated which is verified by DVB-S2 Simulink model. The system performs QPSK Bit mapping on FECFRAME and desired constellation is observed using Simulink. This frame then undergoes Second level of Framing and scrambling called the physical layer framing. The resulting frame is passed through RRC filter and a rolloff of 20% is observed in its spectrum. The resultant frame is captured by Logic Analyzer which verifies the DVB-S2 frame structure. This design can be easily upgraded for generic stream inputs. Depending on ACM command, modulation schemes and coding rate can be changed on frame-by-frame basis. REFERENCES [1]
[2] [3] [4] [5] [6]
Figure 11 FPGA result of RRC Filter
The result of Entire DVB-S2 frame implemented in FPGA is captured using Logic Analyzer. The bandwidth of this resultant frame is verified with a spectrum analyser in Simulink [9]. Figure.12 shows the spectrum of Filtered Output. The bandwidth of the resultant signal is 19.2 MHz as observed in the spectrum shown in Figure.12.
[7] [8] [9]
ETSI 302307 (V1.2.1), "Digital Video Broadcasting (DVB); Second generation framing structure, channel coding and modulation systems for Broadcasting, Interactive Services, News Gathering and other broadband satellite applications (DVB-S2)”, 2009. ETSI 102606 (V1.1.1), “Digital Video Broadcasting (DVB); Generic Stream Encapsulation (GSE) Protocol”, 2007. Dirk Breynaert, Maximilien d’Oreye de Lantremange, “Analysis of the bandwidth efficiency of DVB-S2 in a typical data distribution network”, Newtec, 2005. B. Azarbad, A. Sali, “Study Of BER In DVB-S2 Satellite Implemented in Matlab”, International Conference on Space Science and Communication (IconSpace). Penang, IEEE, 2011. Bahman Azarbad, “A DVB-S2 MATLAB model, its issues and impairments”, INTECH, 2012. GIANNI ALBERTAZZI, “On the adaptive dvb-s2 physical layer: design and performance” Wireless communication. IEEE, 2005. Xilinx,” LogiCORE IP DVB-S.2 FEC Encoder v2.0 – DS505”, 2009. Sreevidya N, H C Sateeshkumar, “SRRC Filter Implementation As Per DVB-S2 Standard”, IJIRD Vol 2. No. 5, May-2013. Richardo A. Losada, “Digital Filters With Matlab”, The Mathworks Inc., May 18, 2008.
Figure 13 Implementation Block Diagram
