Design and Implementation of Forward Error Correction in Software ...

2011 International Conference on Multimedia, Signal Processing and Communication Technologies

Design and Implementation of Forward Error Correction in Software Defined Radio on a Model Based Development Platform Rehan Muzammil, M. Salim Beg

Mohsin M. Jamali

Dept. of Electronics Engineering, Aligarh Muslim University, Aligarh, India [email protected], [email protected]

Dept. of Elect. Engg. & Comp. Sc. The Univ. of Toledo, Toledo, Ohio, USA [email protected] input audio signal. The motivation behind the use of Block Coder in this work is the fact that Block Codes are currently used in a number of communications systems.

Abstract—Forward Error Correction (FEC) plays an important role in today’s Digital Communications Systems. This paper describes the design and implementation of the FEC, the (8,4) Block Coder and 8x8 Interleaver in a Binary Phase Shift Keying Transceiver on a Model Based Development platform for a Software Defined Radio (SDR) system. Model Based Development is a new development process where the model of the communications systems is designed and developed in software such as Simulink / Matlab. Model Based Development process saves considerable amount of time in the form of design, implementation and testing.

II. MODEL BASED DEVELOPMENT In this work, the authors have used a Model Based Development platform which is a Small Form factor (SFF) SDR low power tunable equipment conceived and designed to be used in the development of applications in the field of SDR. It consists of three boards: RF module, Data Conversion Module, Data Processing Module. The board is illustrated in the Fig. 1. The SFF SDR platform comes with two board support packages – Board Software Development Kit (BSDK) and Model Based Development kit (MBDK). The BSDK allows users to quickly become fully functional developing C, C++, or assembly language codes for the DSP and GPP, or HDL code for the FPGA by giving users an understanding of all the platform’s major interfaces such as VPSS, audio codec, data conversion module, or RF module. Similarly, the MBDK allows users to develop applications for the platform with Simulink within MATLAB. By targeting the DSP and FPGA with MBDK tools, users can deploy and validate algorithms on the hardware more rapidly.

Keywords-FEC, FPGA, DSP, SDR.

I.

INTRODUCTION

Software Defined Radio (SDR) has the ability of changing the characteristics of a transmitting and receiving radio device without physically modifying the hardware. This implies that the coding schemes, modulation / demodulation, bandwidth and channel access schemes may be changed. Hence, such hardware is called reprogrammable or reconfigurable and this is done at the baseband stage of the radio system. An implementation of such hardware requires very high speed Digital Signal Processors (DSPs). Fortunately now such high speed processors are commercially available in the market. A number of high speed digital systems are available in the form of Field Programmable Gate Arrays (FPGAs). These FPGAs are deployed in the baseband section of the radio systems where all the processing of the data is done in digital form. Software Defined Radio are highly configurable hardware platforms that provides the technology for realization of the rapidly growing digital wireless communication infrastructure [1-12]. Many sophisticated signal processing tasks are performed in a SDR, including channel estimation, equalization, forward error correction, modulation / demodulation etc. All these tasks are performed in the baseband section of the radio receiver where the FPGAs are deployed. FPGAs have experienced a lot of innovations in the past several years. Advanced process technology has enabled the development of high density devices that are extremely well suited to the needs of the high performance real time signal processing. FPGAs are organized as an array of logic elements and programmable routing resources used to provide the connectivity between the logic elements [9].

Fig. 1. The SFF SDR platform. Unlike the SDR development platforms in the market, the SFF SDR development platform is a hybrid hardware-software system that supplies the necessary full-signal chain for multiprotocol software defined radios. By separating the base-band, IF, and RF from one another as distinct modules (rather than maintaining a single, fixed architecture), developers can extend their radio development capabilities and optimize costs and power consumption. The SFF SDR development platforms can be used to perform four types of development – FPGA, DSP, GPP, and

This paper describes novel design and implementation of the FEC used in the BPSK transceiver which consists of a (8,4) Block Coder and a 8x8 Interleaver for SDR system. The work includes the implementation of a CODEC for digitization of

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Model based (combination of the above three). This paper describes model based development using this platform, though only FPGA and DSP are exploited. The model based development saves considerable amount of time in the form of design, implementation and testing as compared to traditional design method [5].

Where, m1, m2, m3, and m4 are the 4-bits of data or message 1 2 3 1 2 3 4 . bits. The code word is given as, Another parity bit is calculated, which is the parity of these 7 1⊕ 2⊕ 3⊕ 1⊕ 2⊕ 3⊕ 4 bits, given as, Hence, the code word now becomes:

III. DESIGN OF BPSK TRANSCEIVER

Hence, now we have (8, 4) block code where 4 are the message bits and 8 is code word length. This is done with each of the eight 4-bit words and we get a 64-bit word at the output of the coder. Hence, to the 32-bit message 32 parity bits or redundant bits are added to make it 64-bit word. The coding rate is ½.

1 2 3

The BPSK or binary phase shift keying transceiver is designed and developed in Simulink / Matlab environment. It is a digital modulation scheme where the digital information is present in the phase of the carrier. The phase of zero degrees is binary ‘0’ and a phase of 180 degrees is binary ‘1’. Hence, just by observing the phase of the received waveform we can tell that the transmitted bit was ‘0’ or ‘1’. The software installed are Code Composer Studio, System Generator, Xilinx ISE, and MATLAB. All the above software is necessary for the development of the transceiver. The design of the complete BPSK transceiver including FEC is done in two parts namely DSP front-end and FPGA back-end. The DSP model is given in Fig. 2 and FPGA model is given in Fig. 3. IV.

63 55 47 39 31 23 15 7

63 62 61 60 59 58 57 56

BACK END FPGA MODEL

4,

2

2⊕

3, 3

2⊕

3⊕

60 52 44 36 28 20 12 4

59 51 43 35 27 19 11 3

58 50 42 34 26 18 10 2

57 49 41 33 25 17 9 1

56 48 40 32 24 16 8 0

55 54 53 52 51 50 49 48

47 46 45 44 43 42 41 40

39 38 37 36 35 34 33 32

31 30 29 28 27 26 25 24

23 22 21 20 19 18 17 16

15 14 13 12 11 10 9 8

7 6 5 4 3 2 1 0

From the Analog-to-Digital Converter (ADC) the receiver section starts. The ADC takes on the analog signal and converts it into digital for the processing. This digital word, sample by sample, is passed onto the demodulator / detector for detection. One bit is detected each time. This serial bit stream is passed onto the serial-to-parallel (S/P) converter for converting into a 64 bit parallel word. This 64-bit word is passed onto the de-interleaver for re-arranging the incoming bits to the original form. The 8x8 De-Interleaver is opposite to the interleaver. The rearranging is done exactly the same way as is done in the interleaver. The input to de-interleaver is according to Table 1 and output as Table 2. In general, the interleaver / deinterleaver is a must for use with block coder to prevent burst errors. The (8,4) Block Decoder takes the 64-bit word and breaks it into eight 8-bit words. First process here is to find out the parity of these eight bits. This parity is a good indication of a bit error. If there is single bit error this parity is set otherwise it is unset. If there is even bits error, this is set to ‘0’ otherwise it is set to ‘1’. The error correction is performed only when it is ascertained that there is a single bit error in this 8-bit word. Otherwise no error correction is performed. The parity is calculated as:

(1)

1⊕

61 53 45 37 29 21 13 5

Hence, we observe that the input 64-bit word is rearranged. This is passed on to the P/S converter.

The (8,4) Block Coder is the first block in the FEC chain. Here the incoming 32 bit word is broken up into 8 4-bit words. These 4-bit words are the main message bits to which the parity bit is added as follows: The parity check matrix H is given in Eqn. 1 taken from [13]. The three parity bits, p1, p2, p3 are generated according to the parity check matrix H [13].

3⊕

62 54 46 38 30 22 14 6

Table 2. The output layout of the 64–bits from interleaver

This is the model where almost all of the data processing of the transceiver is done. Here the 32 bit word is taken from the front end, passed through a block coder then an interleaver and then the Parallel to Serial Conversion (P/S) and an output bit stream is obtained. This is passed to a modulator where the modulating signal is this bit stream and the carrier is 2.5 MHz cosine wave. The output of the modulator is fed to the Digitalto-analog converter (DAC) for conversion to analog form and is passed on to the RF section where a frequency upconversion is done and the signal is transmitted at a frequency of 800 MHz which is set at the front end model as described in the previous section.

1⊕

4

The above sequence of bits is re-arranged in the interleaver block to the following sequence.

In this work the real time audio signal is converted to digital form by the audio Codec and passed to back-end for processing and then transmitted over the air at a frequency of 800 MHz and after the reception back to the front end for converting it back to real time audio.

1

3

Table 1. The input layout of the 64-bits to interleaver

The front end model is illustrated in Fig. 2. The main building blocks are: DSP Options, RFFE, Audio Codec Configuration, ADACMaster III, Audio Codec (In), VPSSVPBE TX, VPSS – VPFE RX, Audio Codec (Out).

1 0 0 1 0 1 1 0 1 0 1 1 1 0 0 0 1 0 1 1 1

2

The 8x8 Interleaver is the next block in the FEC chain of blocks. Here the incoming 64 bit word is broken down into 8x8 matrix and the bits are rearranged as follows and illustrated in Tables 1 and 2.

FRONT END DSP MODEL

V.

1

4

305


⊕ 1

2

3

1

From Eqn. 1 we calculate

2

3

4

Table 3 Syndrome and error bit location

, the transpose of H.

e

0 0 0 0 0 0 0 0 1

The code word at the decoder is, 1 2 3

1

2

3

4

From this p is excluded to give modified code word as, 1 2 3

1

2

3

4

Syndrome now is calculated as, = [s1 s2 s3]

(2)

Another variable ‘e’ is calculated as, ⊕

1

2

3

(3)

Syndrome [s1 s2 s3]

Error bit

Action taken

000 100 010 001 110 011 111 101 ---

none p1 p2 p3 m1 m2 m3 m4 -

none none none none m1⊕1 m2⊕1 m3⊕1 m4⊕1 none

The basis for taking (8,4) block coder in this work is that the implementation is block by block and each block of 32 bits is formed as a multiple of 8 blocks of 4 message bits each.

The value of the syndrome tells us which bit is in error. On the other hand the value of ‘e’ depicts the number of bit errors. If e = ‘1’ then there are multiple bit errors. This is illustrated in Table 3.

These message bits from each 8-bit word are joined together in the proper order to form a 32-bit word at the output of the decoder. After the decoding process the data is sent to the front end to convert to analog form which is heard onto the speakers connected to line-out of the MBD platform.

Hence, just by observing the variable ‘e’ we can tell that there is a single bit error or multiple bit errors. If error is more than one bit, ‘e’ is set to ‘1’ and no action is taken. This process is performed for all of the eight 8-bit words. Now we separate four message bits, after correction, from each 8-bit word. The advantage of taking (8,4) block codes is that it is a slightly improved version of (7,4) block codes.

FIG. 2 FRONT END DSP MODEL

306


Fig. 3 Back End FPGA Model

VI.

SDR system. The results are compared by varying the gain of the DAC and observing the output. It was observed that even at a very low DAC gain a fairly good quality audio is obtained. Out of the 32-bit samples, eight bit errors can be corrected theoretically.

REAL TIME RESULTS AND CONCLUSION

REFERENCES [1] Tian Hangpei, Gao Deyuan, Wang Deli, Zhu Yian, Zhang Shengbing, Qwang Jing, “Dynamically Reconfigurable Instruction Set for Software Radio Encoding / Coding”, 2008 International conference on Multimedia and Ubiquitous Engineering, Busan, Korea, pp. 330 – 335. [2] W.H.W. Tuttlebee: “Software Defined Radio: Facets of a Developing Technology”, IEEE Personal Communications, April 1999. [3] Matthew Sherman,. Apurva N. Mody, Ralph Martinez, Christian Rodriguez, “IEEE Standards Supporting Cognitive Radio Networks, Dynamic Spectrum Access, and Coexistence”, IEEE Communications Magazine, July 2008, pp. 72-79. [4] Xianjun Gao, Yanbin SHI, Ying GAO, Zhongji Tan, “Research on Software Radio in Base-Band Signal Processing”, Proc. 4th international conference on Wireless Communications, Networking and Mobile Computing, 2008, WICOM’08, Dalian, China, pp. 1-4. [5] Ahmadian, M; Nazari, Z,J.; Nakhaee, N.; Kostic, Z.; “Model Based Design and SDR”, DSP enabled Radio, 2005, the 2nd IEE/EURASIP Conference on (Ref No. 2005/11086), pp 19/1 – 19/6. [6] J. Mitola, “Software Radio Architecture: a mathematical perspective”, IEEE J Select. Areas Commun, VOL. 17, 1999, pp. 514-538. [7] Michael L. Dickens, Brian P. Dunn, and J. Nicholas Laneman, “Design and implementation of a Portable Software Radio”, IEEE Communications Magazine, August 2008, pp. 58-66. [8] T. Jahan, R. Muzammil, M. Salim Beg, Izharuddin, “Software Defined Radio based on 16-QAM for future mobile applications”, Proc. Nat. Conf. Mobile Computing, New Delhi, 17-18 Oct. 2008, pp. 137-147. [9] Antonio Di Stefano, Giuseppe Fiscelli, Costantino G. Giaconia, “An FPGA based Software Defined Radio Platform for the 2.4 GHz ISM Band”, Research in Microelctronics and Electronics, 2006, pp 73-76. [10] Xilinx website www.xilinx.com [11] Jeffrey H. Reed, “Software Radio: A Modern Approach to Radio Engineering”, Pearson Education, 2002. [12] Tony J. Rouphael, “RF and Digital Processing for Software-Defined Radio: A Multi-Standard Multi-Mode Approach”, Newnes, 2008. [13] Simon Haykin, “Digital Communications”, John Wiley & Sons, 1988, pp 370-379.

Fig. 4 Audio TX wave

Fig. 5 Audio RX wave

The C code for the DSP and the VHDL code for the FPGAs are generated automatically by the Real Time Workshop and System Generator respectively. These codes are further compiled and built to form “.out” file and “.bit” file for the DSP and FPGAs respectively. Subsequently these output files are burnt onto the DSPs and FPGAs respectively and our system starts running in real time. An audio MP3 player is injected into the line-in and a speaker at the line-out. As can be seen from Fig. 4 & 5, a fairly good quality audio is obtained. Block coding is difficult to realize in practice and hence the developers go in for easier alternative such as convolution coding. Thus this paper has described a successful design and implementation of (8,4) block coder for a BPSK transceiver of an

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