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Wang D, Hu Y, Li HW et al. Design-for-testability features and test implementation of a giga hertz general purpose microprocessor. JOURNAL OF COMPUTER SCIENCE AND TECHNOLOGY 23(6): 1037–1046 Nov. 2008

Design-for-Testability Features and Test Implementation of a Giga Hertz General Purpose Microprocessor Da Wang1,2 (王

达), Yu Hu1 (胡 瑜), Hua-Wei Li1 (李华伟), and Xiao-Wei Li1,∗ (李晓维)

1

Key Laboratory of Computer System and Architecture, Institute of Computing Technology, Chinese Academy of Sciences Beijing 100190, China

2

Graduate University of Chinese Academy of Sciences, Beijing 100049, China

E-mail: {wangda, huyu, lihuawei, lxw}@ict.ac.cn Received May 17, 2008; revised September 1, 2008. Abstract This paper describes the design-for-testability (DFT) features and low-cost testing solutions of a general purpose microprocessor. The optimized DFT features are presented in detail. A hybrid scan compression structure was executed and achieved compression ratio more than ten times. Memory built-in self-test (BIST) circuitries were designed with scan collars instead of bitmaps to reduce area overheads and to improve test and debug efficiency. The implemented DFT framework also utilized internal phase-locked loops (PLL) to provide complex at-speed test clock sequences. Since there are still limitations in this DFT design, the test strategies for this case are quite complex, with complicated automatic test pattern generation (ATPG) and debugging flow. The sample testing results are given in the paper. All the DFT methods discussed in the paper are prototypes for a high-volume manufacturing (HVM) DFT plan to meet high quality test goals as well as slow test power consumption and cost. Keywords

1

microprocessor design-for-testability, test generation, built-in self-test, at-speed testing

Introduction

Nowadays, the semiconductor industry is adopting new fabrication processes which are able to improve design performance, reduce chip area, and save power consumption. High quality design-for-testability (DFT) techniques are critical to economical integrated circuit (IC) testing solutions. Since the microprocessors designed are more complicated and are fabricated with deep sub-micron (DSM) silicon technologies, it is difficult to test them by low-cost testers with previous simple DFT solutions. DFT methodologies, such as test compression, embedded memory testing, at-speed testing, and low testing power consumption methods, are presented for the purpose of conquering various testing challenges of various existing microprocessors[1−9] . From these researches, it is clear that comprehensive DFT frameworks are needed for high performance designs to cover all the details that should be considered. This paper introduces the DFT architecture and its implementation strategies on a giga hertz general

purpose microprocessor designed in the Institute of Computing Technology, Chinese Academy of Sciences. The microprocessor is a low-power, nine-stage, superpipelining and four-issue general purpose RISC microprocessor based on 64-bit MIPS instruction set[10−12] . It contains approximately 50 million transistors and is

Fig.1. Blocks and clock domains of the microprocessor.

Regular Paper ∗ Corresponding Author This paper is supported in part by the National Natural Science Foundation of China under Grant Nos. 60633060, 60606008, 60776031, 60803031 and 90607010, and in part by the National Basic Research 973 Program of China under Grant Nos. 2005CB321604 and 2005CB321605, and in part by the National High Technology Research and Development 863 Program of China under Grant Nos. 2007AA01Z107, 2007AA01Z113, and 2007AA01Z476.

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implemented with STMicroelectronics 90nm, 7-layer metal CMOS technology. The microprocessor includes nine logic blocks with 3 main clock domains, and JTAG with TCK clock domain, as shown in Fig.1. The DDR2 block works at 333MHz ddr clock domain, which is supplied by PLL 1. The PCI block runs at 133MHz pci clock domain. Other seven blocks perform at 1GHz sys clk domain, which is the system clock supplied by PLL 0. In order to obtain a low-cost and high quality testing solution to this giga hertz microprocessor, we try to optimize our DFT framework and test solution. To decrease test data volume for the High Volume Manufacture (HVM) testing, we adopted a hybrid scan compression structure which reaches more than ten times compression ratio. More than 99% test coverage is obtained. To save chip area and ease memory debug, we inserted scan collars into the memory built-in self-test (BIST) circuitries which replaced bitmaps. The scan collar also can be used to shorten functional testing time. To test the chip at-speed with low cost tester, we designed a PLL clock control (PCC) unit to provide complex high speed clock sequences for delay testing. The peak test power consumption is less than 6W. The rest of the paper is organized as follows. Section 2 emphasizes several DFT features in this design. Test pattern generation skills used for overcoming the DFT limitations are discussed in Section 3. Section 4 gives out the sample testing results and the issues we faced.

Section 5 concludes the paper. 2

DFT Features

This microprocessor has several test modes for both manufacture testing and system debug. The DFT logic of this microprocessor is designed for qualities, such as test compression structure, PCC unit for at-speed testing, test control logics for reducing test power consumption, and memory BIST logics which are equipped with scan collars to ease debugging. Fig.2 shows the prototype DFT schematic of the microprocessor. In this framework, the detailed features will be discussed in the following subsections. 2.1

Hybrid Scan Compression Structure

There are about 106 500 flip-flops in the microprocessor. 98% of them are scannable D-flip-flops, the other 2% non-scannabled flip-flops are distributed in JTAG and some control logic. To decrease test data volume, one should compress the scan. A good scan compression (SC) design needs high compression ratio, simplified physical implementation and flexible test execution. In this design, the scan compression structure is applied with a bottom-up flow to the nine logic blocks in order to ease floor planning and routing as well as shorten physical design period. A single scan chain, which connects two special short scan chains that are in the two PLL Clock Control (PCC) units (it will be

Fig.2. DFT schematic of the microprocessor.

Da Wang et al.: DFT and Test Features of a Giga Hertz General Purpose Microprocessor

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Fig.3. Hybrid scan compression structure.

discussed later in Subsection 2.3), is designed together with the SC logics to constitute the hybrid scan compression structure. As shown in Fig.3, the scan in/out ports of the IO block are connected to the primary inputs (PIs) and primary outputs (POs) through the ports of the IO block. Due to some physical design reasons, the scan out ports of some small blocks must go through the IO block to the POs. It makes the task of tracing scan chains more complex. Therefore, we need convenient SC structures in future designs. The length of the compressed scan chains is around 80 flip-flops. The SC structure gets at least ten times compression ratio. Since the SC logics are inserted into each block, the registers in small blocks have more correlation, so we will lose a little test coverage in SC mode. To catch up the test coverage, the short scan chains can be concatenated together to form a long chain called Internal Scan Chain. In this case, the microprocessor is tested in internal mode. A dedicated signal “test compress” is used for switching between SC mode and internal mode. Though the compression ratio got by this SC structure is not as high as that done by the orthodoxy flat, top-level scan compression[1−3] , the method we used in this design brings considerable benefits. It reduces engineering change order (ECO) impact. In this case, we conducted physical design along with RTL modification. Though we changed the scan compression structure module by module, this technique saved more than two months time as much as the flat, top-level way. In addition, our SC structure supports pseudo partition scan test, which depends on generating test patterns for blocks to be tested separately. Compared with other advanced scan solutions[4−7] ,

SC lacks real partition design, and cannot reduce the test power to the utmost. However, it makes the ATPG simpler and faster, and shortens test application time. In our future work, we need to find out more convenient SC structures to satisfy both compression ratio and test power reduction while achieving the targeted test coverage. Furthermore, if partition scan is necessary to the reduction of test data volume and test power consumption, special designs will be implemented. 2.2

Memory Testing

In this design, we used modified March 14N and March 17N as MBIST test algorithms for embedded memories in different logic modules. The MBIST can provide back-to-back read/write operations which detect some of the dynamic faults. To minimize the timing impact on performance, MBIST does not cover register files (regfile) on critical paths. The percentage of the undetected faults of these regfiles only occupies less than 1% proportion of the whole fault set. In order to increase test coverage, we inserted scannable flip-flops into each port of these unBISTed regfiles. Taking into consideration the memory BIST test power consumption and the ECO impact, we synthesized the MBIST circuitries at 600MHz. The detailed experimental discussion will be given later. Furthermore, to decrease chip area and power consumption, we inserted scan collars into the MBIST circuitries which replaced bitmaps for debugging and failure analysis. 2.2.1 Why 600MHz MBIST Circuitries Test power dissipation is an important issue that must be taken care of. Before conducting synthesis and

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ATPG, we had done experiments on previous versions of the microprocessor to verify the delay test power dissipation, and the results fell into three categories. • Synthesize the MBIST logic at 1GHz and run transition faults (TF) ATPG for the whole circuitry. The TF test will get more than 90% test coverage easily. At the same time, the peak test power by simulation is about twice that of function. In addition, in this case, the embedded memories might be destroyed due to thermal burst. • Synthesize the MBIST logic at 1GHz and do TF ATPG at block level. The test power during TF test is decreased sharply. However, the testing time increases to triple of the first case with the same test coverage. Furthermore, the memory test power is not reduced during high speed MBIST testing. • Synthesize the MBIST logic at 600MHz and run TF ATPG for the whole circuitry. Though the TF test coverage only reaches 85%, which is 5% lower than the previous cases, the test power for both memory testing and delay testing can endure the die without increasing TF test time. We adopt this strategy with trading off between benefits and disadvantages.

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debug the memory array under certain conditions as needed. Considering the memory locations and routing congestion, we let four to five memory arrays share one MBIST controller. For the scan collar of each memory array, they can also be connected together with normal scan chains or the other scan collars. The connection strategy made it easy and time saving to shift in/out data of memories during testing and debugging.

2.2.2 Why Insert Scan Collars into MBIST Generally speaking, bitmaps are usually fed into MBIST to ease silicon debugging. A bitmap contains at least the information of one failure word, such as word address, data, status. The bitmap with one failure word for a 512 × 32 memory array will easily cost more than 50 registers. Since there are more than 120 memory arrays in L1 and L2 caches, if a bitmap is equipped for each memory array, there will be more than ten thousand registers added. The area overheads will be very heavy. To combat with the area overheads and power consumption, we inserted scan collars into MBIST circuitries instead of bitmaps. A scan collar is a specific scan chain as shown in Fig.4(a). It contains particular scan cells (P-cell, as shown in Fig.4(b)) connecting to the CSN, WEN, Address and Q ports of the memory array. D and Q ports share the same P-cell by using a multiplexer. When doing debug, we set the MBIST circuitry into scan collar mode. Particular debug data are shifted into the scan collar at first. And then data are written into the D ports of the memory in one cycle. In the next cycle, data are captured from the Q ports. During the shift process, the SE signal is high and asserts the memory array selection enable (CSN) signal to protect values in the cache. During the capture process, CSN is determined by the value of the register connected to CSN. Thus, we are able to test and

Fig.4. (a) Scan collar in the MBIST circuitry. (b) P-cell used in scan collar.

2.2.3 Benefits and Drawbacks of Using Scan Collar We have conducted experiments based on the former version of the microprocessor, and found out that there are many advantages of using scan collars instead of bitmaps. a. It reduces more than four thousand registers compared to use bitmaps. Furthermore, the routing complexity and power consumption are reduced. b. It is convenient for various memory test algorithms to do further testing, debugging, and analysis. For example, we can write and observe a targeted cell by shifting in a certain test pattern and capture the response. c. It is easy to do functional test with scan collars. We first write the functional test instructions into caches through the scan collar. And then, boot the design until a symbol which indicated the end of the test is shown. Therefore using scan collars can save

Da Wang et al.: DFT and Test Features of a Giga Hertz General Purpose Microprocessor

debugging time while offering the flexibility for choosing some other functional test patterns for certain purpose. d. It enhances the test coverage of the chip. Because scan collars can also be used as normal scan chains during scan testing. Though there are many benefits of using scan collars, it makes the ATPG flow complex and time-consuming. When executing memory debugging or further testing under other test algorithms, the engineer must generate test patterns exactly for the given memory cells or arrays in scan mode. 2.3

Clock Control

2.3.1 PLL Clock Control (PCC) Unit Previous work has pointed out that for the design with embedded memories, it is necessary for complex sequences to let test patterns go through memories[9,13] . In this microprocessor, we have designed a PLL Clock Control (PCC) unit to provide proper at-speed test clock sequences based on our previous work[14] , as shown in Fig.5(a). The PCC unit has three inputs. One is pll clk, the clock signal from PLL. The second one is SE, the scan enable signal from ATE. The last one is the input of clock chain, a special scan chain in the test clock do-

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main. In the PCC unit, the AND-gate network is the key to export test sequences. Each AND gate has three inputs. One is connected with the Q port of the register in the clock chain, and the other two are connected with the input and the output of the register in the upside chain, which is within the pll clk domain. The data in the clock chain are used for setting control signals for AND gates to generate various clock waveforms. The upside chain is used for properly propagating the SE signal to let AND gates output clock waveforms in a complete pll clk cycle without glitches. To make the SE signal stable, a D flip-flop is inserted just behind it, locking its value at the active edge of the test clock. In test mode, the negative value of SE is filtrated and shifted into the upside chain under pll clk. When SE is high (active), which means the circuit under test (CUT) is in the process of scan shift (load/unload), values in the upside chain are all “0”s. Once the shift process is finished, SE is low (inactive) and the CUT changes into scan launch-capture mode. Before and after launchcapture, there should be enough setup/hold time to ensure that all the flip-flops are stable. Thus, five pll clk cycles are inserted by using registers shift reg[0-4] and shift reg[9-13] separately in the upside chain. These registers work as a glacis of slow-to-fast/fast-to-slow clock switching to avoid high current appearance when SE is switched. When the “1” to “0” switching of SE

Fig.5. (a) PCC unit logic. (b) Clock sequences for at-speed testing. (c) Clock select unit.

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is transmitted to shift reg[5], the positive input and the negative output of this register will work together to set the first AND gate to output the signal coming from register clock chain[0]. At the next active edge of pll clk, the first AND gate is disabled due to the switch of SE transmitted to the next register in the upside chain. It guarantees that the first AND gate outputs a complete pll clk cycle. The rest of the logic works in the similar way. The function of the PCC unit is to supply proper high-frequency pulses for at-speed testing, and pcc clk, which is only valid when SE is low as indicated in Fig.5(b). It is simple for ATPG tools to choose pulses in a range of two to four cycles which depended on the “1”s in the clock chain during generation of at-speed test patterns. The PCC logic can also prevent metastable state caused by clock or asynchronous “reset” signals. This unit is designed to be independent of PLL frame and silicon technology. Compared with other designs that using on-chip clock for at-speed testing[15,16] , our design is much simpler, and easy to extend to providing more flexible test sequences in various designs for multi-clock domains testing. Based on this PCC unit, we further presented a clock control scheme to test timing-related faults in inter-clock domain and intra-clock domain logics in [17]. This scheme will be applied in our future designs. 2.4

Other DFT Logics

In this microprocessor, the usual DFT logics are completely equipped, as shown in Fig.2. We designed JTAG controller, TAP, using a 4-bit instruction register and more than 12 instructions to conduct test operations and support standard commands. We simplified the relationship between the test control signals in the test control unit so that the testing controllability and test coverage were enhanced. For example, the test control signals for scan and AC/DC tests are globally set and directly controlled by the tester. The test control signals for MBIST and other tests are individually set for blocks with combinational logic. Since there are multiple clock domains in the design, and to ensure that these various clocks run correctly during test, we designed the clock control unit to give proper clock for testing and functional modes, as shown in Fig.5(c). Three multiplexers were used to select suitable clock as internal clock. Multiplexer “A” uses signal “test mode” to select between test clock for testing or pll clk for function. Multiplexer “B” selects low speed clock from the tester or the sequences coming from multiplexer “C”. Multiplexer “C”, which is set by SE, combines the tester clock and pcc clk together as

the clock sequences for at-speed testing. 3

Test Pattern Generation

The test goal of high-volume manufacturing is to detect defects as many as possible with fewer test patterns. Test pattern generation is another key process to test this high performance design with quality[18] . In this section we use TF ATPG as an example to describe our ATPG flow. 3.1

Transition Delay Faults ATPG

Since the MBIST logics which reused the 1GHz sys clk are synthesized at 600MHz, we generated atspeed testing patterns in two steps. 1) First of all, we ran 1GHz ATPG. During this phase, the MBIST logics were frozen by clock gating. For the purpose of extending fault coverage, embedded memories were bypassed and constrained in the functional mode. To avoid unknown bits (X bits) aliasing from the memory in the functional mode, we filled the memory with constant by the MBIST logic at the initial stage before ATPG. The testing time increased by memory filling was ignored. 2) Then, we ran ATPG at 600MHz to test the MBIST logics. At this step, we enabled the memories without filling the constant. Test patterns can go through the memory for propagation or sensitization. With these steps, the test power was controlled effectively and efficiently. Table 1. 1GHz TF ATPG Results Logic Block

No. Faults

Test Cov.

Mem. Size

CORE CTRL FETCH MEMORY FLOAT FIX INTF CTRL L2 Cache DDR2 PCI Arbiter Total

717 108 527 652 870 054 1 083 778 581 592 283 294 675 042 1 055 582 615 868 312 918 5 950 908

94.78% 81.25% 85.43% 79.47% 81.19% 92.74% 62.73% 75.29% 91.58% 90.81% 82.30%

– 72KB 72KB 6KB 4KB – 576KB – – – 730KB

Table 1 shows the TF ATPG results of each block. From the table we can see that the blocks with embedded memories contribute low test coverage, except DDR2 (without embedded memory, in bold). DDR2 is an IP core with un-scanned DFFs and feedback loops in the design. It confused the commercial ATPG tool in making a good decision. As indicated in the table, the unit with the lowest test coverage, L2 Cache (in italic

Da Wang et al.: DFT and Test Features of a Giga Hertz General Purpose Microprocessor

bold), is the unit with the maximum memory size. Although the PCC unit can provide several complex clock sequences, the targeted test coverage is hard to achieve. We have tried to gain higher test coverage, but the test data volume increases to an unacceptable amount. Meanwhile, the ATPG and testing time will aggrandize to unbearable quantity. Since in our future design the MBIST modules will be synthesized at 1GHz, and in that case the test coverage will be significantly improved, we mainly shorten ATPG and testing time in our present design. In summary, the causes that impact test coverage are concluded as follows. The first one is the test compression structure that is inserted with a bottom-up flow for each block in this design. Because in some small blocks, there is high correlation between DFFs, it decreases the testability. The second one is the 600MHz MBIST circuitries. These logics in the system clock domain cannot run at system speed. The third one is the design of DDR2 which hurts the delay fault test coverage. The last one is that the ATPG tool cannot work efficiently with functional models of embedded memories. Such shortcomings will be improved in our future work. 3.2

ATPG Flow and Results

The test patterns for delay fault and bridging fault (BF) testing can also detect a large number of single stuck-at faults (SSAF). To minimize the test data volume, we generated delay test patterns and BF test patterns at first. Then we used these test patterns to do fault simulation based on SSAF model. Afterwards, incremental patterns were generated for the undetected SSAFs in both SC and internal mode. Finally we chose 10 patterns that reached 90% IDDQ test coverage from SSAF test sets. With this flow, 6% more test data volume was further reduced. 4 4.1

Test Implementation and Sample Testing Results Full Chip Test Implementation

Fig.6 shows a typical microprocessor testing flow. It consists of wafer sort, assembly, final test I, burnin test, and final test II. Usually, wafer sort consists of most of the test items. Other test phases are the subset of all the test items. 4.1.1 Wafer Sort Wafer sort usually starts with open/short test to examine the connectivity, input/output leakage test, and

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Fig.6. Typical microprocessor testing flow.

standby/active current test for measuring the operating current. The manufacturer information and device IDs are also verified. To test these items, we should provide I/O test patterns and JTAG test patterns. These patterns must contain standby/active commands and can set the chip into a stable mode. For instance, for this microprocessor, we designed IOmap and NANDTree for IO AC/DC characteristic testing. During this test stage, the 2% no-scanned DFFs are tested by testing JTAG logic and IO pads. Furthermore, for the purpose of detecting the defects brought in by instability of manufacture, structural testing items are executed. In this design, we implemented scan test as follows: SSAF test patterns with 99.3% test coverage; BF test pattern with 85% coverage; TF test patterns with 82.7% test coverage under 1GHz; path-delay faults (PF) test patterns which covered 7000 paths with 60% test coverage. The MBIST test patterns were employed to test the embedded memories. Though MBIST circuitries for the L1, L2 caches are different from that for regfiles, we modified the MBIST of regfiles to make sure all the MBIST logics can run at the same time, reducing test cost. Since the regfiles were multi-read/write ports, we tested the read/write ports in couple order. IDDQ test was also employed for this 90nm design, and it will be particularly discussed in Subsection 4.4. Functional tests made use of testing the logic parts that have low at-speed test coverage by structural test patterns, such as DDR2 block, L2 cache, and those regfiles without MBIST circuitries. The function of the PLL was also tested in this stage. A 1/8 frequency divider was connected between the output of the PLL and an output pad. Thus, we were able to test the PLL function by testing this special pad’s output. 4.1.2 Final Test and Burn-In Test After assembly, the chips should be retested in final test I. In this test stage, only I/O test and some of the structural test items will be employed, depending on the design. The major motivation is to detect the invalidated chips after package. We executed I/O

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AC/DC test, JTAG test, MBIST, SSAF, and TF test at typical case as test items during final test I. Burn-in test is the most important test to screen out the infant failure chips. It focuses on the devices stability and reliability. We used JTAG, MBIST, flush pattern and simple functional test patterns as burn-in test items. Then we went on to final test II stage to make sure the I/O of the chips was fault-free. Passing all these test stages, the chip is considered ready for delivering to customers. 4.2

Sample Testing Results

The sample testing yield and the failure percentage of each testing items are shown in Table 2. Table 3 gives the results of some of the test items with real testing time and test power consumption. From the testing time we can see that the test data volume reduction strategy and the utilization of scan collars prove effective and economical. From the yield of the sample dice we can see that, delay faults are the most likely defect to happen for this giga hertz microprocessor. It means that the unstable manufacturing technique affects the performance of the microprocessor. Along with the performance improvement of the design, there is further requirement on the silicon manufacturing quality. In addition, though the structure of memory array is regular, from the testing result we also found out that more than 3% dice failed on MBIST test. As the International Technology Roadmap for Semiconductors Table 2. Yield of the Sample Dice Item Total tested Passed Failed TF SSAF MBIST JTAG IDDQ Open Miscellaneous Total Failed

No.

Percent

656 517 57 25 22 13 8 7 7 139

100.0% 78.8% 8.7% 3.8% 3.4% 2.0% 1.2% 1.1% 1.1% 21.2%

(ITRS) pointed out that there will be more and more embedded memories employed in the microprocessor and ASIC designs[19] . Memory will be the yield dominator of the silicon chips in the future. In this microprocessor, the core voltage domain in typical, worst and best cases is 1.2V, 1.1V, and 1.3V respectively. For the TF testing, the power consumption was more than 5W when the sys clk was set at 600MHz, under the condition that embedded memories and MBIST were enabled. To protest the chip, 1GHz TF testing was only applied with bypassing embedded memories, and the test power was about 6W. Test power of 450MHz and 600MHz MBIST testing was about 2W and 2.5W separately. The test power listed in the table proves our DFT power control solution obviously. The major difference between an ASIC design and a general purpose microprocessor is that the ASIC usually has much more stringent power consumption budget with higher performance goal. Therefore, test scheduling and test pattern optimization for low power need to be further considered in testing ASIC. 4.3

At-Speed Power Supply and IR Drop

Besides high power consumption caused by excessive switching activities, it is common that IR drop occurs during TF testing. In the typical case, the sample dice failed in 1GHz TF delay testing with 1.2V power supply. They can pass the test at maximum 960MHz with 1.2V power supply. As we have considered TF test power reduction in both DFT and ATPG flows, it is not clear whether the dice failed due to additional delay caused by IR drop, or due to delay faults. Therefore, at-speed functional test patterns should be used to validate the TF testing results in our future work. And the test power during functional tests is a good reference to judge whether there is or no serious IR-drop during TF testing. If the failures are due to IR drop, it may indicate that the coarse flow control during ATPG is not enough, and current ATPG tools or algorithms should be improved and targeted on low-power delay test pattern generation to avoid it.

Table 3. Sample Testing Results Fault Model

Cover.

Transition Delay Fault Path Delay Fault Bridging Fault Single Stuck-At Fault Memory BIST

> 82% 7000 paths > 85% > 99% –

Shift Freq.

Testing Time

Sim. Power

Test Power

30MHz 30MHz 30MHz 30MHz 600MHz

∼66ms ∼10ms 3ms ∼30ms ∼0.1ms

5W (1GHz) – ∼3W ∼3W –

∼6W –