Designs of All-Optical Higher-Order Signed-Digit Adders Using

Optics and Photonics Journal, 2014, 4, 113-128 Published Online June 2014 in SciRes. http://www.scirp.org/journal/opj http://dx.doi.org/10.4236/opj.2014.46012

Designs of All-Optical Higher-Order Signed-Digit Adders Using PolarizationEncoded Based TerahertzOptical-Asymmetric-Demultiplexer (TOAD) Ali Hajjiah*, Abdullah Alqallaf, Abdallah Cherri Department of Electrical Engineering, College of Engineering & Petroleum, Kuwait University, Safat, Kuwait * Email: [email protected] Received 1 February 2014; revised 2 March 2014; accepted 1 April 2014 Copyright © 2014 by authors and Scientific Research Publishing Inc. This work is licensed under the Creative Commons Attribution International License (CC BY). http://creativecommons.org/licenses/by/4.0/

Abstract Various designed circuits for multiple-valued all-optical arithmetic are demonstrated. The terahertz-optical-asymmetric-demultiplexer (TOAD) switch is used as the basic structure unit in the proposed circuits due to its compact size, thermal stability, and low power operation. The designs of trinary and quaternary signed-digit numbers based adders are presented using different polarized states of light. These proposed polarization-encoded based adders use much less switches and their speeds are higher than the intensity-encoded counterparts. Further, it will be shown that one of the proposed trinary signed-digit adders is twice as fast as a recently reported modified signed-digit adder.

Keywords Multiple-Valued Signed-Digit, All-Optical Gates, Polarization-Encoding, Terahertz-Optical-Asymmetric-Demultiplexer (TOAD)

1. Introduction Multiple-valued logic and arithmetic is being extensively investigated as being a promising choice for future digital and optical computing [1]-[10]. Redundant signed-digit is among the various multiple-valued number systems [11]. Attractions features of this choice are higher information transmission, higher data storage i.e. more logic density and higher processing speed due to the opportunity of having parallel computing algorithms *

Corresponding author.

How to cite this paper: Hajjiah, A., Alqallaf, A. and Cherri, A. (2014) Designs of All-Optical Higher-Order Signed-Digit Adders Using Polarization-Encoded Based Terahertz-Optical-Asymmetric-Demultiplexer (TOAD). Optics and Photonics Journal, 4, 113-128. http://dx.doi.org/10.4236/opj.2014.46012

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[12]. The addition/subtraction of two signed-digit numbers restricts the carry propagation to one or two adjoining digits. Many researchers proposed optoelectronics implementations to achieve fast computing arithmetic [13]-[18]. On the other hand, the recent developments in all-optical switches that are capable of demultiplexing Tb/s pulse trains push the researchers to shift towards all-optical implementations to design ultra-fast logical and arithmetic units using binary and nonbinary algorithms [19]-[24]. Recently, all-optical arithmetic operations based on terahertz-optical-asymmetric-demultiplexer (TOAD) switch were demonstrated [20] [22]. All-optical multiple logic gates (XOR, NOR, NAND) as well as binary half- and full-adders were reported using parallel TOAD structures. Further, with the help of TOAD switches, fast nonbinary adders were demonstrated [23] where the input and the control signals are all-optical in nature. The high speed is achieved due to the use of the nonlinear optical materials and the nonbinary modified signeddigit (MSD) number representation. In contrast to binary adder, the proposed circuits can be extended to n digits by employing additional stages without affecting the total addition time. Since the multiple-valued digits cannot be directly implemented using the two binary states of the TOAD switches, intensity-encoding schemes are used to transform the signed-digits into binary bits. More recently, the intensity-encoded MSD adder was improved in terms of its TOAD switches count and its speed by utilization of polarization-encoded scheme [24]. Now since multiple-valued logic/arithmetic is being viewed as an interesting approach in optical information processing, we present, in this paper, design methods to implement trinary signed-digit (TSD) and quaternary signed-digit (QSD) arithmetic. TSD and QSD number systems are represented by five and seven literals, respectively. Consequently, the two-bit intensity-encoding (light, no light) scheme, as reported in [24], cannot be used in designing the higher-order signed-digit (SD) adders. A straightforward solution is to use a three-bit intensityencoding scheme for each SD literal. However, in this case the all-optical circuit implementation will be very complicated. Alternatively, this limitation is solved by proposing the polarized state of light (vertical and horizontal) and a two-bit encoding scheme. The polarization-encoding method is used to design fast all-optical TSD and QSD number based adders. The proposed adders are compared in terms of numbers of gate delays, TOAD switches, beam combiners, and polarization converters. Further, these circuits are compared to the previously reported MSD adder [24]. It will be shown that the TSD adder is two times faster than the MSD one; while the QSD adder speed is the same. Sections 2 and 3 will briefly review the operation of the TOAD switch and the SD number representation, respectively. Section 4 and 5 provide five adder designs: three for the TSD and two for the QSD adders. In section 6, we summarize the results and make some conclusions.

2. Operation of TOAD Based Optical Switch In the last few years, the TOAD switch [19] was extensively used in realizing various ultrafast logical and arithmetic operations. Its speed is due to its capability of demultiplexing tera bits per second pulse trains where a light signal controls another light beam. In addition to its speed, the relatively low power consumption makes it attractive for large-optical integration. TOAD switch consists of a loop mirror with an intra loop 2 × 2 coupler and a semiconductor optical amplifier (SOA) which is offset from the loop’s midpoint by a distance Δx as shown in Figure 1(a). The SOA constitutes the nonlinear element within the switch where when exposed to a strong light it saturates and its index of refraction is changed. Full details of the operation of the TOAD switch is explained in [19] [22]. The TOAD switch operates with two lights signal through nonlinear interaction in a material based on interferometer setup: a strong optical signal, called the control pulse—CP, and another optical signal, called the incoming pulse—IP. Briefly, the TOAD switch works as follows. When there is no CP signal, the IP signal enters the loop shown in Figure 1(a) and splits into two counter propagating ones. These two signals now recombine and interfere at the input coupler and emerge as a single light at the input port. However, if a strong CP light is injected into the loop causing the SOA to saturate and its index of refraction is changed. Consequently, the two IP counter propagating signals will face differential phase shift such that they will interfere and re-emerge or transmitted from the output port. At the two ports (reflected and transmitted), a polarization or wavelength filter is used to block the optical CP signal and only pass the optical IP signal. The energy of the optical CP must be sufficient to modify the optical property of the SOA element whereas the two counter propagating IP signals do not. Further, the IP and the CP signals are to be entered the SOA at about the same time. Further, in the absence of the CP signal, the input light exits from the lower port in the figure (no light is present in the upper port). However, when both CP and IP signals are present simultaneously, all light is directed towards the upper port because of the refractive-index change induced by the CP signal (no light is present in the lower port). When there is no IP

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SOA

C O U P L E R

∆X

Filter

OUTPUT 1

(Transmission)

Filter

OUTPUT 0

(Reflection)

Control Light

Input Light

Incoming Pulse Light (IP) Control Pulse Light (CP)

(a)

T O A D

Output 1

Output 0

(b)

Figure 1. (a) TOAD-based optical switch; (b) a schematic diagram for the switch.

signal, both channels receive no light as the filter blocks the CP signal. A schematic block diagram for the TOAD switch is shown in Figure 1(b). TOAD switches can successfully be used for designing logical circuits. For instance, cascaded TOAD switches as shown in Figure 2 are used to generate the sixteen minterms for four input logical variables xi1 xi2 yi1 yi2 . This structure can be viewed as a 1 × 16 decoder where only one output is activated that corresponds to a specific minterm. Note that the output ports are numbered according to the corresponding generated minterms. ORing of these minterms (sum-of-products) is performed with flexible outputs interconnectivities (beam splitters/combiners) and ANDing operations are achieved by cascading stages (switches) where any output port signal can be used as an input to another switch. Note that in this case, the output optical signal of the first switch may need to be amplified and/or wavelength converted before it is fed to the next switch. As a result, this switch structure can be used as a preliminary non minimized basic building block to realize any logical Boolean function.

(

)

3. Signed-Digit Numbers Signed-digit (SD) numbers are formally defined as follows [12]: given a radix r, each digit of SD number assumes (2α + 1) values of the digit set {−α,  , −1, 0, 1,  , α} where α ≤ r − 1 and r ≥ 3. In general, a decimal number D may be represented in terms of an n-digits SD number as n −1

D = ∑ bi r j

(1)

j =0

where bi digit is selected from the set {−α,  , −1, 0, 1,  , α} to produce the appropriate decimal representation. For trinary signed-digit (TSD) r = 3, the digit set is { 2 , 1 , 0, 1, 2}; whereas for quaternary signed-digit (QSD) r = 4 and the digit set is { 3 , 2 , 1 , 0, 1, 2, 3}. Here the digits 3 , 2 , and 1 denote −3, −2, and −1, respectively. For radix ≥ 3, the addition operation of two SD numbers is performed in two successive steps because some digit combinations cause carry propagation to the next higher-order digit. The generation of a carry may be avoided by mapping the two SD digits in question into an intermediate sum and an intermediate carry (also known as weight and transfer digits) such that the i-th intermediate sum and the (i−1)-th intermediate carry when added generate no carry. The two-step addition is governed by the following equations:

Step-one → X i + Yi= rTi +1 + Wi

(2)

Step-two → Si =Ti + Wi

(3)

where Ti and Wi represent the intermediate carry and sum, respectively, and Si is the final carry-free sum. Further, subtraction of two SD numbers can be obtained by first complementing the subtrahend and then an addition operation is applied. Thus, the subtraction of two SD numbers involves three steps.

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xi1

xi2

yi1

yi2 xi1 xi2 yi1 (7)

T O A D

xi1 xi2 (3)

1 2 i i

1 i

x (1)

x x ( 2)

T O A D LIGHT

T O A D

T O A D

xi1 xi2 yi1 (6)

xi1 xi2 yi1 (5)

xi1 xi2 yi1 (4)

T O A D

T O A D

T O A D

T O A D

1 2 1 2 → xi xi y i y i (15) 1 2 1 2 → xi xi y i y i (14) 1 2 1 2 → xi xi y i y i (13) 1 2 1 2 → xi xi y i y i (12)

1 2 1 2 → xi xi y i y i (11) 1 2 1 2 → xi xi y i y i (10)

1 2 1 2 → xi xi y i y i (9) 1 2 1 2 → xi xi y i y i (8)

1 2 1 2 → x i x i y i y i (7 )

xi1 (0)

T O A D

xi1 xi2 (1)

T O A D

xi1 xi2 yi1 (3)

x x y ( 2)

T O A D

xi1 xi2 yi1 (1)

T O A D

xi1 xi2 yi1 (0)

T O A D

1 2 1 i i i

xi1 xi2 (0)

T O A D

T O A D

1 2 1 2 → xi xi y i y i (6)

1 2 1 2 → xi xi y i y i (5) 1 2 1 2 → x i x i y i y i ( 4)

1 2 1 2 → xi xi y i y i (3) 1 2 1 2 → xi xi y i y i (2)

1 2 1 2 → xi xi y i y i (1) 1 2 1 2 → xi xi y i y i (0)

Figure 2. 1 × 16 TOAD based decoder.

The totally-parallel adder for SD number representation is shown in Figure 3 where the functional blocks A and B represent the computing rules generated from Equations (2) and (3), respectively. For TSD and QSD numbers, all possible two SD numbers that satisfy Equations (2) and (3) above are listed in Table 1 and Table 2, respectively. Note that the SD numbers in these tables are grouped according to the value of the output digit. The pairs of the to-be-added trinary digits are first divided into nine groups (for the first step) as shown in the second column of Table 1a whereas the third column of the table shows the necessary intermediate carry and intermediate sum digits for carry-free addition. Table 1(b) lists the rules for the second step of the addition. Thus, Table 1(a) and Table 1(b) represent the 25 and the 9 computational rules that are used in blocks A and B of Figure 3 for the TSD addition. Notice that these tables include polarization encoding of the SD digits that will be explained in the next section. Similarly, the pairs of the to-be-added quaternary digits are arranged into thirteen groups for the first step and seven groups for the second step as shown in Table 2.

4. Polarization-Encoded TOAD-Based TSD Adder Circuits It was mentioned in the previous section that the TOAD-based decoder method can be used to implement any logical function expressed as sum-of-products. The variables of the minterms are the control signals of the decoder. Now, since the TSD numbers { 2 , 1 , 0, 1, 2} have five symbols, a three-bit intensity-encoding scheme (light, no light) is needed for each SD symbol to provide the control signals. Therefore, the addition of two SD numbers requires six control signals. Consequently, the design of the all-optical circuit requires 1 × 64 decoder with tens of TOAD switches. Obviously, this is not practical. As a solution to this limitation we propose using polarized state of light (vertical and horizontal) and a two-bit encoding scheme such that the TSD numbers { 2 , 1 , 0, 1, 2} are encoded as {H0, 0H, 00, 0V, V0}, respectively. Further, recall that the light of the two inputs in a TOAD switch (the CP and the IP lights) must have different intensities, different wavelengths, or different light polarization states. Since we do not know the polarization state of the light representing the TSD number ahead of time, then we cannot feed this light signal to the decoder as a control signal. This difficulty can be solved by using polarization beam splitters in order to generate two polarization channels for each TSD digits. Therefore, a TSD digit Xi, which is decoded as X i = xi1 xi2 , is routed to polarization beam splitters (PBS) to produce

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Table 1. (a) Truth table and polarization-encoding for the first step TSD addition; (b) Truth table and polarization-encoding for the second TSD addition.

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(a) Group Number

Addend/Augend

xi yi ( x x y 1H i

2H i

1H i

2H i

y

1V i

2V i

1V i

2V i

x x y y

)

Intermediate Carry/Sum Ti +1Wi

G1

2 2 (0 0 0 0

V 0 V 0)

1 1 (V V)

G2

2 1 (0 0 0 0 1 2 (0 0 0 0

V 0 0 V) 0 V V 0)

1 0 (V 0)

G3

1 1 (0 0 0 0 0 2 (0 0 0 0 2 0 (0 0 0 0

0 V 0 V) 0 0 V 0) V 0 0 0)

1 1 (V H)

G4

01 10 21 12

(0 0 0 0 (0 0 0 0 (0 0 0 H (0 H 0 0

0 0 0 V) 0 V 0 0) V 0 0 0) 0 0 V 0)

0 1 (0 V)

G5

00 11 11 22 22

(0 0 0 0 (0 0 0 H (0 H 0 0 (0 0 H 0 (H 0 0 0

0 0 0 0) 0 V 0 0) 0 0 0 V) V 0 0 0) 0 0 V 0)

0 0 (0 0)

G6

21 12 01 10

(H 0 0 0 (0 0 H 0 (0 0 0 H (0 H 0 0

0 0 0 V) 0 V 0 0) 0 0 0 0) 0 0 0 0)

0 1 (0 H)

G7

1 1 (0 H 0 H 0 2 (0 0 H 0 2 0 (H 0 0 0

0 0 0 0) 0 0 0 0) 0 0 0 0)

1 1 (H V)

G8

1 2 (0 H H 0 2 1 (H 0 0 H

0 0 0 0) 0 0 0 0)

1 0 (H 0)

G9

2 2 (H 0 H 0

0 0 0 0)

1 1 (H H)

(b) Group Number

Intermediate Carry/Sum

Final Sum

G1

1 1 (0V0V)

2 (V 0)

G2

0 1 (000V) 1 0 (0V00)

1 (0 V)

G3

0 0 (0000) 1 1 (0VH0) 1 1 (H00V)

0 (0 0)

G4

0 1 (00H0) 1 0 (H000)

1 (0 H)

G5

1 1 (H0H0)

2 (H 0)

TW T H Ti V Wi HWi V ) i i ( i

Si ( Si1 Si2 )

X i = xi1H xi2 H xi1V xi2V as shown in Figure 4. This encoding scheme is used for the addend and the augend for the TSD numbers in Table 1 and Table 2. Further, whenever the intermediate carry or the intermediate sum digit in the adder belongs to the set { 1 , 0, 1}, one-bit encoding such as {H, 0, V} is used in the encoding scheme.

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Table 2. (a) Truth table and polarization-encoding for the first step QSD addition; (b) Truth table and polarization-encoding for the second step QSD addition. (a) Addend/Augend

Intermediate Carry/Sum Group 1H 2 H 1H 2H xi1V xi2V yi1V yi2V ) Ti +1Wi ( ti +1 wi1V wi2V wi1H wi2 H ) Number xi yi ( xi xi yi yi 3 3 (0 0 0 0

V V V V)

(0 0 0 0 (0 0 0 0 (0 0 0 0 (0 0 0 0 2 2 (0 0 0 0 2 1 (0 0 0 0 1 2 (0 0 0 0 0 3 (0 0 0 0 3 0 (0 0 0 0 1 1 (0 0 0 0 0 2 (0 0 0 0 2 0 (0 0 0 0 3 1 (0 0 0 H 1 3 (0 H 0 0 0 1 (0 0 0 0 1 0 (0 0 0 0 2 1 (0 0 0 H 1 2 (0 H 0 0 3 2 (0 0 H 0 2 3 (H 0 0 0 0 0 (0 0 0 0 1 1 (0 0 0 H 1 1 (0 H 0 0 2 2 (0 0 H 0 2 2 (H 0 0 0 3 3 (H H 0 0 3 3 (0 0 H H 0 1 (0 0 0 H 1 0 (0 H 0 0 2 1 (H 0 0 0 1 2 (0 0 H 0 3 2 (H H 0 0 2 3 (0 0 H H

V 0 V V) V V V 0) V V 0 V) 0 V V V) V 0 V 0) V 0 0 V) 0 V V 0) 0 0 V V) V V 0 0) 0 V 0 V) 0 0 V 0) V 0 0 0) V V 0 0) 0 0 V V) 0 0 0 V) 0 V 0 0) V 0 0 0) 0 0 V 0) V V 0 0) 0 0 V V) 0 0 0 0) 0 V 0 0) 0 0 0 V) V 0 0 0) 0 0 V 0) 0 0 V V) V V 0 0) 0 0 0 0) 0 0 0 0) 0 0 0 V) 0 V 0 0) 0 0 V 0) V 0 0 0)

G9

1 1 02 20 31 13

(0 H 0 H (0 0 H 0 (H 0 0 0 (H H 0 0 (0 0 H H

G1 G2 G3

G4

G5

23 32 31 13

1 2 (V V 0 0 0) 1 1 (V 0 V 0 0) 1 0 (V

0 0 0 0)

1 1 (V

0 0 0 H)

0 2 (0

V 0 0 0)

0 1 (0

0 V 0 0)

0 0 (0

0 0 0 0)

0 1 (0

0 0 0 H)

0 0 0 0) 0 0 0 0) 0 0 0 0) 0 0 0 V) 0 V 0 0)

0 2 (0

0 0 H 0)

G10

1 2 21 30 03

(0 H H 0 (H 0 0 H (H H 0 0 (0 0 H H

0 0 0 0) 0 0 0 0) 0 0 0 0) 0 0 0 0)

1 1 (H

0 V 0 0)

G11

31 (H H 0 H 1 3 (0 H H H 2 2 (H 0 H 0

0 0 0 0) 0 0 0 0) 0 0 0 0)

1 0 (H

0 0 0 0)

G12

3 2 (H H H 0 2 3 (H 0 H H

0 0 0 0) 0 0 0 0)

1 1 (H

0 0 0 H)

G13

3 3 (H H H H

0 0 0 0)

1 2 (H

0 0 H 0)

G6

G7

G8

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(b) Intermediate Carry/Sum

Final Sum Si ( Si1 Si2 )

G1

1 2 (0 V V 0 0 0)

3 (V V)

G2

1 1 (0 V 0 V 0 0)

2 (V 0)

G3

0 1 (0 0 0 V 0 0) 1 0 (0 V 0 0 0 0)

1 (0 V)

G4

0 0 (0 0 0 0 0 0) 1 1 (0 V 0 0 0 H) 1 1 (H 0 0 V 0 0)

0 (0 0)

G5

0 1 (0 0 0 0 0 H) 1 0 (H 0 0 0 0 0)

1 (0 H)

G6

1 1 (H 0 0 0 0 H)

2 (H 0)

G7

1 2 (H 0 0 0 H 0)

3 (H H)

Group Number

Ti Wi (Ti H Ti V wi1V wi2V wi1H wi2 H )

Figure 3. The two-step multiple-valued SD addition scheme. PBS

X

1 i

PBS

x

1V i

X

xi1H

xi2 H

PBS

Yi

1

xi2V

2 i

PBS

y

1V i

yi1H

Yi

2

yi2V yi2 H

Figure 4. Two-bit polarization-encoding of the multiple-valued SD digits.

4.1. TSD: DESIGN1 The TSD addition is a two-step process where the first step generates an intermediate transfer Ti +1 digit and an intermediate weight Wi digit that do not have the symbols 2 and 2; whereas the second step adds the digits Ti and Wi to produce the final sum. Table 1 lists the polarization-encoding of the two-step TSD addition. Studying Table 1(a) reveals that the minterms can be divided into three parts: (i) one group of minterms (the first eight entries) that have only V symbols; (ii) s second group of minterms (entries eighteen to twenty five) that have only H symbols; and (iii) a third group of minterms that have mixed V and H symbols. Therefore, a straight forward design method is to construct three channels or circuits to combine these minterms and produce the corresponding Ti +1Wi digit outputs using the 1 × 16 decoder as the basic building block. Figure 5 illustrates this design method for the TSD adder based on this minterms grouping. Figure 5(a) and Figure 5(b) illustrate the V-channel and the H-channel circuits, respectively; while the circuit in Figure 5(c) takes some outputs of the V- and the H-channel and combine them in order to produce the corresponding Ti +1Wi digits. Note that the output of the 1 × 16 decoders in these circuits are denoted by numbers in parentheses with a superscript letter

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xi1V

xi2V PC

PC

yi1V

yi2V

xi1H

PC

PC

PC

xi1V xi2V y i1V

T O A D

xi1V xi2V

T O A D

T O A D

xi1V xi2V y i1V xi1V xi2V y i1V

xi1V

V Light

xi1V xi2V y i1V

xi1V xi2V y i1V xi1V xi2V

xi1V

T O A D

T xi1V xi2V O A D

xi1V xi2V

T O A D

PC

T O A D

TiV+1

T O A D

T O A D

T O A D

WiV

(10)V

T O A D

TiV+1

(9)V (8)V

T O A D

xi1H

xi1H xi2 H

xi1H xi2 H

T O A D

T O A D

xi1H xi2 H y i1H

xi1H xi2 H yi1H 1H 2 H 1H i i i

x x y

H Light

x

1H i

(5)V

T O A D

1H 2 H i i

x x

T O A D

(5) V

T O A D

(8) V (0)

xi1H xi2 H yi1H

(4)V xi1H xi2 H

T O A D

xi1H xi2 H yi1H

(4)

V

x x y

(1)V (0)V

V i +1

T

(5) H

(8) V

T O A D

(8) H

PC

WiV

TiV

Ti +H1

WiV

(1)

H

( 6) H

(5) H

T O A D

T O A D

(1) H

T O A D

(4)

T O A D

H

Wi

WiV

(2) H

T O A D

(8) H

(1) H (4) H

(1) V (4) V

(c)

WiV T O A D

T O A D

Wi H

Si1V PC

H LIGHT

Ti H

PC

T O A D

H

(0) V T O A D

Ti +H1

(8) H

( 0) H

( 2) H

(0) H

(2) V

( 9)

Ti +H1

H

( 2) H 1H 2 H 1H i i i

(0) V T O A D

(10) H

( 4) H

T O A D

H

(1) V

T O A D

Wi H

(b)

Wi H

PC

T O A D

T O A D

(a) (2) V

T O A D

x x y

(6)V

T O A D

T O A D

1H 2 H 1H i i i

(2)V

xi1V xi2V y i1V

PC

PC

xi1H xi2 H y i1H

T O A D

T O A D

yi2 H

T O A D

xi1V xi2V y i1V

xi1V xi2V y i1V

yi1H

xi2 H

Si2V

Wi H T O A D

V LIGHT

T O A D

PC

S i1H PC

T O A D

Si2 H

(d)

Figure 5. Designed circuits of the TSD adder: DESIGN1: (a) Step 1 V-channel circuit; (b) Step 1 H-channel; (c) Step 1 HV-channel circuit; and (d) Step 2 circuit.

representing the polarization state. Figure 5(d) represents the designed circuit for the second step (Table 1(b)) of the adder that generates the sum digits. In this figure, a simplified 1 × 4 decoder is used. This adder design requires only 36 switches and it takes seven gate delay units for the addition. Note that this is a non-minimized TSD adder design, which can be improved by reducing both the numbers of TOAD switches and the delay units. Further, polarization converters (PC) are used before the control signals and continuous light sources are needed for the circuit to work properly.

4.2. TSD DESIGN2 This subsection demonstrates a second design method for the TSD adder which is not based on the 1 × 16

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TOAD decoder. When a closer look at the polarization-encoded TSD digits of Table 1(a) is carried out, it is observed that when the signals ( xi1H , xi2 H , yi1H , yi2 H ) are combined and produced no light output, then this indicates the V-channel entries in the table. In a similar way, the signals ( xi1V , xi2V , yi1V , yi2V ) indicate the H-channel entries of the truth table. Now, the combined signals of ( xi1V , xi2V , yi1V , yi2V ) can be used as IP input and the combined signals ( xi1H , xi2 H , yi1H , yi2 H ) can be used as CP input in one TOAD switch; while they can be used as CP and IP inputs in a second TOAD switch as illustrated in Figure 6(a) and Figure 6(b). This same method is used to distinguish the mix polarization channel as shown in Figure 6(c). T O A D

( xi1V + xi2V + yi1V )

T O A D

( xi1V + yi1V + yi2V ) ( xi1V + xi2V + yi1V + yi2V ) (x + y ) 1V i

PC

xi1V yi1V V i

(22) W

TiV+1

( xi2V + yi1V + yi2V )

PC

T O A D

(11)

( xi1H + xi2 H + yi1H + yi2 H )

PC

Wi

(x + y ) 1H i

1H i

PC

( xi1V + xi2V + yi1V + yi2V )

xi1H yi1H

T O A D

T O A D

TiV+1

(20) PC

Wi

PC

H

( 2 2) Wi H

Ti +H1

( xi2 H + yi1H + yi2 H )

( xi1H + xi2 H + yi2 H )

xi2 H yi2 H

(02)

H

PC

TiV+1

T O A D

(1 1)

( 1 0) Wi H

T O A D

T O A D

T O A D

Ti +H1

( 2 0) PC

WiV

(0 2 )

WiV

PC

Ti +H1

(a)

(b) V i

T

V i

W

PC

WiV

( xi1V + yi1V )

( xi2 H + yi2 H )

T O A D

V i

(2 1,1 2) W

Ti H

(x + y ) 2V i

T O A D

( 21,12) Wi H

(11) S i1V (01,1 1)

T O A D

T O A D

(01,10) Si2V

(Ti H + Wi H ) T O A D

( 1 1 ) S i1H (0 1,1 1 )

Ti H PC

( 1 1,1 1 )

(10,1 1 )

Wi H PC

Wi H

T O A D

TiV PC

( xi1H + yi1H )

2V i

(0 1 ) Wi H

( 1 2, 2 1 ) Ti +H1

T O A D

T O A D

T O A D

( xi1V + xi2V + yi2V )

xi2V yi2V

(10) WiV

T O A D

T O A D

( xi1H + yi1H + yi2 H )

(12,21) T 1V i

( xi1H + xi2 H + yi1H + yi2 H )

PC

(01) W

V i +1

T O A D

T O A D

( xi1H + xi2 H + yi1H ) V i

T O A D

T O A D

( 1 0,1 1)

(1 1,1 1) ( 0 1 , 1 0) S i2 H

(TiV + WiV ) (c)

(d)

Figure 6. Designed circuits of the TSD adder: DESIGN2: (a) Step 1 V-channel circuit; (b) Step 1 H-channel; (c) Step 1 HV-channel circuit; and (d) Step 2 circuit.

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On the other hand, the second step of the TSD adder is redesigned in order to eliminate the continuous H- and V-light sources in the circuits and at the same time maintain the same numbers of TOAD switches and the delay units as demonstrated in Figure 6(d). Furthermore, to clarify the generated outputs of each TOAD switch in the circuit, we posted the corresponding minterms at the output ports. This design method resulted in a better and a faster adder than DESIGN1. Thus, DESIGN2 requires only 24 gates and it takes only four gate delay units for the addition. Note that this design needs more beam combiners.

4.3. TSD DESIGN3 This proposed design method avoids using the 1 × 16 TOAD decoder, the polarization beam splitters that generate the H- and the V-channels, and the continuous H- and V-light sources. The TSD numbers { 2 , 1 , 0, 1, 2} are encoded by two digits X i = xi1 xi2 as {H0, 0H, 00, 0V, V0}. This imposes on the designer to carefully consider the state polarizations of both the control and the incoming pulse signals (CP and IP) for every possible combination digits of the TSD adder. In this regard, every signal in the TOAD switch (being an input or an output signal) has a trinary representation i.e. the signal can have vertically polarized, horizontally polarized, or no light. Exhaustive considerations of xi1 , xi2 , yi1 , yi2 or any combinations of these digits as being either CP or IP inputs along with polarization conversion, lead to DESIGN3 as shown in Figure 7. Again in this figure, the minterms of the adder of Table 1 are posted at the outputs of every TOAD switch. A huge improvement is achieved in this design since the number of gates is reduced by 70% to 11 and the delay is reduced by 72% to 2 units.

5. Polarization-Encoded TOAD-Based QSD Adder Circuits The quaternary literals { 3 , 2 , 1 , 0, 1, 2, 3} need a three-bit intensity encoding (light, no light encoding) for each signed-digit representation. However, a two-bit scheme is sufficient to represent the seven symbols when polarization-encoding is used such as= { 3 HH= , 2 H 0= , 1 0H = , 0 00 = , 1 0= V , 2 V= 0 , 3 VV HH}. In a similar manner to the TSD adder, the QSD addition is a two-step process where the first step generates an intermediate transfer Ti +1 digit that belongs to the set { 1 , 0, 1} and an intermediate weights Wi digit that belongs to the set { 2 , 1 , 0, 1, 2}; whereas the second step adds the digits Ti and Wi to produce the final sum. Therefore, a single polarized bit can be used to represent the transfer digits Ti +1 while two polarized-bit are needed to represent the weight digits Wi . xi1 yi1

xi1 yi2 T O A D

PC

(22, 2 2) Wi PC

(21, 2 1 ) Ti+1

(11,1 1 ) Ti+1 Wi

PC

xi1 xi2

T O A D

PC

xi2 yi2

PC

yi2

Wi

xi1 T O A D

(01,0 1 ) Wi

x

y

1 i

yi1

yi2

xi2 (a)

PC T O A D

(10,1 0) Wi

yi2

Ti Wi

Wi

yi1

xi1 1 i

(20, 20) Ti+1 PC

yi1 yi2

xi2 T O A D

T O A D

(02,02) Ti+1

xi1

xi2

(12,1 2) Ti+1

T O A D

yi1 T O A D

PC

T O A D

Ti+1

xi2 yi2

xi2 yi1

(2 1,21) Wi

T O A D

(11,1 1 ) Si1 (01,0 1 )

Wi Ti

( 1 2,12 )

PC

T O A D

Si2

(10,1 0) (b)

Figure 7. Designed circuits of the TSD adder: DESIGN3: (a) Step 1 circuit; (b) Step 2 circuit.

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5.1. QSD DESIGN1

This design uses the same approach as for DESIGN1 of the TSD adder where the 1 × 16 TOAD decoder constitutes the core part of the design. In this regard, polarization beam splitters are needed to generate the appropriate polarized CP. Table 2 lists the polarization encoding of the two-step QSD addition. Again, the entries in the table are classified as three groups that have only V symbols, only H symbols, and mixed HV symbols. Accordingly, the adder is designed in a straight forward manner and divided into three channels. The combinations of output digits of these channels will produce the appropriate sum. Figure 8 illustrates the circuits for this QSD adder. As it is expected, the circuit is more complicated having 54 TOAD switches and it takes eight gate delay units for the addition.

5.2. QSD DESIGN2 It can be shown that by following a similar procedure to that of DESIGN2 of the TSD adder of the previous section, a better and reduced number of gate count for the QSD adder can be obtained. However, in this subsection we will provide a much better QSD adder, which follows the design method used in DESIGN3 of the TSD adder. Figure 9 presents this design where the nonzero outputs of the minterms (the entries in Table 2) are realized individually and they are shown at the output ports of the TOAD switches. To illustrate the working mechanisms of this design, let us consider generating the output for the minterms 3 1 , which is encoded as xi1 xi2 yi1 yi2 = VV 0 H . This minterms is obtained using the circuit in the upper left corner in Figure 9(a). The input V . Thus the upper port of TOAD1 will have light to TOAD1 is yi2 = H and the control signal is xi2 + yi1 = H-light and it is used as input signal to TOAD2. Since the control signal of TOAD2 is xi1 = V , then the upper port of TOAD2 will have H-light, which is polarization converted to generate V-light as it is required. In a similar way, we can obtain the output of the minterm 31 . This QSD adder is denoted as DESIGN2 where the size is reduced by one half and the speed is increased by a factor of two compared to QSD DESIGN1 adder. The designed circuit requires only 27 gates and it takes four gate delay units for the addition.

(

)

6. Conclusions In this paper, designs of ultra-fast all-optical TOAD-based adders for multiple-valued SD numbers are reported. xi1V

xi2V

yi1V

PC

PC

yi2V PC

PC

xi1V xi2V yi1V

xi1V xi2V

xi1V

T O A D

xi1V xi2V

T O A D V Light

T O A D

T O A D

xi1V xi2V yi1V

xi1V xi2V yi1V

xi1V xi2V yi1V

T O A D

T O A D

T O A D

T O A D

(15)V (14)V (13)V (12)V (11)V (10)V

(9)V (8)V (7)V

xi1V

1V 2V T xi xi O A D

xi1V xi2V

T O A D

T O A D

xi1V xi2V yi1V xi1V xi2V yi1V

xi1V xi2V yi1V

xi1V xi2V yi1V

(a)

123

T O A D

T O A D

T O A D

T O A D

(6)V

(5)V

wi1V

(5) V (15) V

(11)V

(14)V

wi2V

(7 ) V (10)V

(3)V

V

(2)V

(13) (6)V

(1)V

(9)V

(0)V

TiV+1 TiV+1

V

( 4)

wi1V

TiV+1

PC

TiV+1

wi2 H

A. Hajjiah et al.

xi1H

xi2 H

yi1H

PC

PC

yi2 H PC

PC

1H 2 H 1H i i i

x x y T O A D

xi1H xi2 H

xi1H

T O A D

T O A D H Light

xi1H xi2 H yi1H

(14) H (13) H

T O A D

(12) H

T O A D

xi1H xi2 H yi1H

T O A D

xi1H xi2 H

(15) H

T O A D

(11) H

(9)

T O A D

xi1H xi2 H yi1H

H

x

T O A D

1H 2 H i i

T x x O A D

x x y

xi1H xi2 H yi1H

(6)

Ti +H1

(11) H

(14)

H

wi2 H

H

Ti +H1

(5) H T O A D

xi1H xi2 H yi1H

T O A D

xi1H xi2 H

T O A D

1H 2 H 1H i i i

wi1H

(15) H

(8) H (7 ) H

1H i

wi1H

(5) H

(10) H

(7 ) H ( 4) H (3) H

T O A D

xi1H xi2 H yi1H

(13)

(2) H

H

(6) H

(1) H T O A D

Ti +H1

(10) H

(9) H

(0) H

wi2V

PC H i +1

T

(b) (1) V (4) V

(1) H

wi2V

T O A D

(4) H

(3) H

(2) V

T O A D

V

wi2V

(12) H

(0)

H

(2) H

wi2 H

T O A D

(12)

1V i

w

(0)

V

T O A D

w

wi2V

(2) H (8) H T O A D

(1) V (4) V 1H i

T O A D

V

wi1H

T O A D

(1) V (4) V T O A D

(3) V

(2) V (8) V

(8) H

(1) H (4) H

wi2 H

T O A D

( 0) V

( 0) H

(8)

wi2 H

T O A D

wi1V

(1) H (4) H T O A D

PC

Ti +H1

( 0) V

T O A D

wi2V ( 0) H

PC

wi2 H

V i +1

T

(c) wi2V

TiV PC

S i2

PC

1

(11) S i

T O A D

w T O A D

S i1

(12)

wi1V 2H i

V Light

Ti H

PC

T O A D (10,12)

T O A D

(01)

T O A D

Ti H

T O A D

(10)

S i2 (01)

S i2

wi2 H

PC

S i2

PC

(1 1) S

T O A D

H Light

1 i

T O A D ( 1 0,1 2 )

PC

T O A D

TiV

S i1

wi1H

wi2V (0 1 )

T O A D

(1 2)

T O A D

T O A D

( 1 0)

S i2 (0 1 )

S i2

(d)

Figure 8. Designed circuits of the QSD adder: DESIGN1: (a) Step 1 V-channel circuit; (b) Step 1 H-channel circuit; (c) Step 1 HV-channel circuit; and (d) Step 2 circuit.

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A. Hajjiah et al. yi2

T O A D

T O A D

x

1 i

(3 1, 3 1)

PC

1

( xi2 + yi1 )

xi1

PC

yi2 T O A D

yi1 yi2

x x

Ti+1 ( xi + yi ) 1

1 i

y

2 i

T O A D

2

T O A D

(01,0 1 ) wi2

T O A D

xi2

( 23,2 3) wi2

(32, 3 2) wi2

(12,1 2) wi2

(02,02 ) wi2

T O A D

T O A D

( xi1 + yi1 )

1 i

(11,1 1 ) wi1 (10,1 0) wi2

PC

(20, 20) w

yi2

( yi1 yi2 ) 1 2 i i

xx

x

T O A D

xi1 yi1 PC

xi2

T O A D

y i1 y i2

2 i

PC

( xi2 yi1 )

T O A D

xi2 yi1 T O A D

1 i

T O A D

T O A D

( xi1 xi2 )

xi1 yi1

xi2 yi1 PC

T O A D

(21,2 1 )

wi2

T O A D

PC 1 i

T O A D

PC

yi1

(2 1,21) wi2

(x + y ) 2 i

wi1

2

T O A D

PC

x

1 i

PC

wi1

(33, 3 3)

T O A D

y

Ti+1 2 i

( xi1 yi1 )

Ti+1 (13,1 3) Ti+1

T O A D

(12,1 2 )

Ti+1 PC

x wi2

2 i

(03,0 3)

Ti+1

T O A D

T O A D

PC

T O A D

w Ti

(30, 3 0)

yi2

PC

(22,2 2 ) Ti+1

wi2 Ti (11,1 1 )

PC

S i2

Ti wi2 PC

T O (10,1 0) A D

(b)

Figure 9. Designed circuits of the QSD adder: DESIGN2: (a) Step 1 circuit and (b) Step 2 circuit.

125

PC

wi2 Ti+1

S i1

T O A D (01,0 1 )

Ti+1

(23,2 3) T O A D

(12,1 2 ) T O A D

wi1

(31, 3 1 ) Ti+1

(a) 1 i

PC

xi2

w

(32, 3 2 )

yi2

1 i

(1 3,1 3) wi1

wi2

A. Hajjiah et al.

Table 3. Comparison between the multiple valued SD circuit designs. Adder

TSD

QSD MSD

Unit delay

Gates count

Beam combiners

Polarization converters

DESIGN1

7

36

14

14

DESIGN2

4

24

26

12

DESIGN3

2

11

9

9

DESIGN1

8

54

20

18

DESIGN2

4

27

8

17

DESIGN2

4

10

11

7

These adders can be used as subtracters units once the augends are complemented and used as input digits to the designed adders. Three TSD (two QSD) circuits are designed and demonstrated. Table 3 summarizes the design elements of the proposed TSD and QSD adders as well as the most recently proposed MSD adder [24]. From this table, we can see that the QSD adder (DESIGN2) has the same speed (unit delay) as for the MSD adder while the gates count is higher as expected. Thus, this makes the proposed QSD adder an attractive circuit candidate knowing that the QSD number system (7 literals) provides more transmission information and more storage density than the MSD number system (3 literals). On the other hand, the TSD adder (DESIGN3) is two times faster than both the QSD and the MSD counterparts. While the TSD gates count is almost the same as for the MSD adder and about 60% less than the QSD adder. Consequently, these results make the TSD adder very attractive and a good candidate for future considerations in digital optical computing. It is worth mentioning that the previous proposed designs are theoretical. However, many theoretical simulations of similar TOAD-based circuits that prove their feasibilities were reported [25]-[28]. In addition, many reported works using TOAD switches demonstrated results with simulations using practical parameters or results from laboratories experimental data. Furthermore, note that when implementing multistage interconnection circuits using TOADs as the basic switch, one has to be aware of many practical issues such as synchronization and cascadability in addition to light intensity losses due to splitters/combiners, polarization, pulse duration, noise and others related issues [29]-[33].

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