Invited Paper
Direct comparison of GaN-based e-mode architectures (recessed MISHEMT and p-GaN HEMTs) processed on 200mm GaN-on-Si with Au-free technology Denis Marcona,*, Marleen Van Hovea, Brice De Jaegera, Niels Posthumaa, Dirk Wellekensa, Shuzhen Youa, Xuanwu Kanga, Tian-Li Wua, Maarten Willemsa, Steve Stoffelsa and Stefaan Decouterea a IMEC, Kapeldreef 75, B-3001, Leuven, Belgium *
[email protected]; phone +32 16 28 8404; www.imec.be
ABSTRACT Gallium nitride transistors are going to dominate the power semiconductor market in the coming years. The natural form of GaN-based devices is “normally-on” or depletion mode (d-mode). Despite these type of devices can be used in power semiconductor systems by means of special drivers or in a cascode package solution, yet the market demands for normally-off or enhancement mode (e-mode) devices. In this work, we directly compare and analyze the two most common approaches to obtain GaN-based e-mode devices: recessed gate MISHEMTs and p-GaN HEMTs. Both approaches have their pro’s and con’s as well as their critical process steps.. Keywords: GaN, e-mode, 200mm GaN-on-Si, Au free.
1. INTRODUCTION Gallium nitride (GaN) and Silicon Carbide (SiC) technologies are the most promising candidates for performance beyond the Si limits. Compared to SiC, which is available only as small diameter and expensive wafers, GaN combines high performance with a low cost thanks to the fact that GaN can be grown on large and inexpensive Si(111) substrates (GaN-on-Si) and it can be processed in a highly productive CMOS line by means of a Au free process [1]. The natural form of GaN-based devices is a normally-on or depletion mode (d-mode) device. Despite these type of devices can be used in power semiconductor systems by means of special drivers or in a cascode package solution, yet the market demands for normally-off or enhancement mode (e-mode) devices. Several approaches have been proposed to obtained e-mode devices and they can be clustered in two main families: recessed gate MISHEMTs and p-GaN HEMTs [2]-[6] The first approach (recessed gate MISHEMT) consists in (fully or partially) recessing the AlGaN barrier below the gate to interrupt the 2DEG thereby obtaining normally-off operation. This critical step is then followed by another key processing step that is the gate dielectric deposition. The second approach (p-GaN HEMT) consists in growing a p-type layer on top of the AlGaN barrier, deposition and patterning of a gate metal and then selective recessing the p-GaN layer over the AlGaN barrier. This gate metal layer forms a Schottky or an ohmic contact with the p-GaN layer, and, as a consequence, the potential in the channel at the equilibrium is lifted-up therefore realizing e-mode operation. In this case, the most critical steps consist in growing the pGaN layer and controlling the recess of the p-GaN layer over the AlGaN barrier in the access areas. In this work, both the technological challenges and the device performance of both e-mode technologies are directly compared and discussed.
2. SAMPLE DESCRIPTION The AlGaN/GaN heterostructures were grown by MOCVD on 200mm Si(111) substrate. The layer stack consisted of a thin AlN nucleation layer, 2.4-µm-thick (Al)GaN buffer layer to enable high voltage operations, 150-nm-thick GaN channel layer and 15nm AlGaN barrier layer. In the case of wafers for recess gate MISHEMT devices, the last top layer was 5 nm in-situ Si3N4 grown directly in the MOCVD reactor (Figure 1a); whereas in the case of wafers for p-GaN HEMTs the last top layer consisted of 70nm Mg-doped p-GaN ( Figure 1b). Devices were processed in imec’s 200mm state-of-the-art CMOS pilot line by means of a CMOS process-compatible Au-free process [1] Gallium Nitride Materials and Devices X, edited by Jen-Inn Chyi, Hiroshi Fujioka, Hadis Morkoç, Proc. of SPIE Vol. 9363, 936311 · © 2015 SPIE CCC code: 0277-786X/15/$18 · doi: 10.1117/12.2077806 Proc. of SPIE Vol. 9363 936311-1 Downloaded From: http://proceedings.spiedigitallibrary.org/ on 05/12/2015 Terms of Use: http://spiedl.org/terms
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Figure 1: Schematic cross-section of (a) epi-stack for MISHEMTs and (b) epi-stack for p-GaN HEMTs.
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Figure 2: Flow-chart of the processing steps for recess MISHEMT and p-GaN transistors.
3. DEVICE PROCESSING The process steps to obtain recessed gate MISHEMT or p-GaN HEMT are very similar with the exception of the gate formation (Figure 2), which represents the most critical step in both cases. 3.1 Processing of recessed gate MISHEMTs For recessed gate MISHEMTs, the processing starts by the deposition of an additional thick ex-situ Si3N4 passivation layer. Afterwards, N2 implantation is employed to destroy the 2DEG outside the device active area to obtain the deviceto-device isolation. Subsequently, in the gate region the Si3N4 layer is selectively etched over the AlGaN layer by means of a SF6-based chemistry. The e-mode operation is then realized by partially or fully recessing the AlGaN layer below
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the gate area. Indeed, below a certain critical thickness of the AlGaN layer, the 2DEG is not formed anymore, consequently interrupting the 2DEG below the gate and therefore realizing normally-off operation. At imec, we have investigated two methods to perform the critical processing step of recessing the AlGaN barrier (Figure 3). The first method consists in recessing the AlGaN layer by means of a time-controlled BCl3 low power plasma etch (Figure 3a). The etch rate of this process is 10nm/min. Unfortunately, we noticed that this type of process resulted in a large spread of the threshold voltage (within wafer and from wafer to wafer within the same lot) for the same targeted remaining AlGaN barrier (Figure 3a). This is because this process step is not self-limiting and the process window in this case is too tight for a robust manufacturable process. To overcome the limitation of the time-controlled etching, we have investigated an Atomic Layer Etching (ALE) process (Figure 3b). In this case, the AlGaN barrier is recessed by means of cycles of oxidation and etching. Indeed, each cycle consists in forming a thin oxide layer on top of the AlGaN barrier which is then removed by low power BCl 3 etching. With each cycle we controllably etch only 1.1nm of AlGaN and this resulted in a very small spread of the threshold voltage characteristics (Figure 3a).
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Figure 3: Schematic process flow for recessing the AlGaN barrier by means of (a) time-controlled recess and (b) atomic layer etching. The threshold voltage measured on transistors over different wafers and different lots is reported for the two processes. As discussed above, to obtain e-mode operation, the AlGaN barrier needs to be recessed at least below a critical thickness beyond which the 2DEG disappears thus enabling normally-off operation. The AlGaN barrier can be partially or fully recessed till the GaN channel.
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For manufacturability, full recess etching of the AlGaN barrier is preferred. Indeed, in this manner it is possible to obtain a robust process with a large process window overcoming issues such as spread in the threshold voltage caused by an non-uniform remaining AlGaN barrier layer over the wafer. In the case of partial AlGaN recess, the uniformity of the AlGaN barrier needs to be below 1nm to obtain a small spread of the threshold voltage over the wafer as few nm’s differences in the AlGaN barrier, from transistor to transistor, can result in significant different Vth. After a full recess of the AlGaN barrier a very tight Vth distribution was obtained, as is illustrated in (Figure 4).
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Figure 4: Ids-Vgs transfer characteristics distribution of fully recessed MISHEMTs processed on a 200mm GaNon-Si wafer. After having controllably recessed the AlGaN barrier, there is a need to deposit a gate dielectric in order to suppress the forward and reverse gate leakage current. The major challenge is to obtain a high quality gate dielectric with a both a low density of interface states and high bulk quality. Si3N4 grown in-situ in the MOCVD reactor on top of the AlGaN layer without any interruption of the epi-growth [7], results in an interface with AlGaN that is crystalline and of high-quality (Figure 5). This because in-situ Si3N4 results in a natural continuation of the AlGaN surface and it provides a nitrogen (N) termination of the AlGaN surface (Figure 5), that otherwise would result in Al or Ga dangling bonds. r
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Figure 5: In-situ MOCVD-grown Si3N4 passivation provides a N-termination of the AlGaN surface and it results in a crystalline interface with AlGaN.
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Unfortunately, in-situ grown Si3N4 can be used only in the access region of e-mode devices (i.e. to provide low surface trapping) and it cannot be used as a gate dielectric since it would require the re-introduction of the wafer in the MOCVD chamber after the gate recessing step described above. Consequently, the gate dielectric needs to be deposited ex-situ after the gate recessing. We have tested several gate dielectrics and deposition techniques to optimize for interface (Dit) and border defects [8]. The density of interface states (Dit) was compared for the following gate dielectrics and processes: Rapid Thermal Annealing-CVD (RTCVD) Si3N4, Atomic Layer Deposition (ALD) Al2O3 and Plasma-Enhanced ALD Si3N4. Despite the fact that RTCVD Si3N4 is grown at high temperature (~800°C) and consequently should result in high dielectric bulk quality, this gate dielectric showed a high Dit value (Figure 6). Similar results were obtained with ALD Al3O2. In contrast, PEALD Si3N4, resulted in a gate dielectric interface with the lowest defect density, with values close to the one of the MOCVD Si3N4 [8]. The deposition of Si3N4 by means of PEALD is performed by alternating cycles of SiH 4 and N2 plasma in an atomic layer deposition sequence, similar to as described in [9]. The initial N2 plasma cycle provides a plasma nitridation of the (Al)GaN surface, thus providing the needed N-termination described above. Recently, Chen et al. have successfully combined surface nitridation with different types of dielectrics such as Al2O3 [10] on MISHEMTs. This clearly indicates that surface nitridation is a promising technique to obtain low trap defect density at the (Al)GaN/dielectric interface.
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EC-ET(eV) Figure 6: Measure interface trap density (Dit) between (Al)GaN and the gate dielectric for 4different deposition techniques: RTCVD Si3N4, ALD Al2O3, PEALD Si3N4 and in-situ MOCVD Si3N4. An (Al)GaN/gate dielectric interface with low defect density is a key aspect for device stability [11] and for device performance, especially on e-mode devices [8]. Indeed, on d-mode devices the gate dielectric interface is far from the channel and therefore its influence on the device performance is limited, as shown in Figure 7. Instead, on e-mode devices, this interface is very close to the channel and therefore its influence is very strong: a reduced channel mobility results in a strong performance reduction (Figure 7) [8]. After the gate recess step and dielectric deposition, a TiN-based metal layer is deposited as a gate metal. Afterwards, ohmic contacts are formed by means of an optimized Au free process for ohmics with low contact resistance (Rc
