of a large transistor is highlighted. Next, the methodology of modeling distributed effects in transistors is discussed and validated. Following this, suitable simple ...
Distributed Effects in High Power RF LDMOS Transistors Kavita Goverdhanam, Wenhua Dai, Michel Frei, Don Farrell, Jeff Bude, Hugo Safar, M. Mastrapasqua, Tim Bambridge Agere Systems, 1110 American Pkwy, Allentown, PA 18109 RF transmission lines on performance aspects, such as, gain, output power, efficiency etc. in high power RF LDMOS amplifiers. The methodology to model and capture the distributed effects will be discussed. Suitable alternatives to mitigate power loss due to distributive effects in large transistors will be presented. Also, the contributions of the package to the overall device performance will be addressed.
I. INTRODUCTION To meet the needs of the 2.5G and 3G cellular and personal communication systems market, high power RF amplifiers with high output power, power gain, efficiency and linearity are required. Silicon technology has demonstrated that it can meet these needs, especially with the LDMOS [1], [2]. As performance aspects continue to improve, accurate and efficient models from the device level [3] to the package level [4] become very important for circuit designs. For high power devices where the device size increases, the distributed effects have a significant impact on the device performance. Due to this reason, modeling of distributed effects has received a lot of attention [5], [6]. This paper focuses on the effects of distributed metal lines on the performance of large transistors, using the RFLDMOS device as an example. To begin with, the effect of distributed metal topology on the output power of a large transistor is highlighted. Next, the methodology of modeling distributed effects in transistors is discussed and validated. Following this, suitable simple modifications to the metal topology for mitigating power loss in large transistors are proposed. The package plays a crucial role in the device performance and this will be shown as well.
with alternate topologies. To understand the mechanism of this power loss, a fullwave distributed Electromagnetics (EM) simulation of the device was undertaken. The topology of the transistor used in this study is shown in Fig. 1. In the figure, the gate and drain rails are metal sections in the lateral (x) direction. The gate and drain trees are metal lines that connect to the gate and drain rails respectively and extend in the longitudinal (y) direction. The gate/drain trees are repeated periodically in the lateral direction. The device investigated here has 21 gate/drain tree pairs. Fig.1 represents the active region as a single sub-device between the each gate-drain tree pair. In reality, the active device is distributed periodically in the longitudinal direction along every tree. The device has a total gate width of 126mm. A fullwave EM simulation of this device in the package environment showed a nonuniform distribution of voltage along the 21 trees. Fig.2. shows the amplitude of the voltage at the gate terminal along each of the 21 sequential trees for this device. Gate Pads
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Fig. 1: Schematic of Distributed Transistor Model Vg amplitude (V)
Abstract - This paper focuses on the effects of distributed
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II. POWER LOSS IN LARGE TRANSISTORS This study began with the investigation into an unexpected loss of over 20W of power observed in measurement of the performance of a large LDMOS transistor whose output power was calculated to scale to about 70W from the measurements of a scaled smaller device. While it was expected that there would be some deviation from this scaled value of 70W due to losses associated with distributed effects, the extent of losses observed for this particular device/topology was out of the range of what was observed for most other devices
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Fig. 2: Amplitude of gate voltage at 2.1GHz for the sequential trees of LDMOS device shown in Fig.1 From Fig. 2, it can be seen that the voltage peaks at the center and tapers off drastically at the edges. The net average output power density of this device is 0.41 W/mm. Thus for a device with a gate width of 126mm, the distributed model of the device with the package leads to approximately 50W power at 1dB gain compression (P1dB). The loss in power is also observed
from measurements. In the follow sections, the methodology of developing a fullwave packaged device model and solutions to mitigate the power loss are presented. III. METHODOLOGY OF DEVELOPING DISTRIBUTED TRANSISTOR MODELS Package Lead
Input Matching Capacitor BONDWIRES GATE PADS GATE RAIL
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Fig. 3: Schematic of packaged 60W RF LDMOS in the package environment To develop an accurate model of the transistor, the distributed metal lines of the device, as well as the package need to be modeled in addition to the active device. Fig. 3 shows a schematic of the distributed transistor in the package environment. The LDMOS device is enclosed in a metal-ceramic package which consists of a metal flange (package lead) and a dielectric (ceramic) frame. Bondwires are used to connect the transistor to the package. Input and output matching capacitors are used to tune to the desired resonance. A packaged fullwave distributed Electromagnetics (EM) model of the transistor is developed in the following manner: a) The passive distributed metal structure of the transistor layout is modeled using full wave EM simulations to account for the distributed effect of the metal topology. b) To connect the transistors along each of the gate/drain ‘trees’, internal hooks/ports are added to the structure used for the EM simulations. An electrothermal model is used to represent the active subdevices. Although active sub-devices are distributed in the lateral and longitudinal directions of the distributed metal lines, in the analysis of the complete 21 tree device, the longitudinal distributed effects of the active sub-devices along the device ‘trees’ are neglected and only the lateral distributed effects (along the gate and drain rails) are included so that the number of ports are limited. Hence just one set of internal ports is used for every gate-drain tree pair as seen in Figs. 1 and 3. It is
important to note that for the passive metal lines, both, the longitudinal and lateral distribution is taken into account. c) In order to connect the package to the distributed device, internal ports are also added at the gate and drain pads of the device. d) The distributed metal structure with internal ports is analyzed using a fullwave EM solver and the S parameter matrix resulting from the simulation is imported into a circuit simulator where the lumped active device model is attached at the appropriate ports to obtain the distributed device model. e) Finally the lumped package model which includes the bondwires, matching capacitors, package leads and other package parasitics is attached to the distributed device model at the circuit simulator level to obtain the packed distributed device model. For the fullwave EM simulations, the commercial 2.5D electromagnetic field simulator EMX [7] was used. For the circuit simulations and package modeling, ADS [8] was used. To validate the approximation of using a single pair of nodes to connect the active sub-device along the longitudinal direction in the gate/drain tree, a small device with a single gate-drain tree pair was analyzed using the distributed as well as lumped topologies for the active sub-device along the gate-drain tree and it was seen that the difference was negligible upto almost the 3rd harmonic of the device operating of 2.1GHz. IV. VALIDATION OF SIMULATION METHODOLOGY AND SIGNIFICANCE OF INCLUDING DISTRIBUTIVE EFFECTS IN DEVICE MODELING To validate the aforementioned methodology of developing the distributed model by analyzing the passive distributed metal sections using fullwave EM simulation and adding the equivalent model of the active device at the appropriate ports in the circuit simulation level, a small device which consists of a single gate-drain ‘tree’ of Fig.1 was selected. The small signal gain was measured for this device under forward bias condition. The measured data was compared with the data obtained from simulations using a lumped equivalent model of the transistor as well as simulations of a distributed transistor model. Fig. 4 shows a comparison of the small signal gain of the lumped, distributed and measured structures. The close agreement between the measured and distributed modeled data validates the simulation methodology. It is also seen from the analysis of this small device that including distributed effects has a significant impact on the accuracy of the models, especially at higher frequencies. As seen from the figure, not including the distributed effects predicts an Fmax of 14GHz. The distributed model predicts the correct Fmax of 6GHz.
active sub-devices accounts for self heating, heat distribution across the large device is not taken into account. Detailed analysis of the device has shown that the non-uniformity in voltage pattern is sufficient to account for a significant portion of the loss in power. Thermal effects/heat distribution across the device is not the dominant factor. This is supported by Fig.6 which shows that there is a nonuniform voltage distribution across the device even at low power where thermal effects are not significant.
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V. EFFECTS OF DISTRIBUTED LINES ON THE PERFORMANCE OF LARGE DEVICES
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This section focuses on the effects of distributed lines on large devices. In section II, it was mentioned that a 126mm LDMOS device which is designed to operate at 2.1GHz measured a loss in power of about 20W. From measurements of a small device, the scaled/lumped power should have been closer to 70W. Fig. 5 shows the modeled plot of gain and efficiency for this device as a function of the output power. The model was developed from the methodology discussed in section III. The optimal load for the device was obtained by performing loadpull simulations. The package model was set up for optimal performance. The simulations also assumed perfectly matched impedance on the source side. From Fig.5 it can be seen that the modeled P1dB for the aforementioned device is 51.9W. This loss of power is attributed largely to the distributed effects of the passive metal structure of the large transistor. Fig. 6 shows the amplitude of the voltage at the gate terminals along every ‘tree’ of the distributed transistor for a range of source powers, obtained from the distributed model.
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Fig. 5: Gain and PAE of the uncut 126mm device obtained using the distributed device model at 2.1GHz From this figure it can be seen that there is a significant variation in the input voltage seen by the devices in each tree. The nonuniform nature of this distribution was also confirmed from photoemission data of the device. The degradation in the device performance is attributed to this variation. It is important to note here that while the electro-thermal transistor model used to model the
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Fig. 6: Amplitude of Voltage at sequential gates for the uncut device for a range of source powers 60
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Fig. 4: Small Signal Gain of a Single ‘Tree’ Device
In order to mitigate the powerloss, the distributed metal structure topology is modified to reduce the nonuniformity in the input voltage pattern across the large device. Specifically the gate metal rail is cut into several sections and the distributed device simulations are repeated. Fig. 7 shows the log scale plot of the gain and PAE as a function of output power for the uncut, 1cut, 3cut and 4cut devices. It is seen from this plot that cutting the gate rail improves the device performance.
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Fig. 7: Gain and PAE of the uncut, 1cut, 3cut and 4cut devices at 2.1 GHz Table 1 summarizes the performance of the uncut device and devices with 1, 3 and 4 cuts in the gate rail. The table also includes measured data for 3 cut device. The data in the table is obtained by performing harmonic balance simulations after obtaining the ideal load from loadpull simulations. To begin with, the table
shows a P1dB of 70W for the lumped transistor model. However, due to distributed effects, specifically the non-uniformity of the signal at each of the device trees, the uncut device shows a P1dB of 51.9W. From the table it can be seen that cutting the gate rail improves the P1dB from 51.9W for the uncut device to 62.5W for the 4cut device. It can be seen that 1 cut gaterail only marginally improves the performance. The performance is improved considerably for the 3 cut device. 3-cut 4-cut Lumped Uncut 1-cut 3-cut (model) (model) (model) (model) (meas) (model) P1dB (W) Gain (dB) PAE (%)
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Table1: Summary of uncut and cut device performance
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As the number of cuts increases from 3 to 4, there is only a marginal improvement in the device performance from 61.3W to 62.5W as seen from the table. Having a package that would allow a very uniform distribution of signal to all the device trees would bring P1dB closer to that of the ideal lumped device. Fig. 8 compares the magnitude of the voltage seen at the sequential gate terminals for the packaged uncut, packaged 4cut and an uncut device with an ideal uniform feed (no package).
the voltage distributes almost evenly with each tree resulting in about 0.556 W/mm of net output power for the particular topology of the transistor used here. On the other hand, for the uncut device with the package, the power density reduces to about 0.410 W/mm. In the 4 cut device, the resulting 5 sections have 4, 4, 5, 4 and 4 gate-drain tree pairs. It can be seen from Fig.8 that this significantly reduces the non-uniformity in the voltage across the sequential trees. The power density for a packaged 4 cut device, with more uniform feed, increases to 0.49 W/mm. Thus for a device with 126mm gate width, the uncut distributed model of the device with a package leads to P1dB of 51.9W and the corresponding number for the 4cut device is 62.5W. This could be improved further by feeding a more uniform signal across the device with changes in the feed/package structure. VI. CONCLUSION In this paper, the impact of distributed metal lines on the performance of large transistors has been discussed. It has been shown that including distributed effects is important to predict the correct Fmax, gain, P1dB and PAE. Modifications in the distributed metal lines to improve device performance have been presented. Finally the contribution of the package to the overall device performance has been highlighted.
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The authors would like to thank Peter Gammel and Ozzie Lopez for their support of this work.
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Fig. 8: Gate Voltage Amplitude for uncut packaged, uncut non-packaged and 4cut packaged devices From Figs. 6 and 8 it is clear that large packaged transistors with continuous gate rails between fingers cause non-uniformity in the input signal pattern of the device and cutting the gate rail into smaller sections while keeping the same package reduces this nonuniformity. Detailed analysis of these structures has shown that the non-uniform distribution of voltage is always accompanied by a loss of power and deviation from the scaled power. Improving the uniformity of the voltage distribution reduces the power loss. If the uncut device with the long gate rail could be fed with a point source instead of the package with its inherent distributed effects, the voltage at the gate terminals would be more uniform as seen in Fig.8. For a uniformly fed uncut structure (no package effects)
REFERENCES [1] A. Wood, W. Brakensiek, C. Dragon, W. Burger, “120W, 2GHz, Si LDMOS RF Power Transistor For PCS Base Station Applications”, IEEE MTT-S Digest, 1998. [2] S. Xu, A. Shibib, Z. Xie, H. Safar, J. Lott, D. Farrell, M. Mastrapasqua, “High Performance RF Power LDMOSFET Technology for 2.1GHz Power Amplifier Applications”, IEEE MTT-S Digest, 2003. [3] J. Jang, O. Tornbald, T. Arnborg, Q. Chen, K. Banerjee, Z.Yu, R.Dutton, “RF LDMOS Characterization and its compact Modeling”, IEEE MTT-S Digest, 2001. [4] T. Liang, J. Pla, P. Aaen, M. Mahalingam, “Equivalent-Circuit Modeling and Verification of MetalCeramic Packages for RF and Microwave Power Transistors”, IEEE Trans on Microwave Theory and Tech., Vol 47, No. 6, June 1999. [5] S. Lee, P. Roblin, O. Lopez, “Modeling of Distributed Parasitics in Power FETs”, IEEE Trans on Electron Devices, Vol 49, No. 10, October 2002. [6] A. Abdipour, A. Pacaud, “Complete Sliced Model of Microwave FET’s and Comparison with Lumped Model and Experimental Results”, IEEE Trans on Microwave Theory and Tech., Vol 44, No. 1, January 1996. [7] Integrand Software, Inc., EMX [8] Agilent Technologies, ADS
