Drosophila Food Search algorithms for High Resolution Loser-Take-All (LTA) VLSI circuit for Compression. 1
P.K.Paul, 2K.L.Baishnab, 3Naushad laskar, 4Sourav Nath 1,2,3,4 National Institute of Technology Silchar Assam 1 2
[email protected],
[email protected],
[email protected],
[email protected]
ABSTRACT:
A high resolution CMOS LoserTake-Circuit (LTA) is designedin emulating biological features. Drosophila Food Search (DFO) algorithmshas been employed in order to optimize multi-objective circuit parameters.Simulation is carried out in MATLAB using DFO and Particle Swarm Optimization (PSO) and a comparison is taken out.Based on the result derived using DFO, further Simulation is carried out in CADENCE software to validate the earlier results. Simulation results demonstrate circuit possesses high resolution 0.5mV. Keywords: Drosophila Food search algorithms, Analog Circuits, Selective attention in biological systems. I.
INTRODUCTION:
Unlike digital camera, the visual data in vertebrate retina are processed in parallel through fluid mediabefore reaching to visual cortex for high level features detection, Kareemet al. [2].Visual information has been used in biological systems in order to control the motion of the eyes for tracking stimuli,Meadet al.[3] Douglas et al [4], Koch et al. [5]. The main principle behind the faster response time of biological system is to single out a specific input or region of interest (ROI)
of inputs by eliminating redundant information which eventually compress the input data to greater extend. In order to accomplish such a task, a set of analogcircuits proposed by several authors [6-13]could be used to emulate the biological behaviour in silicon. One of such popular circuits is CMOS Loser-Take-All circuit (LTA) has been proposed by several authors. All the circuits proposed in literatures have certain level of limitations in terms of resolution, speed, slew rate, response time etc.The proposed LTA circuit has been designed to meet the requirement of high resolution, where even though sample values are closely located, after competition eventually only winner survive and loser perish to ground. The circuit could be extensively used to compress data like data compression in selective attention system prevailing in biological system. The majority circuits in literatures is in current mode [6-7], where a current-voltage converter is required to interface with digital processor, which invites more bulkiness of a system. For visual image processing where, compression is essential for reducing the image transmission or storage costs for broad areas of applications such as high-definition television, teleconferencing, remote sensing,
radar, sonar, computer communication, facsimile transmission, and image data-base management. The alternative solution is to design voltage mode WTA circuits, which could be easily interfaced with external processing unit without current to voltage converter. Choi et al. [11]Donker et al.[12]introduced simplified voltage mode WTA circuit which requires only one clock cycle to evaluate The WTA circuit proposed by “Choi”, having two portions, first portion converts input voltage to current and second portion converts current to voltage. To achieve high speed, all the transistors are kept in saturation region at the cost of some other specifications like resolution and SNR. In order to improve resolution, several similar WTA circuits are to be cascaded. The resolution of the circuitis found to 100mV, without cascading and 15mV on cascading. Down the line Donckeret al.[12],Rahaman et al. [13] generalized the circuit, in contrast with a standard OTA along with additional steering circuit. The obtained resolution and delay is however not satisfactory and necessitated further research to improvise the resolution and delay to meet the target goal.In order to achieve high resolution an appropriate scientific tools is necessary to pick up appropriate circuit parameters. Traditional circuit design is happened in two stages Binkly [14-15]. . The first stages identify an optimal point through theoretical analysis based of output requirements, whichdiffer from the actual design point. The second stage is happened with optimizing design parameters, which is more laborious and time consuming. With the growth of VLSI industry and in order to catch the competitive market,the power, silicon area
and other aspects of a circuit are paramount. So silicon industry is migrating its design paradigm from traditional approach to scientific approach, where an appropriate optimization tools areused to tune all circuit parameters simultaneously to reach to a global solution, unlike traditional design where a single parameter is swept at a time.The circuit design using optimization techniques would have more precision, less error and more robustness.There are several optimization techniques are available is literature, which are broadly (i) un-constrain and (ii) constrains optimizations. Sumani et al. [16], Miloslav KUBAŘ et al. [17], YAN et al. [18] has elaborated and analyzed several algorithms in context to analog circuit design. It has been observed that evolutionary algorithms have received lots of attention in recent past. The optimization of analog circuit has taken a momentum with the adoption of genetic algorithm (GA), and waswidely used quite some time; however over the time it is observed that it did not have a favourable outcome, in terms of computation and convergence for certain applications. Very recently Das et al. [14] proposed Drosophila food search algorithms, and also demonstrated, it is superior to PSO under certain circumstances. In this paper DFO is adopted and illustrated that DFO is better algorithms to optimizing LTA circuits. III.
PROPOSED LOSER ALL CIRCUIT
TAKE
The block diagram of a LTA is illustrated in Figure-1, where two/more competing cells, are connected to a common point Each circuit has excitory and inhibitory, which boost up
the speed and resolution based on target requirement..
Figure-1 Block diagram of LTA
M2 of the winner cell. Similarly grow up at lower input voltage.
will also
At the end of transient phase the cell Vx Vcom t t with higher will survive and rest will die out. The winner cell is forced at the positive rail voltage and all other cells at the negative rail voltage and realised as winner-take all (WTA).
A. Working Principle Coming to the circuit in Figure 2, input stage of each cell is a common source amplifier, composed of transistors M6 and M7 and transistors M1, M2 and M3 form a voltage to current converter followed by a current comparator at the output with transistor M4 and M5. Current mirror form by the transistors M3, M5 and M8 to provide higher current to push the output voltage further. The cell having lower will have higher and vice versa, since input transistor M6 acts as a resistance in triode region. The transistor M8 acts as excitory it boosts up (voltage at Node-1) recursively with the action current mirror formed with the transistor M3. The transistor M9 acts as inhibitory as it sucks a part current from the transistor M1. So , = + . Again transistors M1 and M3 form current mirror, so
(
=(
) )
. Similarly the final output is
push up to rail to rail since transistor M5 formed current mirror with M3. Finally with the action of current comparator formed by M4 and M5, the output is boosted up. In the transient phase, the common point terminal will follow the drain voltage of the transistor
Figure 2 Proposed LTA circuit with transistor M6 and M7 form input stage, whereas transistor M1-M3 form voltage to current conversion and finally transistor M4 and M5 form current comparator which bring out rail to rail output. Transistor M3, M4 and M8 form current mirror.
B. Design and Analysis So in order to achieve better resolution (minimum ∆ ), higher gain is desirable. Coming to the proposed circuit as shown Figure-2, it is seen that it has, the circuit has three portions, 1stportion input stage is a common source amplifier and second stage amplifies current and third stage again amplifies voltage. Combining all three stages
total gain achieved 70dB as shown in the Figure-4. Since the proposed circuit is composed of with front end common source formed by transistor M6 and M7, followed by several other stages. The thermal noise (ignoring flicker noise), generated at the transistors M6 and M7 plays major role to the total input referred noise power. 2 4KT gm7r072 gm6r062 2 1 gm6 3 Vn,in2 4KT 2 2 gm7 r07 3 gm7 gm72 In order to keep the transistor at different level of inversion, as mentioned, the transistors in the circuit are biased properly with the following node voltages as shown in TABLE-A TABLE-A Biasing voltages of different node points of the circuit quoted as model 2 Node Point
Voltage (mV)
Node Point
Voltage(mV)
Node-1
687
Node-3
1314
Node-2
589
Node-4
869
The objective of the proposed design is to improve resolution, which could be expressed as V sat Rail to rail output V sat Vin Av Av
Where is the gain of LTA. So in order to have better resolution (minimum ∆ ), the gain needs to be maximized. The small
signal voltage gain of the proposed circuit is approximated,
Av
g m 2 g m1 g m 3 X g ds1
gm 4 (5.4) gds 4 gds5
ID2 ID1 ID8 ID4 nUT IC20.5 IC11 nUT IC10.5 IC11 nUT IC80.5 IC81 nUT IC40.5 IC41
ID1 ID4 ID5 10L110L4 10L5
Where
g m stands for trans-conductance
and g ds = output conductance. g ds 4
ID4 I D4 V4 10 L4
T Vx G1 1 exp Node1 T Vcom G2 1 exp Node 2 Where G1 and G2 is DC voltage at Node-2, is the RC time constant at Node-1 and Node-2 respectively, T is the time period of input signal. In transient state both and rises exponentially, and rate of exponential growth depends on RC time constant respectively.
and
During unsupervised parallel competition of several cells, both and of every participating cells rises exponentially, cell Vx Vcom t t with higher will survive and
rest all will be set to ground. So cell with lowest will have highest and survived as a single winner after competition and realised as a Loser–Take-All (LTA). From 5.4 and using In order keep transistor at different place, in order meet the requirement of high gain and latency an objective function is derived. The objective function =
−
4.6 .
where PM, are Phase margin and Gain of the circuit. The range of value of K= 10-5-1030 . From small signal analysis of the circuit, SR and G are calculated in terms of circuits parameters. Finally simulation is carried out using Drosophila food search algorithms using C++ and results are illustrated in TABLE-II. TABLE-II Parameters Q
PSO 0.8
DFO 0.97412
IC2
0.29337
0.228639
IC7 IC4 IC5 IC6 IC8 ID2 ID3 ID5 ID6 ID7 ID8 L2 L4 L5 L6 L7 L8 W2 W4 W5 W6 W7 W8 Cgs6 PM L3 K Error function(f)
0.82568 56.7850 1.45250 1.28923 0.51456 1.124e-05 0.954472 1.42745 0.823419 0.563472 0.1256e-05 4.63981e-5 8.3518e-05 0.94512e-05 2.42335e-06 3.55236e-06 1.37834e-05 6.44815e-05 8.33567e-04 9.45524e-05 3.24678e-06 7.88449e-05 12.7256e-05 7.2971e-11 45 4.22745e-005 10-5-10-30 1.8577e-08
0.240796 23.8584 4.25150 0.676454 0.126233 0.000145643 1.14548e-005 4.9835e-005 0.000184972 0.000185858 0.000189335 1.12302e-007 1.37835e-007 1.48847e-007 1.79595e-007 1.23556e-007 1.98627e-005 1.25555e-005 3.51291e-005 1.23563e-005 6.19583e-006 2.97864e-005 0.000361441 3.09002e-013 63.935007 1.72916e-007 10-5-10-30 8.56243e-025
IV.SIMULATION AND ANALYSIS Based results obtained using DFO, circuit simulation is carried out in Spectra CADENCE 180 nm technology. There are several analysis tools in cadence, using which different features of the circuit could be evaluated. The Figure-3 demonstrates DC analysis, of two competing cells, where input voltage of cell-1( ) is varied keeping other cell fixed at 1.3V. As along as Vin1
