Dual Z-Source Inverter With Three-Level Reduced ... - IEEE Xplore

IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 43, NO. 6, NOVEMBER/DECEMBER 2007

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Dual Z-Source Inverter With Three-Level Reduced Common-Mode Switching Feng Gao, Student Member, IEEE, Poh Chiang Loh, Member, IEEE, Frede Blaabjerg, Fellow, IEEE, and D. Mahinda Vilathgamuwa, Senior Member, IEEE

Abstract—This paper presents the design of a dual Z-source inverter that can be used with either a single dc source or two isolated dc sources. Unlike traditional inverters, the integration of a properly designed Z-source network and semiconductor switches to the proposed dual inverter allows buck–boost power conversion to be performed over a wide modulation range, with three-level output waveforms generated. The connection of an additional transformer to the inverter ac output also allows all generic wyeor delta-connected loads with three-wire or four-wire configuration to be supplied by the inverter. Modulationwise, the dual inverter can be controlled using a carefully designed carrier-based pulsewidth-modulation (PWM) scheme that will always ensure balanced voltage boosting of the Z-source network while simultaneously achieving reduced common-mode switching. Because of the omission of dead-time delays in the dual-inverter PWM scheme, its switched common-mode voltage can be completely eliminated, unlike in traditional inverters, where narrow commonmode spikes are still generated. Under semiconductor failure conditions, the presented PWM schemes can easily be modified to allow the inverter to operate without interruption, and for cases where two isolated sources are used, zero common-mode voltage can still be ensured. These theoretical findings, together with the inverter practicality, have been confirmed in simulations both using PSIM with Matlab/Simulink coupler and experimentally using a laboratory-implemented inverter prototype. Index Terms—Buck–boost, dual inverters, reduced commonmode (RCM) switching, three-level inverters, Z-source inverters.

I. I NTRODUCTION

T

HE CONNECTION of two traditional voltage-source inverters (VSIs) to form a three-level inverter has been reported for use in either open-end-winding [see Fig. 1(a)] [1] or dual-voltage [Fig. 1(b)] [2] induction motor drives. Compared with the popular neutral-point-clamped (NPC) inverter,

Paper IPCSD-07-024, presented at the 2006 Industry Applications Society Annual Meeting, Tampa, FL, October 8–12, and approved for publication in the IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS by the Industrial Power Converter Committee of the IEEE Industry Applications Society. Manuscript submitted for review November 11, 2006 and released for publication May 5, 2007. F. Gao is with the Power Engineering Design Laboratory, School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore 639798 (e-mail: [email protected]). P. C. Loh and D. M. Vilathgamuwa are with the School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore 639798 (e-mail: [email protected]; [email protected]; [email protected]). F. Blaabjerg is with the Institute of Energy Technology and the Faculty of Engineering, Science, and Medicine, Aalborg University, 9220 Aalborg, Denmark (e-mail: [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TIA.2007.908173

Fig. 1. Schematics of dual inverter supplying motors with (a) open-endwindings and (b) two stator windings per phase.

a dual inverter does not suffer from neutral-point voltage unbalance, does not require any clamping diodes, and has more redundant states that can be used for equalizing the switching losses among the numerous controlled switches. It therefore offers an attractive topological alternative for implementing a three-level inverter, and a number of pulsewidth modulation (PWM) algorithms have been reported since then. As for other three-level inverters (or VSIs in general), the dual inverter is expected to suffer from some performance limitations. First, it generates a significantly large common-mode voltage when controlled using traditional carrier disposition or space vector modulation (SVM) schemes. This generated common-mode voltage is known to cause premature motor bearing failure in variable-speed ac drives, and its induced leakage current to ground can cause electromagnetic interference and false tripping of ground current protection relays. Baiju et al. [1] and von Jauanne and Zhang [2] have proposed a number of PWM schemes as possible solutions for modulating the dual inverter with reduced common-mode (RCM) switching. Specifically, in [1], a modified SVM scheme that attempts to avoid the alternating common-mode voltage in open-end-winding induction motors has been proposed. Although effective, this scheme gives rise to a larger current ripple because of the requirement to switch both full bridges in the dual inverter discontinuously. Similarly, in [2], a scheme

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Fig. 2. Two-level Z-source inverter (a) topology and (b) continuous modulation sequence.

that requires only a simple reassignment of gating signals to the two full bridges has been reported, but its application is only limited to dual-voltage induction motors with six phase windings. The second constraint that limits a dual inverter (or any VSI, in general) is its ability to perform only voltage-buck power conversion, unless a front-end dc boost converter is added to the inverter dc link or other boosting techniques are used. Among the recent single-stage topological solutions proposed, the Z-source boosting technique has attracted some attention with its relatively simple configuration, involving only the connection of an X-shaped LC impedance network [see Fig. 2(a)] for an illustration of the Z-source network) between the input dc source and a standard full-bridge inverter. Using the Z-source network, inductive boosting of the inverter dc link can be achieved by simply turning on both switches from the same inverter phase leg (implementing a shoot-through state) without damaging semiconductor switches. These performance features have been confirmed experimentally in [3]–[7], but to date, Z-source power converter research has mainly focused on two-level VSI [3]–[6] and current-source [7] topologies. Its extension to a three-level NPC inverter has only been recently attempted in [5], [8], and [9], with a number of issues still left unresolved when other three-level inverter topologies (including dual inverter) are used.

With the two preceding limitations in view, this paper proposes the development of a dual Z-source inverter topology, implemented through the cascading of two Z-source VSIs and a three-phase transformer (see Fig. 3). The designed inverter can be used with either a single dc source [Fig. 3(a)] or two isolated sources [Fig. 3(b)] and can supply all generic delta- or wye-connected loads. Connecting a controlled switch with an antiparallel diode Sw1 (and Sw2 when two isolated sources are used) in series with the input source, instead of only a single diode in a traditional Z-source VSI [3]–[6], the proposed dual inverter supports bidirectional power conversion and avoids erroneous voltage boosting caused by diode reverse biasing under light-load conditions. Modulationwise, the integration of a carefully designed PWM scheme to the inverter allows it to operate with equal voltage boosting across its two dc links and three-level RCM switching. For the latter feature, because the proposed dual inverter does not require dead-time protection, its terminal common-mode voltage can be completely eliminated, unlike that of a traditional three-level inverter, where common-mode spikes are still observed. In addition to its good performance under the normal operating mode, the proposed inverter with many redundant states can function equally well under the semiconductor failure mode, provided that its PWM scheme is appropriately reconfigured to formulate alternative state

GAO et al.: DUAL Z-SOURCE INVERTER WITH THREE-LEVEL REDUCED COMMON-MODE SWITCHING

Fig. 3.

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Schematics of dual Z-source inverter with (a) a single dc source and (b) two isolated dc sources.

sequences. For verifying these theoretical findings and the practicality of the proposed dual Z-source inverter, PSIM (with Matlab/Simulink coupler) simulation and experimental testing on a laboratory prototype are performed, with their captured results presented in Section VI. II. R EVIEW OF T WO -L EVEL Z-S OURCE VSI The two-level Z-source VSI, shown in Fig. 2(a), was first proposed in [3], with its operating modes broadly classified under shoot-through and nonshoot-through states. When a shoot-through state is commanded, both switches from a selected phase leg are turned on to initiate inductive boosting of the Z-source impedance network, and when the inverter is commanded to revert back to a nonshoot-through state (representing any of the six active or two null states commonly assumed by a traditional two-level inverter), this stored inductive energy, together with energy from the dc source, is released to the external ac loads, resulting in a boosting of the

inverter ac terminal voltage. Mathematically, the boosted dc link voltage Vi and peak ac output voltage Vo are expressed as [3], [4] Vi = Vdc /(1 − 2T0 /T ) = BVdc V0 = M {Vi /2} = M BVdc /2

(1)

where T0 represents the total shoot-through time in a switching period T , B(≥ 1) is the boost factor, and M (≤ 1.15) is the modulation index commonly used for traditional inverter modulation. Clearly from (1), the ac output voltage depends on both B and M , and can be boosted by increasing B above unity or stepped down by holding B at unity and decreasing M . The two aforementioned operating modes are subsequently shown in [6] to be part of a larger pool of operating modes that can be assumed by a Z-source inverter with low Z-source inductance. To demonstrate the existence of additional operating modes, it is assumed that the inverter is initially in a

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nonshoot-through state, with its dc input current expressed as idc = iL1 + iC1 = iL1 + (iL2 − iin ) = 2iL − iin > 0 (see Fig. 2(a) and assuming that iL1 = iL2 = iL for a symmetrical Z-source impedance network). With idc maintained above zero, input diode D continues to conduct until iL falls toward 0.5iin , during which idc = 0 (implying that iL = 0.5iin ), and the diode stops conduction. The inverter then enters a new operating mode, which can give rise to a nonlinear voltage boost, a distorted ac current, and a more complex set of transfer gain equations [6]. In passing, it is commented that, in [6], the new operating mode is further divided into two submodes, depending on whether the inverter is in a null (iin = 0) or active state [iin = ioX , X = a, b, or c, in Fig. 2(a)], but this distinction and other operating modes identified in [6] are not the theme of this paper and are therefore not further discussed here. The new operating mode previously described is obviously not solely linked to the low-inductance condition studied in [6] but can equally occur under low-modulation and light-load conditions, during which the “ripple-to-average” ratio of iL is high. To avoid entering this operating mode and its associated complications, the Z-source inductance must be large (implying that iL ≈ IL , where IL is the average inductive current), and M must satisfy a constraining inequality derived as follows under the worst case operating condition:  IL ≥ 0.5Iin  Vdc Idc = Vdc IL = 3Vo Io cos ϕ/2  Iin = Io (worst case condition) ⇒

3Vo Io cos ϕ 1 ≥ Io 2Vdc 2

M≥

2 3 cos ϕ

(2)

where cos ϕ is the load power factor; Vo and Io are the peak ac output voltage and current, respectively; and M = Vo /(Vdc /2) gives the modulation ratio under the low-output-voltage condition without boosting (implying that Vi = Vdc ). Regardless of the operating mode assumed, for voltage boosting, it is necessary to insert shoot-through states to the inverter state sequence, which traditionally consists of only active and null states. These shoot-through states can be inserted either at the start and end of every switching cycle [3] or in between active/null states, as documented in [4] and [5]. The latter approach is illustrated in Fig. 2(b) and is selected for this paper, because it requires a minimum of six device commutations per switching cycle, with no additional switching loss introduced. As an illustrative example for demonstrating the inverter commutation sequence, the first shoot-through state inserted to the “null-to-active {100}” transition in Fig. 2(b) is analyzed, where it is deduced that the transition of phase A from 0 to 1 can be effected by switching the {SA, SA } of phase A [see Fig. 2(a)] from {0, 1} → {1, 1} → {1, 0}. Clearly, the underlined intermediate state corresponds to the shorting of phase A and can be introduced by simply advancing the turning on of SA by T0 /3T with respect to the turning off of SA , without additional commutation needed. The only constraint that must be observed while inserting these shoot-through states is that the active states must stretch over the same time durations as for a conventional VSI when the reference phasor is orientated at the same angular position. This implies that shoot-through

states can only be inserted within null intervals, and because they give rise to the same set of zero line voltages, the external ac loads will see the same normalized voltage-second average when supplied by either the Z-source or traditional inverter. As expected, the shoot-through state insertion can physically be implemented by the explicit placement of space vectors in a designed SVM scheme. Alternatively, the shoot-through states can implicitly be inserted by using six modified sinusoidal references (two references per phase) in a carrier-based implementation. These references (normalized to a peak of unity) are mathematically expressed in Vmax(SX) = Vmax +Voff +T1 Vmid(SX) = Vmid +Voff +T2 Vmax(SY ) = Vmax +Voff +T2 Vmid(SY ) = Vmid +Voff +T3 Vmin(SX) = Vmin +Voff +T3 , Voff = −0.5(Vmax +Vmin ); Vmin(SY ) = Vmin +Voff +T4 T1 = −T4 = T0 /T ;

T2 = −T3 = T0 /3T

{X, Y } = {1, 4}, {3, 6}, or {5, 2}

(3)

and are later used for controlling the proposed dual Z-source inverter to take advantage of its autostate-sequencing and placement features. III. T OPOLOGICAL D ESIGN OF THE D UAL Z-S OURCE I NVERTER A dual Z-source inverter can be constructed by cascading two Z-source full bridges with either a single dc source or two isolated sources, as shown in Fig. 3(a) and (b), respectively. The six ac outputs of the two full bridges (labeled as inverters 1 and 2 in Fig. 3) can then be connected to the six terminals of an open-end-winding induction motor or a dual-voltage motor with six stator phase windings, similar to the conventional dual topologies shown in Fig. 1. Instead of these motor loads, an ac transformer can also be connected to the dual-bridge ac outputs, as illustrated in Fig. 3. In that figure, the transformer secondary windings are wye connected to give a neutral-star point, allowing it to feed wye- or delta-connected generic loads with three- or four-wire configurations. Connecting in this way also results in a set of three-phase three-level switching waveforms for powering the external loads. The dual Z-source inverter therefore offers an alternative way of implementing a three-level inverter without using clamping diodes, unlike the Z-source NPC inverter reported in [5]. The only requirement of the dual inverter is the need for a three-phase output transformer, which, although will increase the system cost, but has the advantages of providing electrical isolation and inductive filtering of the inverter output voltages. Alternatively, a centertapped current-balancing inductor can be used, but this option is more appropriate for paralleling the inverter bridges in an interleaved manner for reducing the overall inverter output current ripple [10], rather than for doubling the voltage intensity attained by the proposed series cascading of bridges using a transformer. In addition to being able to power all generic loads, the dual Z-source inverter can also boost its output voltage by using either one or two X-coupled Z-source impedance networks (see


Fig. 4.

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Logic for controlling Sw1 and Sw2 (see Fig. 3).

Fig. 2), and a carefully designed PWM scheme. A notable feature in the Z-source networks used here, as compared to those used in [3]–[6], is that the series input diode D used in Fig. 2(a) is now replaced by an insulated-gate bipolar transistor (IGBT) with an antiparallel diode (see Sw1 and Sw2 in Fig. 3). This replacement is required to provide for bidirectional power conversion and, more importantly, to avoid erroneous voltage boosting under low-modulation and light-load operating conditions, during which the input source becomes disconnected from the Z-source network if only a diode is used (⇒ reversebiased diode, as discussed in Section II). With the controlled IGBT switch added, a slight hardware modification is needed to provide for a seventh gating signal for driving Sw1 [an eighth signal for Sw2 is also needed if two isolated sources are used as in Fig. 3(b)], in addition to the six independent signals needed for driving the 12 switches in the two full bridges with RCM switching. (It is shown later that both full bridges use the same signals in a rotated sequential manner, and therefore, only six gating signals are needed for the resulting inverter.) This seventh gating signal can be generated using the simple logic structure shown in Fig. 4, where SX and SX (X = A, B, or C) are the gating signals for controlling the upper and lower switches of each phase leg in a full bridge. Briefly, when a phase leg shoot-through is commanded (e.g., SA = 1 and SA = 1), a turn-off signal is automatically sent to Sw1 (and Sw2), whose antiparallel diode is naturally reverse biased, to disconnect the source from the dc Z-source network. On the other hand, when in a nonshoot-through active or null state, an on signal is sent to Sw1 (and Sw2) for connecting the source to the Z-source network. Together, these operating states result in voltage boosting with bidirectional power conversion ability. Alternatively, if only unidirectional dc–ac operation is required, Sw1 (and Sw2) can be turned off permanently during voltage boosting (shoot-through states are inserted), with only its antiparallel diode now connected in series between the input source and Z-source network. This diode would then naturally reverse bias in a shoot-through state and start conducting immediately upon the reentry into a nonshoot-through state. On the other hand, when voltage boosting is not required (no shoot-through state is inserted), Sw1 can still remain off until a boundary limit below which unintended reverse biasing of the antiparallel diode of Sw1 occurs. Depending on whether one or two dc sources are used, this boundary limit assumes different expressions, which can conveniently be derived using the same

Fig. 5. Space vector diagrams of full-bridges in dual inverter.

mathematical procedure documented in Section II. Specifically, when a single dc source is used, with its dc link powering six phase legs (two for each phase) simultaneously as in Fig. 3(a), the inverter dc link current and peak ac output voltage under RCM switching are expressed as iin = iin1 + iin2 ≤ 1.5Io √ and Vo = ( 3/2) ∗ M ∗ Vdc , respectively, assuming √ that a 1:1 transformer is used. (Note that the factor of ( 3/2) in the expression of Vo is introduced by the three-level RCM PWM, as explained in [11] and [12].) Using these operating expressions and the inequality of IL ≥ 0.5Iin , the boundary constraint that M must satisfy is derived as √ 3 1 3 3 M cos ϕ ≥ ⇒ M ≥ √ . (4) 2 2 3 cos ϕ Alternatively, when two isolated sources are used as in Fig. 3(b), the two full bridges in the dual inverter virtually have no direct connection between their dc links, and therefore, their dc link currents are expressed as iin1 = iin2 = iin ≤ Io . In addition, with √ RCM switching, their peak output voltages are expressed as ( 3/2) ∗ M ∗ Vdc . Noting also that the ac output power is now equally shared between the two full bridges and considering the constraining inequality of IL ≥ 0.5Iin , the boundary limit imposed on M with two isolated dc sources is derived as √ 3 3 4 M cos ϕ ≥ 1 ⇒ M ≥ √ . (5) 4 3 3 cos ϕ

IV. M ODULATION OF A D UAL Z-S OURCE I NVERTER W ITH T HREE -L EVEL RCM S WITCHING Fig. 5 shows the space vector diagrams of the two full bridges in a dual Z-source inverter, with each having six active states and two null states, which are labeled as SV0 to SV7 for inverter 1 and SV0 to SV7 for inverter 2. With the two

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Fig. 8. State combinations 1 and 2 for controlling dual Z-source inverter with three-level reduced common-mode switching.

Fig. 6. Combined space vector diagram of dual inverter.

Fig. 7. Reduced common-mode voltage space vectors of dual inverter.

full bridges working simultaneously, the resulting dual inverter can output 64 switching states, arranged into 19 space vectors, as shown in Fig. 6. (The vertices of the hexagon are labeled with the first number representing the inverter 1 switching state and the second number representing the inverter 2 switching state.) Obviously, the 19 vectors form a three-level inverter vector diagram with numerous redundant states, which should be optimally used for equalizing voltage boosting and switching losses between the two full bridges. Being a three-level inverter, it is also possible to restrict the dual inverter to switch only among the seven space vectors shown shaded in Fig. 7 so as to generate zero common-mode voltage. Note that, in [11], this vector restriction has been used for controlling a conventional three-level NPC inverter, but it is subsequently discussed in [12] that common-mode spikes can still appear during dead-time intervals introduced for inverter protection. Fortunately, for

the dual Z-source inverter, dead-time delays are not required, and therefore, a more thorough elimination of common-mode voltage can be expected. Another feature noted in Fig. 7 is that there are more redundant states associated with the seven permitted vectors (two for each vertex and eight at the origin), as compared to those of an NPC inverter. The presence of these redundant states allowed Baiju et al. [1] to classify them into two state-sequencing options using either states {13 , 15 , 35 , 31 , 51 , 53 , 11 , 33 , 55 } or states {64 , 24 , 26 , 46 , 42 , 62 , 22 , 44 , 66 }. These statesequencing options result in zero alternating common-mode voltage at each of the two full bridges, in addition to the elimination of overall common-mode voltage at the output terminal of the dual inverter. The combined effect is a further reduction of bearing and leakage currents induced through electrostatic coupling when the inverter is used for driving an open-end-winding induction motor [1]. Although both techniques function well, they generally result in discontinuous PWM switching at one of the full bridges, which, at most, would result in a larger current ripple at the inverter dc link when the dual inverter is powered by a single dc source [see Fig. 3(a)]. On the other hand, when a second isolated source is added [see Fig. 3(b)], discontinuous switching would result in unbalanced voltage boosting across the two Z-source networks, giving rise to a distorted output and an incorrect voltage transfer gain. For controlling the dual Z-source inverter in this paper, an alternative carrier-based approach with continuous PWM switching and rotated sequential order is therefore recommended. For a simple illustration of the modulation principle, Fig. 8 shows a possible state combination (labeled as combination 1 in the figure) with two state sequences for controlling the two full bridges in a dual Z-source inverter. Comparing the sequences, it is noted that the second sequence is derived from the first by logically shifting the state bits toward the left. These bit-shifted sequences then result in a set of normalized inverter phase voltages VAN , VBN , and VCN , which are calculated, e.g., as VAN = 1 − 0 = 1, VBN = 0 − 1 = −1, and VCN = 0 − 0 = 0 for the first active states {100} and {010} in both sequences. Further calculation of the common-mode voltage as Vcm = (VAN + VBN + VCN )/3 gives rise to a value of zero, implying a complete elimination of common-mode voltage. The same computation can be performed for the remaining switching states, with the same conclusion anticipated. In addition to eliminating common-mode voltage, it is anticipated that the previously described bit-shifting process can spontaneously


TABLE I REDUCED COMMON-MODE STATE SEQUENCES

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states in one sequence, with active states in the other sequence, is observed. This overlapping is expected to result in a finite common-mode voltage, an unwanted voltage-second error, and unbalanced voltage boosting when two isolated dc sources are used, as in Fig. 3(b). Equal sizing and precise timing of shootthrough intervals are therefore important and can automatically be implemented by using a single standard VSI modulator for generating inverter 1 state sequences in Fig. 8 (for example) and subsequently using the left or the right bit-shifting technique previously described for generating inverter 2 state sequences. V. O PERATION OF THE D UAL Z-S OURCE I NVERTER U NDER THE S EMICONDUCTOR F AILURE M ODE Note from Fig. 3 that the dual Z-source inverter uses two times more semiconductor switches than a traditional two-level inverter, and therefore, a study of the inverter operational modes under semiconductor failure (open and short circuit) conditions is deemed necessary and is pursued in this section. A. Dual Z-Source Inverter With Single DC Source

Fig. 9. State combinations for controlling dual Z-source inverter: (a) correct and (b) incorrect shoot-through state sizing.

minimize the high-frequency zero-sequence current circulating between the two full bridges. As mentioned in [10], a highfrequency current ripple will circulate around the inverter when one full bridge is in null {111} while the other is in null {000}. Fortunately, this scenario does not happen when the proposed bit-shifting scheme is used (see Fig. 8), and therefore, no high circulating current will flow. (A low-frequency circulating current caused by parametric mismatch can sometimes flow as well, but it can be easily removed by using an appropriately designed zero-sequence controller [10], which is beyond the scope of this paper.) Obviously, a second state combination can also be derived by shifting the state bits toward the right (labeled as combination 2 in Fig. 8). Performing these bit-shifting methods for a full fundamental cycle then gives rise to the complete list of state combinations shown in Table I. Regardless of which combination is used, it is important to maintain equal total shoot-through durations per switching cycle in the two PWM sequences for controlling the two full bridges so as to equalize the amount of voltage boosting between them. In addition, each shoot-through state in both sequences must start and end at the same time instants so as to avoid imperfect common-mode cancellation when active states are assumed. For an illustration, Fig. 9(a) and (b) shows examples of correct and incorrect shoot-through state sizing, respectively. In Fig. 9(b), overlapping of shoot-through

For the dual Z-source inverter with a single dc source shown in Fig. 3(a), failure in any of the semiconductor switches would result in the inverter losing its RCM switching ability. However, through appropriate reconfiguration of its gating signals, the inverter can still operate with the correct voltagesecond average generated, albeit at a higher output current ripple and a finite common-mode voltage. For illustration, it is assumed that the upper phase-A switch of inverter 2 is open circuited (short circuited), and to continue generating the correct ac output voltage, inverter 2 should be forced into null state {000}({111}), as illustrated in Fig. 10(a), while inverter 1 remains pulsewidth modulated at a high switching frequency, similar to a traditional two-level inverter. (Clamping of phases B and C of inverter 2 to other voltage levels is also possible with the same operating principles applicable to those cases.) Doing so allows the dual inverter to continue functioning like a two-level inverter, with voltage boosting still achievable by inserting shoot-through states to the state sequence of inverter 1 for short-circuiting the single Z-source impedance network. With voltage boosting √ still achievable, the dip in peak output voltage level from ( 3/2) ∗ B ∗ M to B ∗ M/2 due to the malfunctioning of inverter 2 can simply be compensated by lengthening the shoot-through time of inverter 1. Although capable of generating the correct output voltagesecond average, the reconfigured dual inverter now has the lower undotted ends (a2, b2, and c2) of the primary windings of the transformer connected to the negative (positive) dc rail of both full bridges since inverter 2 is in state {000}({111}). The three-phase voltages that appear across the primary and secondary windings of the transformer are therefore equal to the pole voltages of inverter 1 measured with respect to the negative (positive) dc rail and have a finite common-mode voltage since only inverter 1 (effectively, a two-level inverter) is pulsewidth modulated. With two or more switches failing, the solution previously proposed is equally applicable, as long as the failed

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Fig. 10. Suggested configurations of dual Z-source inverter under upper switch open-circuit fault of inverter 2 when supplied by (a) a single power source and (b) two isolated power sources respectively.

(short-circuited) switches are not from the same phase leg. For the latter case of a shoot-through fault, external breakers would be needed for isolating the shorted phase leg so as to allow the inverter to revert back to a nonshoot-through state. B. Dual Z-Source Inverter With Two DC Sources With the addition of a second power source to the dual inverter in Fig. 3(b), an obvious advantage to most readers is the possibility of providing uninterruptible power flow when one of the sources fails. In addition to this obvious advantage, a less noticeable advantage with the inverter in Fig. 3(b) is its ability to operate with RCM switching and the correct voltage-second average generated during semiconductor failure fault. As an example, it is again assumed that the upper phase-A switch of inverter 2 is open-circuited (short-circuited), and inverter 2 is forced into null state {000}({111}). With inverter 2 now in

the null state {000}, as shown in Fig. 10(b), the undotted ends (a2, b2, and c2) of the primary windings of the transformer are connected together through the negative dc rail of inverter 2. This effectively creates a floating star point S (noting that inverters 1 and 2 are independently supplied by their own power sources) whose potential Vstar is expressed as Vstar =

Sa + Sb + Sc Vi 3

(6)

where Sa , Sb , and Sc represent the phase-leg switching functions of inverter 1. The “phase-to-star-point” voltage VX (X = a, b, or c) appearing across the primary and secondary phase windings of the transformer is then expressed as (assuming a 1 : 1 turn ratio) VX = SX Vi − Vstar .

(7)


Fig. 11. Simulated (top to bottom) line voltage, phase voltage, common mode voltage and line current of dual Z-source inverter with a single dc source, T0 /T = 0 and M = 0.4.

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Fig. 12. Simulated (top to bottom) line voltage, phase voltage, common mode voltage and line current of dual Z-source inverter with two isolated dc sources, T0 /T = 0 and M = 0.4.

Using (7), the generated common-mode voltage Vcm is expressed as Vcm =

Sa + Sb + Sc Va + Vb + Vc = Vi − Vstar = 0 3 3

(8)

whose value is zero. With two or more switches failing in a full bridge, the preceding scheme with one full bridge forced to a null state is not feasible if the failed (short-circuited) switches are from the same phase leg or are tied to different dc rails. An alternative scheme is to turn on both switches from any phase leg of the faulted bridge (not required if two switches from the same phase leg fail short circuit), with its dc source disconnected using external breakers to avoid large but gradual discharge current from the Z-source capacitors. Doing so again creates a floating transformer star point at the faulted bridge for forcing the output common-mode voltage to zero. Another point to note with the previously described common-mode elimination method expressed by (6)–(8) is that its level of effectiveness is closely linked to the formation of a balanced floating star point on the primary side of the transformer. Any unbalance in the three-phase transformer impedances is expected to give rise to slight common-mode residue, which conceptually cannot be eliminated by modifying the inverter modulation state sequences, but definitely is acceptable for a short time duration before the planned servicing of the faulty system. This degradation in performance is fortunately not experienced by the inverter during normal (nonfaulted) operating conditions since its three-phase terminal voltages are intentionally shaped by the modulation bit-shifting process described in Section IV, which has no reliance on the formulation of a balanced floating star point. VI. S IMULATION AND E XPERIMENTAL R ESULT The designed dual Z-source inverter with three-level RCM switching is first verified in simulation using PSIM with a Matlab/Simulink coupler. For verifying the dual Z-source inverter performance under light-load condition, Figs. 11 and 12

Fig. 13. Simulated (top to bottom) line voltage, phase voltage, common mode voltage and line current of dual Z-source inverter with a single dc source, T0 /T = 0.3 and M = 0.7.

show simulated results for a single-source inverter and a dual-source inverter, respectively, with M = 0.4, T0 /T = 0, cos ϕ = 0.99, and Vdc = 30 V. (According to (4) and (5), the boundary constraints for both inverters are given as M ≥ 0.58 for the single-source case and M ≥ 0.78 for the dual-source case.) Clearly, with the proper control of switches Sw1 and Sw2 in Fig. 3, both inverter configurations function well, with the correct voltage-second average generated and common-mode voltage eliminated. Next, with a finite shoot-through interval added (T0 /T = 0.3 and M = 0.7), Figs. 13 and 14 show the boosting of inverter output voltage to a pulse height of ≈75 V from an input voltage of only 30 V while still maintaining a zero common-mode voltage with no erroneous spikes [boost factor of B = 75/30 = 2.5, which agrees well with that calculated using (1) (B = 1/(1 − 2 ∗ 0.3) = 2.5)]. For demonstrating the failure handling capability of the proposed dual Z-source inverter, Fig. 15 shows the waveforms obtained when the inverter is powered by only a single dc

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Fig. 14. Simulated (top to bottom) line voltage, phase voltage, common mode voltage, and line current of dual Z-source inverter with two isolated dc sources, T0 /T = 0.3 and M = 0.7.

Fig. 15. Simulated (top to bottom) line voltage, phase voltage, common mode voltage, and line current of dual Z-source inverter with a single dc source, T0 /T = 0.3 and M = 0.7.

source and has a short-circuited upper switch in one of the two full bridges. Under this condition and according to Section V-A, the faulted bridge is forced to null state {111}, giving rise to an inverter phase voltage that is equal to the pole voltage of the functioning full bridge. The resulting phase voltage therefore switches between zero (negative dc rail) and +Vdc (positive dc rail), with a finite common-mode voltage generated. With a second dc source added, Fig. 16 shows the corresponding waveforms obtained under the same failure condition. As anticipated, the phase voltage waveform is now improved, and the common-mode voltage is forced to zero. These observations clearly demonstrate the improved ride-through capability of the dual Z-source inverter when a second dc source is used for powering the inverter. The optimally tuned inverter design previously simulated is then experimentally tested using a constructed laboratory prototype switched at 5 kHz. The prototype is assembled using Semikron IGBT modules (rated at 600 V and 50 A) and

Fig. 16. Simulated (top to bottom) line voltage, phase voltage, common mode voltage, and line current of dual Z-source inverter with two isolated dc sources, T0 /T = 0.3 and M = 0.7.

Z-source parameters of L1 = L2 = 6.3 mH (rated at 5 A) and C1 = C2 = 2200 µF (rated at 400 V), and is controlled digitally using a digital signal processor with an embedded PWM peripheral and an erasable programmable logic device. The assembled inverter is then connected to a star-connected RL load (R = 15 Ω, L = 6.3 mH), which is deemed appropriate since the theme of this paper is simply to test the open-loop modulation concepts proposed for controlling the dual Z-source inverter. With this arrangement, the inverter common-mode voltage is measured by probing the load star point and the transformer secondary neutral, which is labeled as “N ” in Fig. 3. Note that, in practice, the load star point might not be available, meaning that a better way of measuring the commonmode voltage is to simultaneously probe the three secondary voltages of the transformer (with respect to N ) and then sum them to give a measure of the common-mode voltage. For this paper, the latter approach is not adopted because of the limited number of scope channels available and the intention of displaying four distinct waveforms in all figures included herein. To demonstrate the inverter performance under the same lowmodulation condition simulated earlier (M = 0.4, T0 /T = 0, and Vdc = 30 V), Figs. 17 and 18 show the corresponding experimental waveforms, which again show the proper functioning of the proposed dual inverter, with zero commonmode voltage generated. Proceeding further to demonstrate its voltage boosting feature, Figs. 19 and 20 show the captured experimental waveforms with T0 /T = 0.3 and M = 0.7. These results again show the boosting of voltage by a factor of 2.5, with the inverter common-mode voltage kept at zero at all instants. (The measured value of ≈7 V and occasional short peaks in the figures can safely be ignored after taking the physical measurement noises into consideration.) To verify the semiconductor failure handling capability of the dual inverter, Fig. 21 shows the captured experimental waveforms, with two dc sources powering the dual inverter; as predicted, the generated current waveform still remains sinusoidal, but


Fig. 17. Experimental (top to bottom) line voltage 100 V/div, phase voltage 50 V/div, common mode voltage 20 V/div, and line current 1 A/div of dual Z-source inverter with a single dc source, T0 /T = 0 and M = 0.4, time scale: 5 ms/div.

Fig. 18. Experimental (top to bottom) line voltage 100 V/div, phase voltage 50 V/div, common mode voltage 20 V/dic, and line current 1 A/div of dual Z-source inverter with two isolated dc sources, T0 /T = 0 and M = 0.4, time scale: 5 ms/div.

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Fig. 20. Experimental (top to bottom) line voltage 200 V/div, phase voltage 100 V/div, common mode voltage 20 V/div, and line current 3 A/div of dual Z-source inverter with two isolated dc sources, T0 /T = 0.3 and M = 0.7, time scale: 5 ms/div.

Fig. 21. Experimental (top to bottom) line voltage 150 V/div, phase voltage 100 V/div, common mode voltage 20 V/div, and line current 2 A/div of dual Z-source inverter with two isolated dc sources under switch fault, T0 /T = 0.3 and M = 0.7, time scale: 5 ms/div.

unbalanced (quite practically common), which, according to Section V-B, is expected to give rise to a slight common-mode residue. [For clarity, it is briefly mentioned here that the line and phase voltages shown in Fig. 21 switch correctly with three and five distinct voltage levels, respectively, in accordance to the theoretical expressions derived and expressed in (6)–(8)]. VII. C ONCLUSION

Fig. 19. Experimental (top to bottom) line voltage 200 V/div, phase voltage 100 V/div, common mode voltage 20 V/div, and line current 3 A/div of dual Zsource inverter with a single dc source, T0 /T = 0.3 and M = 0.7, time scale: 5 ms/div.

unfortunately, its generated common-mode voltage is not reduced to the extent shown in Fig. 20 (≈20 V in Fig. 21, as compared to ≈7 V in Fig. 20). The reason for this is the three-phase transformer impedances are found to be slightly

This paper has presented the design of a dual Z-source inverter with three-level RCM switching and voltage buck–boost capability. The designed inverter can be supplied by either a single dc source or two isolated sources and can be connected to any generic loads with three- or four-wire configuration. With controlled switches added to the inverter source ends, the proposed inverter can perform bidirectional power transfer and can operate well under both low- and high-voltage operating conditions. Controlwise, the inverter can be easily controlled using state sequences with shoot-through states inserted and can smoothly ride-through semiconductor failure, with the correct voltage-second average and zero common-mode voltage

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generated. These findings, together with the practicality of the inverter, have been verified experimentally in this paper using an implemented laboratory prototype. R EFERENCES [1] M. R. Baiju, K. K. Mohapatra, R. S. Kanchan, and K. Gopakumar, “A dual two-level inverter scheme with common mode voltage elimination for an induction motor drive,” IEEE Trans. Power Electron., vol. 19, no. 3, pp. 794–805, May 2004. [2] A. von Jauanne and H. Zhang, “A dual-bridge inverter approach to eliminating common-mode voltages and bearing and leakage currents,” IEEE Trans. Power Electron., vol. 14, no. 1, pp. 43–48, Jan. 1999. [3] F. Z. Peng, “Z-source inverter,” IEEE Trans. Ind. Appl., vol. 39, no. 2, pp. 504–510, Mar./Apr. 2003. [4] P. C. Loh, D. M. Vilathgamuwa, Y. S. Lai, G. T. Chua, and Y. Li, “Pulsewidth modulation of Z-source inverters,” IEEE Trans. Power Electron., vol. 20, no. 6, pp. 1346–1355, Nov. 2005. [5] P. C. Loh, F. Gao, F. Blaabjerg, S. Y. Feng, and K. N. Soon, “Pulsewidth-modulated Z-source neutral-point-clamped inverter,” IEEE Trans. Ind. Appl., vol. 43, no. 5, pp. 1295–1308, Sep./Oct. 2007. [6] M. Shen and F. Z. Peng, “Operation modes and characteristics of the Z-source inverter with small inductance,” in Proc. IEEE IAS Annu. Meeting, 2005, pp. 1253–1260. [7] P. C. Loh, D. M. Vilathgamuwa, C. J. Gajanayake, L. T. Wong, and C. P. Ang, “Z-source current-type inverters: Digital modulation and logic implementation,” IEEE Trans. Power Electron., vol. 22, no. 1, pp. 169– 177, Jan. 2007. [8] P. C. Loh, S. W. Lim, F. Gao, and F. Blaabjerg, “Three-level Z-source inverters using a single LC impedance network,” IEEE Trans. Power Electron., vol. 22, no. 2, pp. 706–711, Mar. 2007. [9] P. C. Loh, F. Blaabjerg, and C. P. Wong, “Comparative evaluation of pulsewidth modulation strategies for Z-source neutral-point-clamped inverter,” IEEE Trans. Power Electron., vol. 22, no. 3, pp. 1005–1013, May 2007. [10] L. Asiminoaei, E. Aeloiza, J. H. Kim, P. Enjeti, F. Blaabjerg, L. T. Moran, and S. K. Sul, “An interleaved active power filter with reduced size of passive components,” in Proc. IEEE APEC, 2006, pp. 969–976. [11] H. Zhang, A. Von Jouanne, S. Dai, A. K. Wallace, and F. Wang, “Multilevel inverter modulation schemes to eliminate common-mode voltages,” IEEE Trans. Ind. Appl., vol. 36, no. 6, pp. 1645–1653, Nov./Dec. 2000. [12] P. C. Loh, D. G. Holmes, Y. Fukuta, and T. A. Lipo, “Reduced commonmode modulation strategies for cascaded multilevel inverters,” IEEE Trans. Ind. Appl., vol. 39, no. 5, pp. 1386–1395, Sep./Oct. 2003.

Feng Gao (S’07) received the B.Eng. and M.Eng degrees in electrical engineering from Shandong University, Jinan, China, in 2002 and 2005, respectively. He is currently working toward the Ph.D. degree in the Power Engineering Design Laboratory, School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore. From September 2006 to February 2007, he was a Visiting Scholar with the Institute of Energy Technology, Aalborg University, Aalborg, Denmark, where he worked on the development of multilevel Z-source inverters. Mr. Gao was the recipient of the IEEE Industry Applications Society Industrial Power Converter Committee Prize for a paper published in 2006.

Poh Chiang Loh (S’01–M’04) received the B.Eng. (Hons) and M.Eng. degrees from the National University of Singapore, Singapore, in 1998 and 2000, respectively, and the Ph.D. degree from Monash University, Clayton, Australia, in 2002, all in electrical engineering. During the summer of 2001, he was a Visiting Scholar with the Wisconsin Electric Machine and Power Electronics Consortium, University of Wisconsin, Madison, where he worked on the synchronized implementation of cascaded multilevel inverters and reduced common-mode carrier-based and hysteresis control strategies for multilevel inverters. From 2002 to 2003, he was a Project Engineer with the Defence Science and Technology Agency, Singapore, managing major defense infrastructure projects and exploring new technology for defense applications. Since 2003, he has been an Assistant Professor with the School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore, and in 2005, he was Visiting Staff, first at the University of Hong Kong and then at Aalborg University, Aalborg, Denmark. Dr. Loh is currently serving as an Associate Editor for the IEEE TRANSACTIONS ON POWER ELECTRONICS. He was the recipient of two IEEE Industry Applications Society Industrial Power Converter Committee Prizes for papers published in 2002 and 2006.

Frede Blaabjerg (S’86–M’88–SM’97–F’03) received the M.Sc.EE. and Ph.D. degrees from Aalborg University, Aalborg, Denmark, in 1987 and 1995, respectively. He was with ABB-Scandia, Randers, Denmark, from 1987 to 1988. He became an Assistant Professor in 1992, Associate Professor in 1996, and Full Professor of power electronics and drives in 1998 at Aalborg University. In 2006, he became the Dean of the Faculty of Engineering, Science, and Medicine, Aalborg University. He is also with the Institute of Energy Technology, Aalborg University. He is the author or coauthor of more than 300 publications, including the book Control in Power Electronics (Academic Press, 2002). In recent years, he has held a number of chairman positions in research policy and research funding bodies in Denmark. He is an Associate Editor for the Journal of Power Electronics and the Danish journal Elteknik. His research interests are power electronics, static power converters, ac drives, switched reluctance drives; modeling, characterization, and simulation of power semiconductor devices; wind turbines; and green power inverters. Dr. Blaabjerg is an Associate Editor for the IEEE TRANSACTIONS ON I NDUSTRY A PPLICATIONS and the IEEE T RANSACTIONS ON P OWER ELECTRONICS. In 2006, he became the Editor-in-Chief of the IEEE TRANSACTIONS ON POWER ELECTRONICS. He was the recipient of the 1995 Angelos Award for his contribution in modulation technique and control of electric drives; an Annual Teacher Prize at Aalborg University in 1995; the Outstanding Young Power Electronics Engineer Award from the IEEE Power Electronics Society in 1998; the C.Y. O’Connor Fellowship 2002 from Perth, Australia; the Statoil Prize in 2003 for his contributions to power electronics; the Grundfos Prize in 2004 for his contributions in power electronics and drives; and five IEEE Prize Paper Awards during the last six years.

D. Mahinda Vilathgamuwa (S’90–M’93–SM’99) received the B.Sc. and Ph.D. degrees in electrical engineering from the University of Moratuwa, Moratuwa, Sri Lanka, and Cambridge University, Cambridge, U.K., in 1985 and 1993, respectively. In 1993, he joined the School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore, as a Lecturer, and he is currently an Associate Professor. He has published more than 100 research papers in refereed journals and conference proceedings. His research interests are power electronic converters, electrical drives, and power quality. Dr. Vilathgamuwa is the Cochairman of the Power Electronics and Drives Systems Conference 2007.