The influence of RTA (Rapid Thermal Anneal) treatment on. MOS radiation hardness is demonstrated and compared with classical furnace treatment. In the case ...
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IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 42 NO. 6, DECEMBER 1995
EFFECT OF RAPID THERMAL ANNEALING ON RADIATION HARDENING OF MOS DEVICES 0.Flament and J.L.Leray CEA, Centre d'Etudes de Bruyeres-Le-ChAtel,BP12, F91680, Bruy&res-Le-Ch&el,France F. Martin, E.Orsier, J.L.Pelloie, R.Truche CEA/DTA/LETI, BPSSX, F3 8041, Grenoble, France and R.A.B. Devine CNETKNS, BP98, Meylan, F38243, France Abstract
oxygen [7,8], and (ii) thermal and mechanical stress effects [3,5] explain the experimental data.
The influence of RTA (Rapid Thermal Anneal) treatment on MOS radiation hardness is demonstrated and compared with classical furnace treatment. In the case of the RTA, the oxide trapped charge is found to depend on : (i) the anneal temperature as expected. Data are in good agreement with a recently developed model of oxygen out-diffusion, (ii) the location across the wafer with a radial dependence. Results could be related to stress induced by thermal gradient.
I. INTRODUCTION Rapid thermal annealing @TA) has become a common tool for various steps in VLSI processing, such as shallow diffusion profiles, silicide formation and annealing and doped-glass reflow for device planarization. The low thermal budget involved in the RTA process is the key for achieving vertical impurity profile scaling for submicron bipolar and CMOS devices. The duration of heat cycles is typically a few tens of seconds, with temperatures in the range of 800120OOC and cooling rates from 50°C/s to 100°C/s. Since the thermal history of the gate oxide after growth is one of the key parameters for total dose hardness [l-61, including such a RTA step in a given process requires careful attention. It has been demonstrated in previous studies that annealing of a gate oxide in a furnace at temperatures greater than about 925OC can sigmficantly degrade the radiation hardness [ 1,3-41. The present work specifically concerns the RTA anneal step and its effect on the radiation response on MOS devices, since this question has not been clearly approached. We investigate the application of RTA in a CMOS process technology. This paper describes: (i) the effect of RTA on total dose response and non-uniformity of the threshold voltage shift AV,, and (ii) the effect of temperature on the results. The mechanisms responsible for hardness degradation that have been proposed on the basis of (i) out-diffusion of 0018-9499/95$04.00
11. EXPERIMENTAL METHODS a-Irradiafions: All irradiations were performed with a 10 keV X-ray source (ARACOR Model 4 100) at a dose rate of 1 krad (SiOz)/s. A positive (NMOS) or negative (PMOS) 2.8 h4Wcm electric field was applied on the gate oxide of the devices during irradiation. b-RTA equipment: The equipment used in this study is a commercial RTA system (Addax company, France) with two sides of linear lamps. The temperature is monitored with an optical pyrometer. No radiation shields are placed in the processing chamber, so temperature losses are not compensated in this study. c-Devices: The CMOS devices used in this study are manufactured using a hardened process already developed in the series of DMILL technology [9], which is essentially a BiCMOS-JFET process with (i) 1.2 pm epitaxial layer on SIMOX substrate, and (ii) lateral trenches outside a guard band ring surrounding NMOS transistors. For this technology, the standard gate oxide thickness is 18 nm with polysilicon-TaSi2 gates.
111. RESULTS
A. GlobalResults Concerning V,, and V,,
6) Influence of Channel Length Devices with channel lengths of 0.8 to 25 pm and widths of 25 pm were studied. Various lengths were used to measure a possible geometrical effect and to assess uncertainty on results. Figure 1 shows that no signifcant effect of the transistor size is observed, for various sizes of transistor measured on a same die, which is different than previous reported work [lo]. In this first experiment, RTA (l0SOoC, 10s) is compared to furnace anneal (85OoC, 30 min.). RTA appears to affect oxide trapped charge Vat, whereas the interface trapped charge V,t remains almost unaffected. 0 1995 IEEE
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I
600 1
" t E
400
Preirradiation threshold-voltage, measured on the two wafers, was 1.1h 0.03V for this size oftransistor.
v
p E v
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_
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1
10
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Gate length (pm)
Figure 1. Interface trap and oxide charge contributions to the Vt shift after 1 Mad (Si02) versus gate length of NMOS transistor from wafer with 1050°C RTA (X) and without RTA (A). (ii) Effects on Interface States Build Up afer Irradiation
Figure 2 compares the values of AVot and AVit for NMOS transistors that have received various high temperature treatments
Figure 3. Contour plot of the AVot obtained at 1 Mrad(SiO2) on NMOS transistors using the 975°C Rapid Thermal Anneal.
300
After 1 Mrad(Si02)
,025oc 1050°C
975OC
I95wc
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100 ................................................................ ~
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AVot (mv)
Figure 2. AVit-AV,, plot for various RTA conditions in NMOS transistors. This method of representation allows to clearly notice that RTA seems to have no effect on interface states build up. Moreover, the obtained value (AVlt s 100 mV) is the same as the one obtained with a furnace annealing (Cf Fig.l), whatever the RTA temperature. It can be seen in Fig.2 that increasing the RTA temperature results in a large rate of variation in AV,,. After this consideration, we shall focus the data presented in this paper on the Vot topic.
B. WaferMapping AVt values were recorded after 1 Mrad(SiO2) irradiation on 21 test sites distributed in,a checkerboard pattern across a wafer. The following figures 3 and 4 show the contour plot of the isovalues of AV,t obtained for the 0.8-pm transistors.
Figure 4. Contour plot of the AVot obtained at 1 Mrad(SiO2) on NMOS transistors using the 1050°C Rapid Thermal Anneal. From these observations, it becomes clear that severe variations can be obtained across a wafer, especially at high annealing temperature. It can be also noted that the shifts are worse at the periphery. The worst case for NMOS transistors is located near the flat, while the best result is obtained in the center of the wafer. As preirradiation threshold voltage differences were small, this result shows that these variations have no effect on the non-uniformity of AV,,. Non-uniform temperatures across wafers due to edge heat losses are well known [111. Despite the use of compensation techniques, which provide variation in temperature better than 20°C, this could contribute to the AVt non-uniformity.
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The paper will interpret the data in more detail by considering the following two factors : (i) the value of the Vt shift obtained in the central area of the wafer, and (ii) the radial variation of the Vt shifts.
C. Comparison WithFurnace Anneal Figures 5 and 6 show the threshold voltage shift AVt at I Mrad(SiO2) as a function of die location for NMOS and PMOS transistors. The inset shows the location of the sample on the wafer.
;
-1 00 O -200
s3 -300 s
-400
-500 -600 Die Location
Figure 5 . NMOS's Vt shift after 1 Mrad(SiO2) as a function of die location for wafers processed with (A)1050 "C RTA and without (m) RTA.
IV. EFFECT OF ANNEAL TEMPERATURE AND DURATION ON RADIATION HARDNESS
A. Correlation As is classically known for furnace anneal, the primary effect is related to the maximum temperature during the process. The charge separation of threshold voltage shift into radiation-induced oxide trapped charge and interfacetrapped charge also shows a correlation between RTA temperature and AVot(Cf. Figs.3 to 6). Fig. 7 summarizes AVt for NMOS transistors on the central area of the wafer annealed at different temperatures by using two methods: (i) Furnace anneal for 30 minutes (ii) Rapid Anneal for 10 seconds As shown in Fig. 7, a threshold for the onset of radiation sensitivity occurs between 975OC and 1025OC for RTA anneal. Each error bar represents the average, the minimum and maximum deviation based on five samples. The threshold effect also appears for furnace anneal at lower temperature, as previously reported [I-61. For RTA anneal, we notice that non-uniformity increases with increasing temperature. The hardness drops sharply as temperature goes beyond 975"C, consequently a slight variation of temperature across the wafer induces a large increase or decrease in the threshold voltage shift.
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Anneal Temperature ("C)
die location for wafers processed with (A)1050 "C RTA and without (m) RTA. A strong dependence of AVt on transistor location exists for wafers processed with RTA (lO5O0C for 10s) as opposed to those annealed in a furnace ( S S O O C for 30 min.) without RTA. It can be noted that in the case of furnace annealing, wafers can be considered as being at thermal equilibrium in a medium of uniform temperature. This is in contrast with RTA where there exists heat sources, cold walls, etc. and where very fast ramping up and down can induce thermal delay and non-equilibrium. This will be examined in the next Section.
Figure 7. Vt shift after 1 Mrad(SiO2), versus anneal temperature for NMOS transistor.
B. Interpretation by ViscousFlow Theory in Si@ The results show that the radiation hardness of a gate oxide is a sensitive function of the anneal conditions. However, a comparison between RTA and furnace anneals shows that the temperature is not the unique parameter for this sensitivity. This discrepancy is related to the second parameter which i s the annealing time.
To explain the variation of the threshold voltage shift with the temperature and the duration of rhe anneals, a dynamic parameter of the material Si02 has been identified as the key
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to solving t h s problem. Initially thw was proposed to be the viscosity [3,5]. The observation of mechanical stress effects due to thermal treatment is consistent with time constants characteristic of Si02 viscous flow. These time constants range from some tens of seconds to several minutes for temperatures usually used in anneals. Then, the increase in temperature threshold observed with RTA could be explained by an anneal time smaller than the viscous flow characteristic time for temperatures below 975°C. Figure 8 shows the Arrhenius plot of the results together with data from ref. [ 3 ] .
silicon layers (Si and polysilicon gate for gate oxide, or top and bottom Silicon for SIMOX). This model is based on Fick's observation that the solubility limit of oxygen interstitials at elevated temperatures is not negligible:
[O]l = 1.53 1021exp (-1.03 e V l k T ) ~ m ' (1) ~, and therefore, an effect of "gettering"can exist due to Fick's diffusion with oxygen surface concentration at the Si/SiO2 interface. The silicon substrate being very thick, a certain amount of oxygen can penetrate more or less deep into it, basically leaving oxygen vacancies in the oxide, in a quantity detennined by the temperature and the duration of the anneal.
V Furnace anneal
A After Ref. [3]
This should result in the build up of oxygen-vacancies in the silicon dioxide side of the interface, which are"one of the defect-precursors related to positive trapped charge [I 11. If we consider this mechanism, the simple resolution of Fick's equation allows to calculate the profile of 0 interstitials zn the silicon substrate:
0 74 0.76 0.78 0.8 0.82 0.84 0.86 0.88 0.9 0.92
(2)
1000/T (K)
Figure 8 Arrhenius plot of Vt shift after 1 Mrad(SiO2) for NMOS
transistor
We notice that the slope is the same for the three sets of data (# 3eV). This slope, representative of the defect creation energy is similar and independent of the anneal type (either furnace or RTA). Furthermore, since the process (e.g. oxidation, ambient, temperature, thickness, metal gate, etc) and anneal conditions (e.g. anneal duration) used in the present study and in ref. [ 3 ] are very Merent, this suggests that the creation energy could be an intrinsic property of the Si02 material. On a macroscopic scale, the intrinsic properties involved are the mechanical constants of Si02 and Si (thermal expansion coefficients, elastic modulus and viscosity of SiO2). On the microscopic scale, the consequence of stresses and flows involved is the generation of defects and strained bonds in silica and at the interface which are only partially annealed during the treatment. Despite the fact that these theories fairly well account for the activation energy values and the value of the temperature threshold, they inherently fail to describe the microscopic mechanisms involved at the atom bond levels. Another rationale was searched by authors [7,&],starting on the contrary from the microscopic mechanisms based on oxygen solubility and diffusion in silicon.
C. Interpretationin Terms of Oxygen Out-dffusion ent works [7,8] have invoked a mechanism involving 0 out-diffusion from the oxide to the adjacent
where: X is the abscissa in silicon taken from the Si/SiO2 interface, and t is the anneal time (in this simple model, rmping up and down temperature histories are not taken into account).
[O]ii = k [O]~,,, is the concentration of 0 in the oxide adjacent to the interface (z.5. k being the solubility segregation coefficient derived from (1). D,; is the diffusion coefficient for 0 interstitials in Si, modeled as:
Dsi = 0.17 exp(-2.54eY I kT).
(3)
In order to evaluate the validity of these assumptions, one has first to compare the density of traps revealed by irradiation and the quantity of the out-diffused oxygen. Let Nox be the density of oxygen vacancy in the oxide (cm-2) due to high temperature anneals. Let Vow be the voltage shift developed at the MOS interface by the "oxygen vacancies", in the case where they were all charged positively:
Voq = q Nox/Cox.
(4)
The calculated out-dfised concentrations of oxygen as a function of temperature are shown in Fig.9.
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induced positive charge is not correlated one-to-one to the oxygen vacancy precursor [7], and (iii) the dose level of the experimental data is not s a c i e n t to Jill up the available defect precursors.
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To that purpose, we have simply strictly followed the calculation process pointed out by [SI, but applied it to various RTA and furnace anneal conditions. The authors first calculate the out-diffused oxygen profile no, (cm-3) :
800
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900 950 1000 Anneal Temperature (“C)
1050
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Figure 10. Comparison between predicted and experimental threshold voltage shifts.
V. RADIAL GRADIENTS where
A. Global Results Concerning K t and V,,
xsio2 is
the abscissa taken from the Si/SiO2
interface and
D, = 0.17 exp (-2.54eV / k T ) ,
(6)
D,= 2.6exp (-4.7 eV / kT),
(7)
are the diffusivities (cm2-s-’) in silicon and oxide respectively (as taken in [7] or [SI).
It has been shown that there is a good qualitative agreement between the shift of the oxide trapped charge and the voltage due to 0 out-diffusion. However, as shown in Figs. 3 and 4, a second order effect, non-uniform AVot,is observed as RTA temperature is increased. To evaluate this die-location discrepancy, a wafer has been completely characterized as a function of radial position R. Fig 11 illustrates the measurements of AVt, AVit, AVot across the wafer for 975°C RTA anneal.
Then the integration of the profile over xsio2gives No, at a given time. One supposes that cooling down is instantaneous and does not give rise to oxygen back-diffusion into Si02. Although the model is simple, this physical process can explain the difference between the two types of annealing. The model accounts for the two experimental key parameters, the temperature and time of the anneal. Furthermore, the rate limiting process is the 0 diffusion and the activation energy (2.54 ev) is compatible with the slope of the Arrhenius plot (around 3 ev).
3- l-50 oo/ -150
-
0.5
To show that the model closely matches the temperature and time effects of post-oxidation anneal, we calculated the corresponding voltage by using equation (4). Fig.10 illustrates the AVot shift after 1 Mrad(SiO2) and the calculated voltage induced by out-diffusion as a function of the anneal temperature. The shape of the predicted curves is in agreement with the experimental data. Differences in magmtude could be explained by the following three considerations (i) the predicted voltage VOv is calculated by considering only positive charge traps, and (ii) the radiation
I
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2 2.5 3 3.5 Radial position (cm)
4
4.5
5 i
Figure 11. Voltage shift versus radial position on wafer after 1 Mrad(Si02). At this temperature of 975”C, AVot discrepancies between die location close to the center and the edge of the wafer are about 40% while the dependence of AV;, with radial position is lower than the AVotone.
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A 1050°C RTA 0 975°C RTA
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The examination of these non-uniformities has been thoroughly explored in several papers [12,131. These authors made both thermal heat fluxes models and verification using temperature measurements. Modeling is based on the radiative flux exchanges between the heat source, the target wafers and the more or less cold walls and susceptors. In [13], the heat transfer equations are coupled with the elastic stress equation. Figures 13 and 14 reproduce the tangential stress-field ot in the case of a thermal gradient of about 20°C of the same order as ours. The analogy with figures 11 or 12 is satisfactory.
Radial position (cm)
Figure 12. Comparison of AVot as function of radial position for two RTA temperatures, after 1 Miad(SiO2). 17 hi
In Fig. 12 AVot has been normalized to the response of AVotrelated to the radius refered as Rmin. The same type of result is observed at higher temperatures (e.g. increase of AVot with the radius) as shown in Figure 12. However, for the 1050°C RTA, the discrepancies are increased and reach 100% but AVit is much less af€ected (Cf Fig 2). These results again suggest that RTA is only effective on the positive trapped charge defect precursor and does not influence the interface trap build up.
21 1)s 1A 2.1
5
3
t- i 5 .P
G
K
+ o -5 0.0
B. Interpretation A measured temperature profile across wafers made by a pyrometer or by oxide thickness measurements exhibits a decrease of about 20°C from the center to the edge of the wafer at 975°C. So, the increase of the Vot shift with radial position can not be directly related to the temperature gradient in the wafer since a lower temperature at the edge should induce a lower Vot shift.
0.2
0.4
0.6
0.8
1.0
Normatized radius Figure 14. Thermal tangential stress in silicon as computed by [13] as a result of the thermal radial Field.
C, Comments It is important to note that the cold areas are located at the periphery of the wafer. Consequently, according to the classical considerations concerning the funiace anneal temperature and from the new results exposed in the preceding section concerning the RTA, this lower temperature should have given a better hardness expressed as a lower AVot. This observation is unique to RTA because it is probably related to the temperature gradient. In effect, it is not found in furnace anneal which are essentially uniform in temperature and where no thermal graaent exist.
9501 900
00
,:rFf-y', 1 ,
0.2
0.4
0.6
0.8
,
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Normalized radius Figure 13. Radial field of temperature during RTA as modeled and measured by [13]. Boundary values of the temperature fit with our measurements.
A t fhafpoinf,two different hypotheses can be made : - in the frame of the out-Wsion model, a possible explanation would be to consider thermal stresses induced by the temperature gradient across the wafer as described. The activation energy for diffusion of 0 could be increased because of the stress, or the diffusion process could incorporate another component due to the driving force derived from thermodynamics in the presence of a stress gradient. No calculation has been made to date to confim or rule out this hypothesis and this treatment is clearly out of the scope of this present paper.
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- in the frame of the viscous flow model, one could consider that the stresses induced by the thermal gradient modify the stress-field in the oxide, and qspecially the shear stress as considered by [5]. In the esseqce of the viscous flow model, the larger the shear stress ih the oxide, the larger the generated defect density and consequently the worse the hardness. Although the microscopic interpretation still remains vague, the interpretation should be more straightforward. In this theory, the variables are of the same kind as those derived from viscoelastic stress-strain fields only modified by thermal field.
VI. CONCLUSION We have investigated the application of RTA in a CMOS process technology. New insights on hardness and nonuniformity of radiation response were found. The oxide-trapped charge component of the threshold voltage shift increases with the temperature of the RTA. Comparison between RTA and standard furnace anneals indicates that the hardness of the oxide can be considered as controlled by a series of material-related processes involving both silicon and silicon dioxide. - for the classical temperature-hardness correlation, viscous flow cannot be ruled out, but the oxygen out-diffusion model gives striking agreement. This model is better understood as it gives microscopic interpretation of defect precursor generation. We have shown that our anneal data (9501O5O0C, 10 seconds) help to venfy this model in a range very different from the two previously used by the original authors (1320OC-6 hours for SIMOX, 800°C-950°C-30 minutes for thermal oxide). - for the specific radial dependence associated with RTA, the diffusion model requires some modification. The viscous flow theory would give a more direct interpretation.
VII. REFERENCES [l] K.G. Aubuchon, "Radiation hardening of PMOS devices by optimization of thermal Si02 gate insulator", IEEE Trans. Nucl. Sci. Vol.-17, N06, (1971). [2] W.R. Dawes, Jr., G.F. Derbenwick, and B.L. Gregory, "Process technology for radiation-hardened CMOS integrated circuits", IEEE J. Solid State Circuits SC11(4), 459 (1976). [3] P.S. Winokur, E.B. Erret, D.M. Fleetwood, P.V. Dressendorfer, and D.C. Turpin, "Optimizing and controlling the radiation hardness of Si-gate CMOS process", IEEE Trans. Nucl. Sci. Vol.-32, N"6, (1985). [4] J.R. Schwank and D.M. Fleetwood, Temperature effects on the radiation response of MOS devices", Appl. Phys. Lett. 53,770 (1988). [5] E.P. Eernisse and G.F. Derbenwick, 'I Viscous shear flow model for MOS device radiation sensitivity", IEEE Trans. Nucl. Sci. Vol.-23, N"6, (1976). [6] J.L. Leray , "Contribution A 1'6tude de phinomenes induits par les rayonnements ionisants dans les structures a effet de champ au silicium ou a l'arseniure de gallium utilistes en microdectronique" Thkse d'itat, Universitk Paris Sud, France, no 3375 (1989). It
71 W.L. Warren, D.M. Fleetwood, M.R. Shaneyfelt, J.R. Schwank and P.S. Winokur, "Links between oxide, interface, and border traps in high-temperature annealed Si/Si02 systems", Appl. Phys. Lett. 64 (25), (1994). [SI R.AB. Devine, W.L. Warren, J.B. Xu, I.H. Wilson, P. Paillet and J.L. Leray, "Oxygen gettering and oxide degradation during annealing of Si/SiO,/Si structures", J. Appl. Phys. 77 (l), 1, (1995). [9] 0. Flament, J.L. Leray, J.L. Martin, J. Montaron, M. RafTaelli, J.P. Blanc, E. Delevoye, J. Gautier, J. de Poncharra, R. Truche, E. Delagnes, M. Dentan and N. Fourches, "Radiation effects on SO1 analog devices parameters", IEEE Trans. Nucl. Sci. Vol.-41, N"3, (1994). [lo] M.R. Shaneyfelt, D.M. Fleetwood, P.S. Winokur, J.R. Schwank, and T.L. Meisenheimer, "Effects of devices scaling and geometry on MOS radiation hardness assurance", IEEE Trans. Nucl. Sci. Vol.-40, N"6, 1678, (1993). [ l l ] A.X. Chu and W.B. Fowler, "Theory of oxide defects near the Si-Si02 interface", Phys. Rev. B, Vol. 41, nos, 5061 (1990) [12] R. Kakoschke and E. Bussmann, "Simulation of temperature effects during rapid thermal processing", MRS Symposium Proceedings, Vol. 146 (1989). [13] H.A. Lord, "Thermal and stress analysis of semiconductor wafers in a rapid thermal processing oven", IEEE Trans. on Semi. Manufac., Vol.1, N"3, (1988)
