Effective Design and Implementation of GSS-PLL ...

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Effective Design and Implementation of GSS-PLL under Voltage Dip and Phase Interruption Hany A. Hamed, Ahmed F. Abdou, Ehab Bayoumi, and E. E. EL-Kholy,

Abstract — The robust operation of grid-connected converters under non-ideal grids is a challenging topic. Synchronizing of converters requires accurate estimation of the grid vector angle which is traditionally performed by Phase Locked Loops (PLLs). Separating the grid voltage and current sequence components is essential for controlling converters under non-ideal grids. In this paper, an efficient method to separate the grid sequence components using Cascaded Delayed Signal Cancellation (CDSC) is developed. The proposed method is a reduced version of the conventional DSC separation technique. Implementing CDSC in the stationary frame enables for using a higher bandwidth without degrading its filtering capability which enables for using the GSS as a pre-filter stage for the traditional Synchronous Reference Frame PLL (SRF-PLL). Therefore, the obtained Grid Sequence Separation PLL (GSS-PLL) accurately estimates the grid vector angle under severe conditions. The performance of GSS method as well as GSS-PLL is compared to the conventional Multiple Second Order Generalized Integrator (MSOGI) method under unbalance, phase interruption and harmonically distorted grids. The accuracy of the proposed method is verified through simulation and experimental tests. The low computational effort of GSS scheme compared to the MSOGI is a significant advantage which encouraging its implantation for most of the grid-connected converters.

Keywords: AC-DC Power Converters; Phase Locked Loop; Power Quality; Delayed Signal Cancellation.

INTRODUCTION

P

HASE Locked Loop (PLL) is widely implemented for the synchronization of grid-connected converters [1]. Unfortunately, due to various grid disturbances, its performance and grid angle estimations are deteriorated under

voltage dips, phase jumps, dc-offset, and harmonics. Therefore, there is a need to design a robust and disturbance immune PLL for grid-connected applications. The most common types of PLLs use the q-axis component of the grid voltage to estimate the grid angle. As in an unbalance grid, this component is contaminated with a twice frequency wave. The amplitude of which depends on the level of imbalance, so, its positive sequence component should be extracted. Usually, the twice frequency wave can be attenuated by using a low pass filter (LPF) with a small bandwidth [2]. Reducing the filter bandwidth results in slowing down the dynamic response which is not acceptable in some application [3-5]. Moving Average Filter (MAF) is introduced to extract the positive sequence component under disturbed grids. However, the MAF-PLL dynamic performances might not adequate for some applications [6, 7]. An efficient approach introduced in [8] uses a Dual Second Order Generalized Integrator (DSOGI-FLL) to extract the sequence components, but it should use a complicated structure if the grid contains several low orders harmonics. The research on grid sequence extraction continued, by introducing a modified DSOGI-FLL as presented in [9] which is called Multiple Second Order Generalized Integrators (MSOGI-FLL). This approach is proposed to extract the sequence components under harmonically distorted grids and is able to be automatically tuned to grid frequency changes. Later, the research shifted to another domain to cancel wide harmonic orders instead of attenuating them by utilizing Delayed Signal Cancellation (DSC) complex filters [10-15]. The DSC can be arranged in a cascaded mode to cancel a broad range of harmonics with simple structure [16]. The DSC itself is a complex structure that can be developed in either a stationary or synchronous reference frame. The drawback of the cascaded DSC is its inherent delay which is introduced to the control loop. This delay must be considered when designing the PLL controller parameters. Otherwise, the PLL dynamic performance will be degraded. On the

This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. contrary, as a delay is not considered if the DSC is relocated in the stationary frame, a faster dynamic response can be obtained. Therefore, using a stationary frame DSC as a pre-filter for a PLL is preferable when a fast dynamic response is required. In grid-connected converters, the operation under an unbalanced grid requires a sophisticated control to regulate the grid sequence current components separately. The Dual Vector Control (DVC) concept [17-24] is developed to regulate the positive and negative sequences individually. It needs separating the current and voltage sequence components which require a dedicated algorithm. Several extractor algorithms have been proposed such as extracting the sequence components based on delaying the 𝑎𝑏𝑐 phase components [25], using Double Decoupled Synchronous Reference Frame (DDSRF) [23] and DSOGI method [21]. However, separating the sequence based on the DSC concept has gained more attention due to its wide range harmonic filtering capability [10, 26, 27]. In this paper, a simple algorithm for extracting the grid’s sequence components is proposed. It is based on modeling the DSC operator in the stationary reference frame with an extension to extract the sequence components as well as filtering a broad range of harmonics. This sequence extractor is added to the conventional SRF-PLL to obtain a robust system that can efficiently work with non-ideal grids. Mathematical equations for modifying the DSC operator to extract the negative sequence are also presented. The proposed Grid Sequence Separator PLL (GSS-PLL) acts as a pre-filter for the SRF-PLL and is evaluated under grid unbalance, one phase interruption and grid background low order 5th and 7th harmonics. This paper is organized as follows. The concept of a stationary frame DSC is mathematically introduced in section II. The proposed sequence extraction technique is presented in Section III. Three different schemes for PLLs and their controller parameters design is discussed in Section IV. Section V presents the simulation results under voltage dip and one phase interruption fault. The experimental results performed on the dSPACE DS1104 digital platform is presented in Section VI. Finally, a summary and conclusions are given in Section VII.

CONCEPT OF DELAYED SIGNAL CANCELLATION (DSC) The DSC is a complex filter that depends on adding a signal to its delayed version to cancel individual harmonics [28]. Inspired by this idea, a time-domain DSC operator can be defined in the 𝑑𝑞-frame with a delay factor “𝑛” as [16, 29] ′ (𝑡) 𝑢𝑑𝑞 =

1 𝑇 [𝑢 (𝑡) + 𝑢𝑑𝑞 (𝑡 − 𝑛𝑜 )] 2 𝑑𝑞

(1)

where 𝑇𝑜 is the fundamental period of the grid voltage. This transformation is extended for the harmonic content in the grid voltage by presenting (1) with an harmonic order “h” [11]. This transformation can be applied in 𝛼𝛽-frame or dqframe depending on the target application. For example, the SRF-PLL can contain in-loop filters which can be replaced by the DSC in dq-frame or pre-loop filters which can be replaced by DSC in 𝛼𝛽-frame. The different is realized when designing the control loop of PLL as the DSC itself introduce a well-defined delay which should be considered when deploy for the in-loop PLL structures. Moreover, there is a difference related to presenting the harmonic order in both frames as the order ℎ𝛼𝛽 in 𝛼𝛽-frame is less by one when presented in 𝑑𝑞-frame as ℎ𝑑𝑞 or ℎ′ . With an unbalanced or harmonically distorted grid, 𝑢𝑑𝑞 will be polluted. A harmonic signal with the order ℎ′ will superimposing the positive sequence component. If we start analyzing the harmonics in DSC in 𝑑𝑞-frame, (1) can be presented by the harmonic order as follows, The grid voltage vector for any harmonic order can be presented in the generic form using the 𝑑𝑞-frame harmonic order ℎ′ . For any harmonic order ℎ, the grid voltage harmonic can be presented in the 𝑑𝑞-frame as follows, ′

𝑢ℎ = 𝑉ℎ 𝑐𝑜𝑠 ℎ′ 𝜔𝑡 { 𝑑ℎ′ 𝑢𝑞 = 𝑉ℎ 𝑠𝑖𝑛 ℎ′ 𝜔𝑡 Where ℎ′ = ℎ − 1 combining (1) and (2) and using simple trigonometric functions,

(2)

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ℎ 𝑢𝑑𝑞 = 𝑉ℎ [𝑐𝑜𝑠(ℎ′ 𝜔𝑡 −

ℎ′ 𝜋 ℎ′ 𝜋 ℎ′ 𝜋 ) + 𝑗 𝑠𝑖𝑛 ((ℎ′ 𝜔𝑡 − )]. 𝑐𝑜𝑠 ( ) 𝑛 𝑛 𝑛

(3)

Presenting (3) in Euler form, ′

′

′

ℎ 𝑢𝑑𝑞 =⏟ 𝑐𝑜𝑠 (ℎ′ 𝜋⁄𝑛) . ⏟ 𝑒 −𝑗ℎ 𝜋⁄𝑛 ⏟ 𝑉ℎ 𝑒 𝑗(ℎ 𝜔𝑡) 𝑝ℎ𝑎𝑠𝑒 𝑑𝑒𝑙𝑎𝑦 𝑖𝑛𝑝𝑢𝑡 𝑣𝑒𝑐𝑡𝑜𝑟 ⏟ 𝑔𝑎𝑖𝑛

(4)

𝑓𝐷𝑆𝐶 𝑂𝑝𝑒𝑟𝑎𝑡𝑜𝑟

From (4) the gain modulus of the DSC operator 𝑓𝐷𝑆𝐶 can be presented as 𝑓𝐷𝑆𝐶 = 𝑐𝑜𝑠(ℎ′ 𝜋⁄𝑛). 𝑒 −𝑗ℎ

′ 𝜋 ⁄𝑛

(5) (6)

|𝑓𝐷𝑆𝐶 | = 𝑐𝑜𝑠(ℎ′ 𝜋⁄𝑛) The DSC operator delay can be calculated as,

(7) ∠∅𝐷𝑆𝐶 = −ℎ′ 𝜋⁄𝑛 By selecting a proper value of 𝑛 for a certain harmonic order ℎ the gain in (6) can be zero. To illustrate the effect of the DSC operator, its gain is plotted for different delay factors (𝑛=4 and 𝑛=8) as shown in Fig. 1. Based on the 𝑛 value, the gain is zero for wide spectrum harmonics, with those harmonics up to the 19th order listed in Table I. As mentioned before, the harmonic order in 𝑑𝑞-frame is less by one. For example, the 5th harmonic in 𝛼𝛽-frame will be presented by (ℎ′ = -6) in dqframe and eliminated by DSC with delay factor = 4 (DSC4). Similarly, the 11 th harmonic in 𝛼𝛽-frame will be presented as (ℎ′ =12) in dq-frame and eliminated by the DSC with a delay factor = 8 (DSC8).

(a) (b) 𝑇 𝑇 Fig. 1. Frequency response of DSC operator for different delay factors. (a) with 𝑜 delay. (b) with 𝑜 delay. 4

8

TABLE I DSC OPERATOR FOR HARMONICS Harmonic Order Stationary frame

-1

-5

+7

-11

+13

-17

+19

Synchronous frame

-2

-6

+6

-12

+12

-18

18

Sequence

-

-

+

-

+

-

+

DSC delay time

𝑇𝑜 4

𝑇𝑜 4

𝑇𝑜 4

𝑇𝑜 8

𝑇𝑜 8

𝑇𝑜 4

𝑇𝑜 4

Generically, for a delay factor of 𝑛 ∈ (2, 4 ,8, 16, … ), the spectrum of harmonics orders ℎ𝑖 are eliminated. The combination between harmonic order ℎ′ and delay factor 𝑛 could lead to have the gain in (4) equal zero if

ℎ′ 𝜋 𝑛

𝜋 3𝜋

∈( , 2

2

,

5𝜋 2

, … ). As for

industrial grids, the low order harmonics are the most harmful, although it is common practice to install tuned filters to the 5th, 7th and 11th harmonics. However, the PLL should be immune to those harmonics. To filter out the harmonics from 5th up to 13th in the PLL input measured voltage signal, cascaded 𝑑𝑞-DSC filters are used in-loop with different delay factors set to 4 and 8 respectively as shown in Fig. 2.

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𝑢𝑑𝑞

Delay To/4

-

+

1/2

Delay To/8

-

+

1/2

′ 𝑢𝑑𝑞

Fig. 2. Cascaded DSC block diagram.

The total delay introduced by the cascaded blocks can be expressed as follows, 𝑘

𝑇𝑑 = ∑ 𝑖=1

𝑇𝑜 𝑛𝑖

(8)

The disadvantage of using in-loop filters is the introduced delay which degrades the PLL’s dynamic response. Such slow PLLs cannot fit for some power electronics applications which depend on measuring the grid angle to generate the modulating signals [30]. If the DSC operator is relocated outside the PLL control loop, the delay can be ignored when designing the control loop and a higher bandwidth can be used. If the DSC is relocated in 𝛼𝛽-frame, the DSC cannot simply be cascaded by adding

them in series with different delay factors. The next section introduces the cascading method and an extended function of DSC to extract the grid negative sequence components. PROPOSED TECHNIQUE FOR EXTRACTION GRID SEQUENCE COMPONENT DSC operator in stationary frame Although the DSC operator can only function to extract the positive sequence component of grid voltage at dc-frame, it can also be relocated in 𝛼𝛽-frame to eliminate the delay introduced within the PLL control loop. The relocation enables for extracting the sequence component of grid voltage in both 𝛼𝛽-frame as well as 𝑑𝑞-frame. The proposed scheme is called Grid Sequence Separator or (GSS). To perform the relocation, the DSC filtering effect on 𝑑𝑞-frame, theoretically should have the same effect if it is presented in 𝛼𝛽-frame. Accordingly, the DSC operator in dq-frame is mapped to 𝛼𝛽frame as follows [11, 29], 2𝜋 2𝜋 𝑇𝑜 𝑐𝑜𝑠 ( ) − 𝑠𝑖𝑛 ( ) 𝑢𝛼ℎ (𝑡 − ) 𝑢′ℎ𝛼 (𝑡) 1 𝑢𝛼ℎ (𝑡) 𝑛 𝑛 𝑛 ]) (9) [ ℎ ]= ([ ℎ ]+[ ][ 𝑇 2𝜋 2𝜋 𝑢′𝛽 (𝑡) 𝑢𝛽 (𝑡) 2 𝑜 ℎ 𝑠𝑖𝑛 ( ) 𝑐𝑜𝑠 ( ) 𝑢𝛽 (𝑡 − ) 𝑛 𝑛 𝑛 The implementation of (8) is shown in Fig. 3(a). Several orders of DSC can be driven by altering the delay factor 𝑛 to target certain harmonics range. As shown in Fig. 3(b), the DSC2 operator with delay factor 𝑛=2 to cancel the dc-offset while DSC4 is constructed using 𝑛= 4 is shown in Fig. 3(c) to cancel the negative sequence (ℎ′ = -2), 5th harmonic (ℎ′ = 6) and 7th harmonics (ℎ′ = +6). Similarly, DSC8 is shown in Fig. 3(d) to cancel the 11 th harmonic (ℎ′ = -12), 13th harmonic (ℎ′ = +12).

Delay To/n

+

Delay To/n

+

(a)

+ -

+ +

1/2

Delay To/2

-

Delay To/2

-

+

+

1/2

(b)

1/2

1/2

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Delay To/4

1

-

Delay To/4

1

+

+

1/2

1/2

+

Delay To/8

+

+ -

1/2

Delay To/8

+

+ +

1/2

(c) (d) Fig. 3. DSC scheme with different delay factors. (a) generalized structure. (b) DSC2 for canceling dc-offset with 𝑛 = 2. (c) DSC4 for cancelling negative sequence, 5th and 7th and low order harmonics with 𝑛=4. (d) DSC8 for cancelling 11th and 13th with n=8.

Proposed Sequence Separation Technique Several sequence separation techniques have been proposed such as decouple double synchronous reference frame (DDSRF) [31], all-pass filters (AFP's) [32], enhanced type PLL (EPLL) [33], Dual Second Order Generalized Integrator (DSOGI) [34] and adaptive notch filters (ANFs) [35]. Using DSC for sequence separation is realized is some literature but used in single mode. [10, 36]. The method presented in [10] utilizes two DSC block with two axis transformation blocks to separate the sequence components as shown in Fig. 4(a). The proposed method utilizes half of the DCS blocks as shown in Fig. 4(b). This will reduce the computational time when digitally implemented as a part of a complex converter control system. DSC 4

𝛼𝛽

DSC 4

𝛼𝛽

+ 𝑢𝑑𝑞

𝑢𝑎𝑏𝑐 𝑎𝑏𝑐 𝛼𝛽

𝑑𝑞

𝑢𝑎𝑏𝑐 𝑎𝑏𝑐 𝛼𝛽

𝑑𝑞 +

− 𝑢𝑑𝑞

+ 𝑢𝑑𝑞

𝛼𝛽

DSC 4 -

− 𝑢𝑑𝑞

𝛼𝛽 𝑑𝑞

𝑑𝑞

-1

-1

𝜃𝑃𝐿𝐿

𝜃𝑃𝐿𝐿 -

(a) (b) Fig. 4. Sequence component separation techniques. (a) conventional DSC scheme. (b) proposed DSC scheme.

To proposed simplified scheme is inspired by the following, The voltage vector in 𝛼𝛽-frame under unbalance grid operation is resolved into two main components, negative sequence component as follows, + − 𝑢𝛼𝛽 = 𝑢𝛼𝛽 + 𝑢𝛼𝛽

(10)

+ − As the 𝑢𝛼𝛽 is already extracted by DSC operator, 𝑢𝛼𝛽 can be directly extracted by simply using (10) as follows, − + 𝑢𝛼𝛽 = 𝑢𝛼𝛽 − 𝑢𝛼𝛽 th

th

th

(11) th

By cascading DSC4 and DSC 8 to cancel 5 , 7 , 11 and 13 harmonics and using (11) to extract the negative sequence component, the proposed GSS can be constructed as shown in Fig. 5.

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DSC4

𝑢𝛼

𝑍

𝑇 −( 𝑜 ) 4𝑇𝑠

-

+

½

𝑍

𝑇 −( 𝑜 ) 8𝑇𝑠

1 2

+

+ -

½

𝑢𝛼′

𝑍

𝑇 −( 𝑜 ) 4𝑇𝑠

-

+

½

𝑍

𝑇 −( 𝑜 ) 8𝑇𝑠

1 2

+

+ +

𝑢𝑑+

𝛼𝛽

𝑢𝑞+

𝑢𝛽′ 𝑢𝑏

-

+ -

𝑑𝑞

½

𝜃𝑃𝐿𝐿 +

𝛼𝛽

𝑢𝑑−

𝑢𝑞− 𝑑𝑞 −𝜃𝑃𝐿𝐿

FIG.5. PROPOSED GSS BLOCK DIAGRAM.

The GSS should be compared with similar grid sequence separation techniques which extract the positive sequence such as the Dual Second Order Generalized Integrator (DSOGI) which is proposed in [37]. The basic structure of DSOGI is shown in Fig. 6. The DSOGI is not immune to harmonics. As a result, a modified SOGI is called Multiple Second Order Generalized Integrator (MSOGI) is introduced in [9]. The MSOGI requires very complicated scheme “CrossFeedback” for each harmonic order, for example, the MSOGI incorporating 5th harmonic cancellation is shown in Fig. 7. For any specific harmonic order, the MSOGI must be modified by including two additional SOGI blocks with a crossfeedback arrangement which adds more complexity to the control circuit analysis as well as increasing the computational time when digitally implemented. The proposed GSS scheme uses only two DSC blocks to cancel a broad range of harmonics “5th, 7th, 11th, 13th, etc.,” with only two DSC blocks, on the other hand, MSOGI uses additional two SOGI blocks to cancel the 5th harmonic only. MSOGI should use eight SOGI blocks to have the same effect of GSS scheme; which is not comparable. Accordingly, the proposed scheme can eliminate a broad spectrum of harmonics by simply cascading two DSC blocks (DSC4 & DSC8) while the MSOGI requires very complicated scheme. The proposed technique compared to other techniques has the following advantages,

1.

The proposed technique shown in Fig. 4(b) eliminates the need to include two DSC blocks for extracting the negative sequence components, instead, a simple mathematical subtraction operation is used (referring to Eq. 11). This will reduce the computational time when digitally implemented.

2.

The absence of algebraic loops compared to the MSOGI technique avoids degrading the dynamic performance.

3.

The proposed method successfully reduces the residual error to zero compared to the MSOGI method.

4.

The operation under two phases is guaranteed.

Next section will introduce the proposed GSS implementation as a pre-filter for the conventional SRF-PLL scheme.

Proposed PLL based Grid Sequence Separator (GSS-PLL) The GSS, when used with the SRF-PLL as a pre-filter to extract the positive sequence component of grid voltage, is called GSS-PLL as shown in Fig. 8(a). Inherited from GSS concept, the proposed GSS-PLL is having a high immunity to various grid disturbances such as voltage unbalance and low order harmonics. The GSS-PLL dynamic response is simply adjusted due to the absence of in-loop delays. Moreover, there is no need to deploy a LPF with low cutoff frequency as the dominant low order harmonics are filtered out. The GSS can be extended to eliminate also the dc-offset by cascading a DSC2. In this paper, two DSC blocks are cascaded internally in GSS scheme. The GSS itself works as a pre-loop filter with a definite delay time. As the GSS is placed as a pre-loop filter, the control loop can be designed with a much higher bandwidth which results in faster dynamic response. The equivalent block diagram of the proposed scheme is shown in Fig. 8(b).

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𝑢𝛼

+

-

k

𝑣𝛼′

+-

½

𝑞𝑣𝛼′

𝑢𝑞+

𝑑𝑞

++ SOGI

𝑢𝑑+

𝛼𝛽

+-

½

𝜔𝑜

𝜃𝑃𝐿𝐿

𝑢𝛽

+

-

k

𝑣𝛽′

+-

½

𝑞𝑣𝛽′

SOGI

-1

½

𝜔𝑜

𝑢𝑑−

𝛼𝛽

++ -+

𝑢𝑞−

𝑑𝑞

Fig. 6. Block diagram of the DSOGI-FLL [38].

PNSC Cross-feedback

𝑢𝛼

+-

½

-𝑉 ′

𝑉

SOGI 𝜔𝑜 𝑞𝑉 ′

½

′

½

SOGI 𝜔𝑜 𝑞𝑉 ′

½

𝑢𝑑+

𝛼𝛽

+-

𝑢𝑞+

𝑑𝑞

++

𝜃𝑃𝐿𝐿 -𝑉

𝑉

𝑢𝛽

+-

+

-

-1

′ -𝑉 SOGI 5𝜔𝑜 𝑞𝑉 ′

𝑉

𝑢𝑑−

𝛼𝛽

++ -+

𝑑𝑞

𝑢𝑞−

′ -𝑉 SOGI ′ 5𝜔 𝑞𝑉

𝑉

+-

𝑜

Fig. 7. Block diagram of MSOGI with elimination of 5th harmonic [9].

DSC8

DSC4

𝑢𝛼

𝑢𝑏

𝑇 −( 𝑜 ) 𝑍 4𝑇𝑠

𝑍

𝑇 −( 𝑜 ) 4𝑇𝑠

-

-

+

+

½

½

𝑇 −( 𝑜 ) 𝑍 8𝑇𝑠

𝑍

𝑇 −( 𝑜 ) 8𝑇𝑠

+ -

1

+

2

+ -

½

𝑢𝑑+

𝑢𝛼+

𝛼𝛽 𝑑𝑞

1

+

2

+ +

½

𝑢𝑞+

𝛼𝛽 𝑑𝑞

(a)

𝑎𝑏𝑐

𝑢𝑎𝑏𝑐

𝑢𝛼

𝑢𝛽

𝛼𝛽

𝑢𝑞+ GSS

𝑢𝑑−

𝑃𝐼

PLL 𝜔

𝑜

++

1 𝑆

𝜃𝑃𝐿𝐿

𝑢𝛽+ +

𝑢𝑑+

𝑃𝐼

𝜔𝑜 ++

1 𝑆

𝜃𝑃𝐿𝐿

𝑢𝑞−

(b) Fig. 8. GSS-PLL block diagram. (a) detailed block diagram. (b) simplified block diagram.

𝑢𝑑−

𝑢𝑞−

-1

This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. PLL LOOP DESIGN FOR DIFFERENT SCHEMES To compare the performance of the proposed scheme with conventional PLLs, three different PLL schemes will are introduced. They are SOGI-PLL, MSOGI-PLL, and the proposed GSS-PLL. The PI controller of those schemes is designed used Symmetrical Optimum Criteria [39]. In general, the symmetrical optimum design method depends on identifying the in-loop delay for designing the controller parameters. None of those above schemes introduce a delay when designing the closed loop. For the sake of generalizing the design, next section presents the PI controller parameter design for conventional SRF-PLL with LPF, DSC-PLL with DSC blocks in-loop and GSS/DSOGI/MSOGI. SRF-PLL Closed loop design The closed-loop block diagram for SRF-PLL is shown in Fig. 9. The open loop transfer function can be expressed as follows, 𝐺𝑜𝐿 =

𝜔𝑝 𝑘𝑝 (𝑠 + 𝜔𝑧 ) 1 𝑆 + 𝜔𝑝 𝑠 𝑠

(12)

where 𝜔𝑧 = 𝑘𝑖 /𝑘𝑝 and 𝜔𝑝 is the LPF cutoff frequency. As per the symmetrical optimum method, the PLL crossover frequency 𝜔𝑐 should be selected equal to the geometrical mean of the corner frequencies of the open-loop T.F. i.e. 𝜔𝑐 = √𝜔𝑝 𝜔𝑧 . This selection will provide the maximum phase margin (PM) at the crossover frequency. The open loop T.F in (12) can be represented in the following form, (𝑠 + 𝜔𝑐 /𝑏) 𝑠 2 (𝑠 + 𝑏𝜔𝑐 ) The controller parameter can be calculated as [2],

(13)

𝐺𝑜𝐿 = 𝑏𝜔𝑐2

𝑘𝑝 = 𝜔𝑐 𝑘𝑖 = 𝜔𝑐2 /𝑏

(14)

𝑏 = √𝜔𝑝 /𝜔𝑧 { The phase margin is selected in the range of 30< PM