Dan Jiao, Senior Member, IEEE, Joong-Ho Kim, and Jiangqi He, Member, ...... current research interests include high-frequency digital, analog, mixed-signal,.
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Efficient Full-Wave Characterization of Discrete High-Density Multiterminal Decoupling Capacitors for High-Speed Digital Systems Dan Jiao, Senior Member, IEEE, Joong-Ho Kim, and Jiangqi He, Member, IEEE
Abstract—This paper presents an efficient surface-based finiteelement method for the full-wave characterization of high-density and multiterminal decoupling capacitors (2, 8, 14, and any arbitrary number of terminals). In contrast to traditional finite-element methods that involve 3-D volumetric unknowns, this method reduces the unknowns one needs to solve to those on 2-D surfaces only. In addition, the reduction from the 3-D volume-based matrix to a 2-D surface-based one is achieved efficiently by exploiting the geometrical specialty of the decap structure. The entire numerical procedure is numerically rigorous without making any approximation. Its efficiency and accuracy have been demonstrated by both measurements and numerical experiments. Based on its fast and accurate solution, different design configurations of capacitors were studied to identify the optimal configuration that can maximize the performance of a decoupling capacitor. Furthermore, the full-wave model obtained from the proposed method was employed to assess the accuracy of conventional series lumped RLC capacitor models. In addition, the full-wave model was incorporated into a high-performance microprocessor’s power delivery network to investigate system performance. Index Terms—Characterization, decoupling capacitors, full wave, high-speed digital systems, power delivery design, surface-based finite-element method.
I. INTRODUCTION OMPLEMENTARY metal–oxide semiconductor (CMOS) microprocessors and application specific integrated circuits (ASICs) in a modern digital system consist of a large number of internal and external circuits (I/O drivers). The fast switching of these circuits enabled by recent advances in CMOS technology results in large current variations and fast transient droops and noises in a power supply network. These power supply noises can impact power and timing, limit system performance, cause reliability issues, and even lead to system breakdown. The noises can also increase the electromagnetic emissions from the digital system [1]. Therefore, it is of paramount importance to suppress power supply noises. However, the supply voltage is decreasing and the power is
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Manuscript received January 6, 2007; revised July 23, 2007. This work was recommended for publication by Associate Editor J. Schutt-Aine upon evaluation of the reviewers comments. D. Jiao is with the School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN 47907 USA. J.-H. Kim is with the Signal Integrity Group, Rambus Inc., Los Altos, CA 94022 USA. J. He is with the Intel Corporation, Chandler, AZ 85226 USA. Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TADVP.2007.906392
increasing with each generation. They reduce noise margin, increase supply current, and hence complicate the suppression of power supply noises. As a result, power delivery design for a high-speed digital system has become highly challenging. One of the most effective ways to reduce the power supply noise is to use decoupling capacitors on the card, board, package, and/or chip. These decoupling capacitors are used to offset the parasitic inductances present in a power distribution network, thereby yielding a small impedance over a frequency range as large as possible [2]–[4]. In a modern high-speed digital system, the noise budgets are typically in the range of millivolts, and hence it becomes critical to develop accurate models for decoupling capacitors. If decoupling capacitors are neither modeled nor designed properly, it could cripple the overall performance of a power delivery system. There exists research work on the characterization of decoupling capacitors [5]–[8]. Li et al. characterized capacitors in highfrequency ranges [5], studied on the validation of an integrated capacitor using capacitor-via-plane models, and applied quasistatic-type solvers [6]. Smith et al. worked on transmission line models for ceramic capacitors based on measurements and an equivalent series resistance (ESR) model for power delivery systems [7], [8]. These researchers provided detailed information about capacitor characterization based on measurement data. However, the approaches rely on the existence of a capacitor’s data, and hence are not sufficient to design unknown capacitor configurations that meet our requirements. Although a certain extension could be implemented to roughly predict a capacitor’s performance based on these methods, an accurate and fast approach that can model broadband frequency responses of any kind of configurations is highly desired. Moreover, to accurately predict the electromagnetic emission at UHF range, frequencydependent responses of decoupling capacitors are needed. As a result, a full-wave solver would be an ideal choice. Current existing commercial full-wave solvers, however, have certain limitations when applied to tiny, but very complicated, capacitor geometries. The reasons could be conductor loss, large aspect ratio, high permittivity, and a large number of power/ground planes that lead to large memory cost, expensive CPU run time, and slow convergence rate in these full-wave solvers. In this paper, an efficient surface-based finite-element solution is presented to characterize high-density multiterminal decoupling capacitors. In contrast to traditional finite-element methods that involve 3-D volumetric unknowns, this method reduces the unknowns one needs to solve to those on 2-D surfaces only. Furthermore, the reduction from the 3-D volume-based
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Fig. 1. Illustration of decoupling capacitors. (a) Side view of a 0612 two-terminal capacitor. (b) Top view of a 0805 eight-terminal capacitor with polished top surfaces.
Fig. 2. Typical terminal configurations (top view). (a) Eight-terminal (4:0). (b) Ten-terminal (4:1). (c) Twelve-terminal (4:2). (d) Eight-terminal (3:1).
matrix to a 2-D surface-based one is achieved efficiently by exploiting the geometrical specialty of the decap structure. It preserves the advantages of the finite-element method in circuit application such as the flexibility in modeling irregular geometry and the capability in handling arbitrary inhomogeneity. Meanwhile, it eliminates its disadvantages such as large memory requirement and high CPU cost resulted from 3-D volumetric discretization. The details of the proposed method are elaborated upon in Section II. In Section III, the numerical and experimental results are presented to demonstrate the accuracy and efficiency of the proposed method. In Section IV, different configurations of capacitors are investigated to optimize decap design. In Section V, the full-wave model is incorporated into a high-performance microprocessor’s power delivery network to examine system performance. Discussions will then be extended to whether full-wave frequency-dependent capacitor models are needed for a high-current and high-frequency power delivery network compared to conventional single-element series lumped RLC models. Section VI relates to our conclusions. This paper results from our preliminary work published in [9] and [10].
subject to certain boundary conditions. In (1), the bar over denotes a complex permittivity that comprises both permittivity is the relative permeability; and are and conductivity; free-space wave number and impedance, respectively; is the current source; and is the computational domain that encloses the circuit. The coordinate system is defined in Fig. 1 and used throughout this paper. In accordance with variational principle [11], the solution to the boundary value problem defined by (1) and its boundary conditions can be obtained by seeking the stationary point of the functional
(2) denotes the truncation boundary, which is the outerIn (2), most region in the computational domain. is an operator associated with the absorbing boundary condition placed on the truncation boundary. If the first-order absorbing boundary condition is used, (2) can be written as
II. EFFICIENT SURFACE-BASED FINITE-ELEMENT METHOD FOR FULL-WAVE CHARACTERIZATION OF DECOUPLING CAPACITORS Consider a typical capacitor structure shown in Fig. 1. Its common terminal configurations are shown in Fig. 2. satisfies the Inside the decap structure, the electric field second-order vector wave equation in
(1)
(3) Next, we perform discretization. The discretization is conducted for both dielectric regions and conducting regions. Disretizing
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into conductors allows for an accurate modeling of conductor loss, which is important to the accurate characterization of ESR. The triangular prism elements are used to discretize the computational domain. These elements are very suitable for the discretization of decap structures. In each prism element, we expand the unknown electric field into prism vector basis func[12] tions (4)
Fig. 3. Segmenting decap structure along y direction. (a) Perspective view. (b) Top view.
The superscript denotes element. Substituting (4) into (3), and taking the partial derivative of (3) with respect to unknown coefficients yield the following matrix equation: (5) in which and are assembled from their elemental counterparts as shown in
(6) In (6), the inner product is defined as
(7) After solving (5), we can extract design parameters of interest from field quantities . Due to the computational complexity of high-density decoupling capacitors as stated in Section I, the resultant system matrix is very big, which renders conventional full-wave modeling techniques inefficient or even incapable. To solve this problem, we propose an efficient surface-based finite-element solution for the full-wave characterization of decoupling capacitors. It is carried out in four steps: 1) slice the structure into segments and identify structure seeds; 2) construct an excitation and extraction technique that only involves surface unknowns; 3) form a surface-based finite-element matrix for each segment; and 4) assemble the segmental matrices to form the final system matrix and solve it. These four steps will be elaborated in the following four sections. A. Step I: Slice Structure Into Segments and Identify Structure Seeds The decap structure can be sliced along any of , , and directions (refer to Figs. 1 and 2 for the coordinate system). Here, we choose so that the resultant cross section has the minimal size. We also slice the structure in a way that the resultant segment has a constant cross section. Take an eight-terminal decap as an example; Fig. 3 depicts how the structure is sliced from both a perspective view and a top view. As can be seen clearly, along the direction, the segments can be categorized into three structure seeds as shown in Fig. 4. Structure seed 1 only involves interleaved power and ground planes; structure seed 2 involves
Fig. 4. Structure seeds. (a) Structure seed 1. (b) Structure seed 2. (c) Structure seed 3.
power/ground planes and VSS vias/contacts at the left-hand side and VCC vias/contacts at the right-hand side; and structure seed 3 is made of power/ground planes and VCC vias/contacts at the left-hand side and VSS vias/contacts at the right-hand side. Obviously, structure seed 3 can be obtained by flipping over structure seed 2 horizontally. Hence, these two seeds only need to be characterized once. B. Step II: Construct Excitation and Extraction Technique That Only Involves Surface Unknowns As the author stated in [10], the solution of Maxwell’s equations is the field or field at the discretized points inside the computational domain. However, the design parameters of interest are generally circuit parameters such as -, - or -parameters at the terminals/ports of interest. Therefore, instead of constructing an electromagnetic solution at discretized points inside the circuit structure, it is more efficient to formulate a circuit abstraction of the original Maxwell’s system. This abstraction results in a system that only involves fields that contribute to the final circuit parameter extraction. Certainly, the fewer the field unknowns involved in the circuit parameter extraction are, the smaller the abstracted system will be, and hence the more efficient the simulation will result. Here, we construct an excitation and extraction technique that only involves surface unknowns. First, we assign a port to each decap terminal. We then introduce a vertical current probe between the backplane and the decap terminal as shown in Fig. 5. The right-hand sides in (5) corresponding to the field unknowns associated with the current probe become (8)
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From (9), apparently, in order to eliminate volume unknowns, one needs to fill in matrices , , , , , and for each seg, , and ment. In addition, one has to evaluate for each segment. In fact, one only needs to evaluate for each structure seed. This is achieved by exploring the following matrix properties as derived in [15]. 1) Matrix is the same for all the segments. 2) Matrices and are correlated: . 3) Matrix is equal to matrix in each segment. 4) Matrix is linearly proportional to the segment length. 5) Matrix only needs to be formed and inverted for each unique structure seed. is assembled from the following elemental In fact, matrix matrix:
Fig. 5. Excitation and extraction scheme.
(10)
Fig. 6. Procedure of eliminating volume unknowns.
in which is the current and is the length of the current probe. We then inject current to each port in turn. When we inject current into one port, we leave other ports open. We then sample the voltage generated at each port. The voltage can be evaluated by performing a line integral of the electric field from the port to the backplane. Thus, we obtain one column of the impedance matrix . We then inject current into another port. We can obtain another column of matrix. We continue this procedure until all the ports are excited. Finally, we obtain the entire matrix. From the matrix, one can easily obtain both - and -parameter matrices. Clearly, the field unknowns involved in the excitation and extraction are only located on the surfaces since we segment the structure in direction. And hence only these surface unknowns are required to be preserved in the final matrix system. All the other unknowns can be eliminated. C. Step III: Form a Surface-Based Finite-Element Matrix for Each Segment To form a matrix system that only involves surface unknowns in each segment, we need to eliminate volume unknowns. For , instance, the volumetric unknowns in segment 1, which is can be eliminated by using the procedure illustrated in Fig. 6. and are the surface unknowns on the top and bottom surfaces of segment 1. In Fig. 6, the relationship between the transformed matrices and the original ones can be written as
(9) Essentially, the volume unknowns are eliminated by using the relationship between the surface and volume unknowns, which is dictated by the second row of the original matrix shown in Fig. 6.
in which is the segment length, is the node basis function [11, pp. 80], and denotes the region forming a triangular element. Clearly, matrix only needs to be formed and inverted for a segment of unit length. Others can be obtained by scaling accordingly. Moreover, matrix of unit length is different only when the conductor and permittivity configuration is different, is different. Hence, in decap structures, matrix only i.e., needs to be formed and inverted for each structure seed of unit in each segment can then be length. The inverse of matrix readily obtained by linearly scaling the structure-seed-based inverse matrix with the segment length . As an immediate result of the aforementioned factors, the computational cost of eliminating all the volume unknowns only for each structure seed. Generally, involves solving there exist only a few structure seeds in decap structures. For example, an eight-terminal decap has only two structure seeds (seeds 2 and 3 are essentially the same) as can be seen from Fig. 4. As another example, a 10- or 12-terminal decap has only three structure seeds as can be seen from Fig. 2. In addition, and are extremely sparse matrices. Therefore, the reduction from the original 3-D volume-based matrix to a 2-D surface-based one can be performed very efficiently. D. Step IV: Assemble Segmental Matrices to Form Final System Matrix and Solve it With all the volume unknowns eliminated, we assemble the segmental matrices as shown in Fig. 7 to form the final system matrix. Each segmental matrix interacts with its neighbors only through surface unknowns residing on the interfaces. Since the system matrix size is reduced significantly, it can be readily solved. Here, a multifrontal-based method [16] is used to solve the reduced system matrix. III. NUMERICAL RESULTS AND EXPERIMENTAL VALIDATION In order to validate the accuracy and efficiency of the proposed method, we simulated a set of benchmark examples and compared simulation results with both measurements and HFSS (a commercial finite-element-based full-wave solver [13]). The first example is a two-terminal package decap with eight interleaved power/ground planes. It preserves all of the geometrical dimensions and material parameters of their realistic package decap counterparts. But, it has fewer interleaved
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Fig. 7. Final system matrix formed by surface unknowns in each segment.
Fig. 9. Impedance magnitude of a 0805 eight-terminal capacitor with eight power/ground planes.
Fig. 10. Test fixture structure for capacitor measurements.
Fig. 8. Magnitude of input impedance of a two-terminal decap simulated by proposed method and HFSS.
power/ground planes so that a traditional finite-element solver can handle them within feasible runtime and memory. The relative permittivity of the decap fill-in material is 3000. The thickness of the power and ground planes is 5.1 mu. The spacing between power and ground planes is 2.55 mu. The decap is of width 1438 mu, and length 3162 mu. The input impedance simulated by the proposed method shows an excellent agreement with that calculated by HFSS as can be seen clearly from Fig. 8. The proposed method costs less than one minute and tens of MB in characterizing the decap within the entire band of interest. In contrast, HFSS expends 2-Gb memory and 20-h CPU time [9]. We recognize the fact that HFSS is a tool developed for general 3-D high-frequency structures without taking decap-specific information into consideration. The proposed scheme is developed for decap modeling. It is also suitable for arbitrarily shaped multilayer structures. The second example is an eight-terminal package decap as shown in Fig. 3(a). The number of interleaved power (VCC) and ground (VSS) planes is eight. The bottom plane is VSS. The decap is immersed in a dielectric material with 3000 relative permittivity and loss tangent 0.02. The thickness of both VCC and VSS planes is 0.0036 mm. The spacing between power and ground plane is 0.0024 mm. The distance from the top terminals to the topmost power/ground plane is 0.1109 mm. The distance from the bottom terminals to the bottommost power/ ground plane is 0.0935 mm. The terminal thickness is 0.0165
mm. The thickness of top air stack and bottom air stack is 0.1 and 0.065 mm, respectively. The proposed method and HFSS are used to simulate this decap. Both computed an 8 8 -parameter matrix, from which the input impedance between power and ground is derived by connecting four VCC terminals to the power and the four VSS terminals to the ground. Fig. 9 shows the simulated input impedance which reveals an excellent agreement between the proposed method and HFSS. Again, the proposed method exhibits 100 performance gain in both CPU and memory requirement. In order to apply to a realistic decap structure consisting of a large number of interleaved VCC and VSS planes, we validated the accuracy of the proposed method by comparing to two-terminal capacitor measurements. An AVX 0612 0.47 was chosen, and the cross-sectional view is shown in Fig. 1(a). Two-port measurements using an HP 8753D Vector Network Analyzer (VNA) were done for characterizing a frequency-dependent response of the capacitor in the range of 30 kHz to 3 GHz. Using short, open, load, and through (SOLT) calibration, the two-port measurements were made with Cascade Microtech 250 m GS and SG probe sets. However, since the capacitor itself cannot be measured directly, a test fixture structure shown in Fig. 10 was attached for the measurement purpose. By neglecting a very small voltage drop due to the separation between Ports 1 and 2, only a transfer -parameter ( ) can be used to extract such a small impedance of a capacitor ( ) since the two-port measurements reduce the error due to the series probe connection impedance and the transfer impedance becomes self-impedance as the ports are closer [14]. Based on the
JIAO et al.: EFFICIENT FULL-WAVE CHARACTERIZATION OF DISCRETE HIGH-DENSITY MULTITERMINAL DECOUPLING CAPACITORS
Fig. 11. Impedance magnitude of an AVX 0612 0.47 F two-terminal capacitor simulated by proposed method in comparison with measurements.
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Fig. 12. Illustration of geometrical parameters. (a) Side view. (b) Eight-terminal capacitor’s top view. (c) Two-terminal capacitor’s 3-D view.
two-port measurements, the unknown capacitor impedance can be computed as follows [14]:
(11) Since the structure involves a large number of interleaved VCC and VSS planes, due to the large memory requirement, HFSS has difficulty in simulating this example. In contrast, the proposed method finishes the simulation in a few minutes costing only tens of Megabyte memory. Fig. 11 shows the impedance comparison for an AVX 0612 0.47 two-terminal capacitor between the proposed method and measurements, which exhibits an excellent agreement. In the measurements, the capacitance of the capacitor is de-embedded from the fixture parasitics, which can be measured by shorting the capacitor pads. Despite the excellent agreement, in Fig. 11, we also observe that the measured and simulated capacitance and ESR reveal a slight discrepancy. In addition, the simulation result shows a peak parallel resonance around 100 MHz which is not observed in the measurement. This could be due to some inaccuracies in the metal conductivity, dielectric constant, and loss tangent values that are fed into the simulation tool. Although geometrical data was obtained by cross-section measurements, the material parameters were obtained from the vendor’s datasheet. As a result, while capacitance which matches the modeling result shows 0.47 the vendor’s datasheet, the actual capacitance is measured to be . As another factor, the layers of capacitors are around 0.43 not uniformly flat, as shown in Fig. 1(b), which is not included in the simulation. IV. PARAMETRIC STUDY FOR OPTIMUM DESIGN OF DECOUPLING CAPACITORS Once the efficient full-wave characterization of the decoupling capacitors was achieved, different configurations of multiterminal capacitors were extensively studied for an optimum design. Based on the geometrical parameters shown in Fig. 12, the sensitivity of the input impedance was tested by sweeping
Fig. 13. Equivalent loop inductance representation of capacitor.
different geometrical parameters. Fig. 14 shows the impedance comparison as the parameters of interest are varied as , , and while other parameters are fixed. To aid the understanding of Fig. 14, we plot an approximate equivalent circuit to represent the capacitor’s loop inductance in Fig. 13. In Fig. 13, the total loop inductance of a capacitor (equivalent series inductance ESL) is the sum of . Here, , , and are denoted as vertical, horizontal, and mutual inductances, respectively. Fig. 14(a) shows the impedance variation with increased number of layers. It is observed that as the number of power/ground plane pairs increases, the capacitance increases linearly as expected, but reduces and becomes negligible. As a result, the ESL becomes close to . Fig. 14(b) illustrates capacitor performance versus the width of capacitor, which is indicated by parameter “ ” in Fig. 12(a). By increasing the parameter “ ” with other parameters fixed, reduces due to large separation between power and ground terminals, and therefore the overall ESL is increased. Meanwhile, because of the increased area between power and ground planes, the overall capacitance value is increased. In Fig. 14(c), by increasing “ ” both and increase with the same capacitance; however, the sum of vertical and mutual inductance ( ) increases in proportion to the length of the parameter “ ” which is the reason why all the capacitor manufacturers try to minimize “ .” Fig. 14(d) shows how
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Fig. 14. Input impedance with different design configurations: solid line-1X, dashed line-0:5X, and dotted line-2X of parameter.
the impedance changes with variable “ .” Because ac current always flows in its lowest impedance path, increasing variable “ ” (in the direction outward capacitor) will not make any ESL and capacitance change, and that is why the impedance magnitude is close in Fig. 14(d). Fig. 14(e) shows the change of impedance with respect to the variation of parameter “ .” It is clearly observed that both capacitance and ESL are improved. While Fig. 14(a)–(e) focuses on the parameters in a two-terminal capacitor, Fig. 14(f) shows how the impedance varies as a function of the terminal width (“ ”) in an IDC (eight-terminal) capacitor. As “ ” is increased, “ ” is decreased to keep the pitch between the terminals constant. As can be seen clearly from Fig. 14(f), the terminal width has no impact on the capacitance of the structures as expected. However, by increasing the terminal width, the mutual coupling between terminals of alternating polarities is increased which reduces the overall inductance. In addition, the wider terminals also reduce the ESR of the capacitor. The low ESL of IDC capacitors is one of the reasons why they are preferred over two-terminal capacitors for high-frequency decoupling in power delivery application. As a summary of these parameter sweepings, there are three strategies we can apply for better capacitor design. First, in order to increase capacitance without an additional side effect on ESL, the number of planes or dielectric constant need to be increased. Second, to reduce the ESL without reducing capacitance, the shortest distance of the parameter “ ” should be designed and manufactured. Third, to increase capacitance and to reduce inductance at the same time, the parameter “ ” in Fig. 12(c) needs to be large for both two-terminal and multiterminal capacitors. In addition, to maximize the effect of mutual inductance between terminals in multiterminal capacitors, the separation “ ” needs to be as small as possible.
Fig. 15. Typical power delivery network in a computer system.
V. APPLICATION OF FULL-WAVE CAPACITOR MODEL TO SYSTEM-LEVEL POWER DELIVERY ANALYSIS The full-wave model obtained from the proposed method was incorporated into a high-performance microprocessor’s power delivery network to investigate system performance. Fig. 15 shows the topology of a typical power delivery network. The package decoupling capacitor is highlighted by the colored box. Three capacitor models are used to examine the impedance of the power delivery network looking back from the circuit load. The first model is the full-wave -parameter model obtained from the proposed method. The second one is an equivalent series RLC representation where both ESR and ESL are obtained based on the null resonant frequency, and the last one applies a linear inductance approach to obtain ESR at the null resonant frequency and ESL at the highest frequency. As can be seen clearly from Fig. 16, there is a large discrepancy between the input impedance calculated from the full-wave -parameter model and those obtained from the other two
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method has also been incorporated into a high-performance microprocessor’s power delivery network to investigate system performance. REFERENCES
Fig. 16. Input impedance of typical power delivery network obtained from three capacitor models.
conventional lumped RLC models in the high-frequency range, especially at the highest resonant frequency that is coupled with the on-chip capacitor. In addition, for a fixed impedance target, the full-wave model is shown to require fewer capacitors compared with the conventional single element ESL, ESR, and C model since the latter overestimates the impedance. This phenomenon could be attributed to the higher ESR in the high-frequency range and higher order mode effects that cannot be captured by the circuit-based approaches. VI. CONCLUSION An efficient surface-based finite-element solution was presented for the fast and accurate full-wave characterization of high-density and multiterminal decoupling capacitors. In contrast to traditional finite-element methods that involve 3-D volumetric unknowns, this method reduces the unknowns one needs to solve to those on 2-D surfaces only. Furthermore, the reduction from the 3-D volume-based matrix to a 2-D surface-based one is achieved efficiently by exploiting the geometrical specialty of the decap structure. The entire numerical procedure is numerically rigorous without making any theoretical approximation. The method preserves the advantages of the finite element method in circuit application such as the flexibility in modeling irregular geometry, the capability in handling arbitrary inhomogeneity, and sparse matrices. Meanwhile, it eliminates its disadvantages such as large memory requirement and high CPU cost resulting from 3-D volumetric discretization. The accuracy and efficiency of the proposed method has been validated by numerical experiments and the comparison with measurements. Different design configurations of capacitors were studied to identify the optimal configuration that can maximize the performance of a decoupling capacitor. The results show that the ESL of a capacitor is dominated by capacitor terminal inductance and that the impact of planar layer section is a secondary effect. In addition, the full-wave capacitor model has been compared with the conventional lumped element (ESR, ESL, and C) model. It is shown that the full-wave model captures high-frequency effects and predicts power delivery system impedance more accurately in the high-frequency region. For a fixed impedance target, the full-wave model also results in fewer numbers of capacitors compared with a single lumped RLC model. The full-wave model obtained from the proposed
[1] J. He, D. Zhong, S. Y. Ji, G. Ji, Y. L. Li, and D. G. Figueroa, “Study of package EMI reduction for GHz microprocessors,” in Proc. 11th Topical Meeting Electrical Performance of Electronic Packaging, Oct. 2002, pp. 271–274. [2] R. R. Tummala, E. J. Rymaszewski, and A. G. Klopfenstein, Microelectronics Packaging Handbook, 2nd ed. New York: Chapman and Hall, 1997, pt. I. [3] T. Takken, “Integral decoupling capacitors reduces multichip module ground bounce,” in Proc. IEEE Multichip Module, Mar. 1993, pp. 79–84. [4] T. Chou, “Effect of on-package decoupling capacitors on the simultaneous switching noise,” in Proc. 6th Topical Meeting Elect. Perform. Electron. Packag., Oct. 1997, pp. 55–58. [5] Y. L. Li, D. G. Figueroa, J. P. Rodriguez, L. Huang, J. C. Liao, M. Taniguchi, J. Canner, and T. Kondo, “A new technique for high frequency characterization of capacitors,” in Proc. 48th Electronic Components Technology Conf., May 1998, pp. 1384–1390. [6] Y. L. Li, T. G. Yew, C. Y. Chung, and D. G. Figueroa, “Design and performance evaluation of microprocessor packaging capacitors using integrated capacitor-via-plane model,” IEEE Trans. Advanced Packag., vol. 23, no. 3, pp. 361–367, Aug. 2000. [7] L. D. Smith and D. Hockanson, “Distributed SPICE circuit model for ceramic capacitors,” in Proc. 51st Electronic Components Technology Conf., May 2001, pp. 523–528. [8] L. D. Smith, D. Hockanson, and K. Kothari, “A transmission line model for ceramic capacitors for CAD tools based on measured parameters,” in Proc. 52nd Electronic Components Technology Conf., May 2002. [9] J. Kim, D. Jiao, J. He, K. Radhakrishnan, and C. Dai, “Characterization of discrete decoupling capacitors for high-speed digital systems,” in Proc. 54th Electronic Compon. Technol. Conf., 2004, pp. 259–265. [10] D. Jiao, S. Chakravarty, C. Dai, and S. W. Lee, “Surface-based finite element method for large-scale 3D circuit modeling,” in Proc. IEEE 14th Topical Meeting Electrical Performance Electronic Packag., 2005, pp. 347–350. [11] J. M. Jin, The Finite Element Method in Electromagnetics, 1st ed. New York: Wiley, 1993. [12] R. D. Graglia, D. R. Wilton, A. F. Peterson, and I. Gheorma, “Higher order interpolatory vector bases on prism elements,” IEEE Trans. Antennas Propagat., vol. 46, no. 3, pp. 442–450, Mar. 1998. [13] HFSS [Online]. Available: www.ansoft.com [14] I. Novak, “Frequency-domain power-dsitribution measurement—An overview,” in DesignCon East, Boston, MA, Jun. 2003. [15] D. Jiao, S. Chakravarty, and C. Dai, “A layered finite-element method for high-capacity electromagnetic analysis of high-frequency ICs,” IEEE Trans. Antennas Propagat., vol. 55, no. 2, pp. 422–432, Feb. 2007. [16] UMFPACK [Online]. Available: http://www.cise.ufl.edu/research/sparse/umfpack/ Dan Jiao (S’00–M’02–SM’06) received the Ph.D. degree in electrical engineering from the University of Illinois, Urbana-Champaign, in October 2001. She then worked at Technology CAD Division, Intel Corporation, until September 2005 as Senior CAD Engineer, Staff Engineer, and Senior Staff Engineer. In September 2005, she joined, School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN, as an Assistant Professor in the School of Electrical and Computer Engineering. She has authored two book chapters and over 65 papers in refereed journals and international conferences. Her current research interests include high-frequency digital, analog, mixed-signal, and RF IC design and analysis, high-performance VLSI CAD, modeling of micro- and nano-scale circuits, computational electromagnetics, applied electromagnetics, fast and high-capacity numerical methods, fast time-domain analysis, scattering and antenna analysis, RF, microwave, and millimeter wave circuits, wireless communication, and bio-electromagnetics. Dr. Jiao received the 2006 Jack and Cathie Kozik Faculty Start-up Award, which recognizes an outstanding new faculty member at Purdue University. In 2004, she received the Best Paper Award from Intel’s annual corporate-wide
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technology conference (Design and Test Technology Conference) for her work on generic broadband model of high-speed circuits. In 2003, she won the Intel Logic Technology Development (LTD) Divisional Achievement Award in recognition of her work on the industry-leading BroadSpice modeling/simulation capability for designing high-speed microprocessors, packages, and circuit boards. She was also awarded the Intel Technology CAD Divisional Achievement Award for the development of innovative full-wave solvers for high frequency IC design. In 2002, she was awarded by Intel Components Research the Intel Hero Award (Intel-wide she was the tenth recipient) for the timely and accurate 2-D and 3-D full-wave simulations. She also won the Intel LTD Team Quality Award for her outstanding contribution to the development of the measurement capability and simulation tools for high-frequency on-chip crosstalk. She was the winner of the 2000 Raj Mittra Outstanding Research Award given her by the University of Illinois . She has served as the reviewer for many IEEE journals and conferences.
Joong-Ho Kim received the M.S. and Ph.D. degrees in electrical and computer engineering from Georgia Institute of Technology, Atlanta. He is currently a Senior Member of Technical Staff at Rambus, Inc., Los Altos, CA. He is responsible for product design and analysis in signal/power integrity (SI/PI) area for high performance memory interface products such as XDR, DDR2/3, and GDDR. Previously, he was working on SI/PI analysis for CMOS microprocessors and in-house tool developments at Intel Corporation. He has 25 publications in
refereed journals and conferences, five issued patents, and two patents pending. His current research interests include systematic approach considering both signal and power integrity simultaneously, the characterization of high-speed interconnects, S-parameter-based simulation using VNA measurements or full-wave solvers, and the macro-modeling for circuit simulations. Dr. Kim received a Best Student Paper Award at EPEP ’00, the First Place Poster Award at NSF-PRC’ 00, and Best Paper Award at Intel DTTC’ 04.
Jiangqi He (M’01) received the Ph.D. degree in electrical engineering from Duke University, Durham, NC, in 2000, in the field of computational electromagnetics. He has been with the Electrical Core Competency Team at Intel Corporation, Chandler, AZ, since 2000. He has been working on power delivery, high-speed signaling, EMI/EMC, and RF packaging with a focus on interconnect technologies. Currently, his main interest is in high-speed interconnect technologies for computer systems.
