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Electromagnetic compatibility of voltage source inverters for uninterruptible power supply system depending on the pulse-width modulation scheme Krzysztof Bernacki and Zbigniew Rymarski Institute of Electronics, Faculty of Automatic Control and Computer Science of the Silesian University of Technology, 44-100 Gliwice, Akademicka 16, Poland E-mail:
[email protected];
[email protected].
Abstract — The PWM scheme is an algorithm for inverter switch control. A two-leg bridge and three-level PWM are typical solutions in voltage source inverters in UPS systems. The three PWM schemes that are used in inverters are compared herein. Each scheme has different features, including the level of noise generated and interference in the different frequency ranges. The aim of this paper is to analyse the characteristics and electromagnetic interference that is generated by an inverter using different PWM schemes.
Index Terms— EMC - electromagnetic compatibility, EMI – electromagnetic interferences, pulse width modulation converters, radiated emission, conducted disturbances.
I.
INTRODUCTION
The sinusoidal CVCF (constant voltage constant frequency) PWM modulation [1-4] (sometimes called the CB-PWM-carrierbased PWM) is the standard solution in voltage source inverters (VSIs) in UPS systems that have a restricted THD (Total Harmonic Distortion - EN 62040, i.e., the ratio of the RMS amplitude of a set of higher harmonic frequencies to the RMS amplitude of the first harmonic) of the output sinusoidal voltage. In a single-phase VSI, two-level, three-level or multilevel PWM can be used [4-5]. The two first types of modulation can be realised in the same bridge inverter (four switches, two legs), but the multilevel inverters [6] require numerous switches. It can easily be proven [2] that a two-level PWM has the highest THD level for an unfiltered signal in the low amplitudes (low modulation coefficient M) of the generated sinusoidal waveform. In this
2 case, the duty cycle of the modulated rectangle waveform is 50% for a zero value of the modulating signal. It is possible to reduce the THD without improving the inverter architecture using a three-level PWM. In this case (Fig. 1a), the duty cycle of the modulated rectangular signal is zero for a zero value of the fundamental waveform. In three-phase inverters, the two-level PWM is still the most popular because the standard six switches and three-leg bridge are sufficient for this modulation [7]. A regularsampled symmetrical strategy PWM type [1] is the standard in microprocessor-based inverter controls because the reference sinusoidal signal is stored in a discrete (step-like) form. There is one discrete value (in some rare, non-symmetrical strategies, there is more than one “step”) per switching cycle. The high input frequency of the comparator timer in the PWM unit ensures the high-resolution generation of the sinusoidal waveform [8]. The input frequency of a double-edge PWM unit should be more than 68 MHz for the fundamental frequency fm=50 Hz and the switching frequency fc=512fm=25600 Hz (e.g., an affordable 84 MHz STM32F4xx microprocessor) [8]. A small additional error is not introduced into the modulation for such a frequency – the resolution is sufficient to distinguish all of the different switching time intervals during one fundamental period because the values of the stored reference waveform samples in the neighbouring intervals are different, even those close to π/2. A doubleedge PWM has lower low-frequency harmonics (≤9fm) than does a single-edge PWM. A double-edge PWM is an available function in all contemporary microprocessors (AVR, ARM, and Cortex families). These low-frequency harmonics cannot be damped by a low-pass inverter output LC filter because they have a substantially lower frequency than the filter cut-off frequency.
a) Spectrum of the regular-sampled, double-edge, three-level PWM output vPWM voltage, fc/fm=512. Fig. 1. The three-level PWM H-bridge inverter.
b) H-bridge output vPWM voltages for the two- and three-level PWM – a description of the used control variables is presented later in the paper.
3 The value of the output filter inductance causes some problems for a standard (EN 62040-3) nonlinear load. It could be lowered using multilevel inverters [3-4], but a three-level double-edge sinusoidal PWM appears to be an adequate solution for an inexpensive low and medium power single-phase VSI for a UPS. Studies on performance are relative. They must show the differences in the levels of the radiated and conducted disturbances when varying the PWM modulation scheme algorithm. The use of non-linear loads (according to EN 62040-3) could introduce additional disorder that may dominate the results of the research. Only static resistive loads were used. The issue associated with selecting the appropriate control algorithms is not the only domain of the PWM modulation schemes and is not limited to the basic inverter structure. The impedance network [9] can also be used to increase the output voltage. The impedance network structures (e.g., ZSI, qZSI, LCCT-ZSI, SLZSI) [10-16] use the additional “shoot-through” states of the inverter switches during the inverter zero states to store energy in coils and result in increased output voltage. The pulse current flowing through the inverter switches during the “shoot through states” has an instantaneous amplitude that exceeds the amplitude of the load current and markedly increases disturbances. The analysis of such algorithms is not the focus of this paper. The choice of magnetic material in the core of chokes or transformers can impact the level of electromagnetic disturbance [17]. Power losses in choke cores that are made of soft magnetic materials cause additional serial equivalent resistances in the LC circuits. Evaluating the impact that the equivalent resistances have on the level of electromagnetic disturbances is difficult; however, these resistances increase the damping coefficients in LC circuits, thereby reducing the level of disturbances.
II.
THREE-LEVEL SINGLE-PHASE PWM SCHEMES
There are three possible control switches in the bridge (a two-leg inverter), which are called “PWM schemes”, that can be used to generate the three-level, single-phase PWM output voltage. The first two schemes are well known, and they were presented in [18]. All of the transistors (Fig. 1b) are switched with a frequency fc in the first PWM scheme (Fig. 2a), but the switching frequency of vPWM is doubled to 2fc because the conjunction of two serially connected switches (S11 and S22 or S21 and S12) results in two pulses during one switching period. The disadvantage of this scheme is that the common voltage vN0 noise (this changes as the voltage at S22 switches with a frequency fc) can lead to problems with the EMC (electromagnetic compatibility) [18]. The numerical control is as follows: for k 1...( f c / f m )
S11 : TON (k ) / Tc 0.5M sin(2kfm / f c ) 0.5M S12 : NOT (S11) S 21 : TON (k ) / Tc 0.5M sin((2kfm / f c ) ) 0.5M S22 : NOT (S21)
4 In the second PWM scheme (Fig. 2b), the switches S11 and S12 are switched at a high frequency fc, but switches S21 and S22 are switched only with the fundamental frequency fm. This results in lower dynamic power losses, and the common voltage vN0 has a low frequency fm. The EMC also appears to exhibit fewer problems. However, the immediate change in the duty cycles of S11 and S12 from a minimum to a maximum value, and vice versa, must be precisely synchronised with the change in the 50 Hz square waveform that controls the S21 and S22 coupling. In a real device, there is always a small mismatch of these events (e.g., delay), which causes a distortion when the output voltage crosses zero. This distortion may cause the minor problems with the EMC. The numerical control is as follows: for k 1...( f c / f m )
S11 : TON (k ) / Tc M sin(2kfm / f c ) for mt , TON (k ) / Tc 1 M sin(2kfm / fc ) for mt S12 : NOT (S11) S21 : S21 OFF for mt , S21 ON for mt S22 : NOT (S21)
a) The first PWM scheme of the threelevel PWM with the modulated signal frequency fc doubled.
b) The second PWM scheme of a threelevel PWM with one bridge leg S21/S22 switched with the fundamental frequency fm.
c) The third PWM scheme of a threelevel PWM without any issues with the synchronisation of the control waveforms of the second PWM scheme (Fig. 2b) and the EMC issues of the first PWM scheme (Fig. 2a).
Fig. 2. Three different PWM schemes analysed in this paper
The third PWM scheme has not previously been presented in the literature [2], although the scheme can be found in devices that are used in industry. In this scheme, two switches from the same bridge leg utilise complementary switching with the high frequency fc in each half of the fundamental period, and the two switches of the other bridge leg have steady ON and OFF values
5 (Fig. 2c). In the other half of the fundamental period, the control of the pairs of switches changes. There is no problem with the synchronisation of the two waveforms because the fc and fm frequency waveforms can be generated using the same switch shown in Fig. 2c. The common voltage has a steady value vN0 during one half of the fundamental period and the value vH0 during the second half. A higher EMC of the inverter compared with the first scheme can be expected. Because there is a possibility of removing the distortions from the output signal when the output voltage crosses zero, synchronisation does not produce any problems, which makes the third scheme appear to be the best PWM scheme. The numerical control is as follows: For k 1...( f c / f m )
S11 : TON (k ) / Tc M sin(2kfm / f c ) for mt , S11 OFF for mt S12 : NOT (S11) S21 : S21 OFF for mt ,
TON (k ) / Tc M sin(2kfm / fc ) for mt S22 : NOT (S21)
a)
b)
c)
Fig. 3. Experimental inverter voltage output filtered vOUT voltages for the open feedback loop and the resistive 2000 ohm load: a)vOUT of the first PWM scheme, b)vOUT of the second PWM scheme, c)vOUT of the third PWM scheme Figs. 3 and 4 show the filtered experimental inverter output voltages vOUT for an open feedback loop and for a resistive load for the three types of PWM schemes. The small synchronisation shift between the couples of control signals S11, S12 and S21,
6 S22 was deliberately introduced (Figs. 3b and 4b) to reduce the small voltage peaks after the zero crossings. Various advantages and disadvantages of the discussed modulation schemes are presented in Table 1.
a)
b)
c)
Fig. 4. Experimental inverter voltage output filtered voltages vOUT for the open feedback loop and the resistive 47 ohm load: a) vOUT of the first PWM scheme, b) vOUT of the second PWM scheme, c) vOUT of the third PWM scheme
Table 1. Advantages and disadvantages of the three different PWM schemes analysed in this paper
Advantages The first PWM scheme
Disadvantages
-Widely used.
-This PWM scheme causes common mode HF noise
-The double PWM output waveform frequency,
that is higher than in other PWM schemes, which can
compared to the switching frequency of bridge
lead to EMI (electromagnetic interferences) issues;
transistors,
the EMI level can be reduced using an output filter
enables
a
decreased
output
filter
inductance and improves the dynamic properties of
but remains high.
the voltage source inverter.
-All transistors are switched with high frequency, which increases energy losses. -The position of the output sinusoidal voltage zero crossing depends on the accuracy of the phase shift
7 of the two modulating signals.
The second PWM scheme
-Only the H inverter bridge leg (S11 & S12 switches)
-A small phase shift between a 50 Hz square
is switched at high frequency; the L leg (S21 & S22
waveform in one H bridge leg and the high-
switches) is switched at the low fundamental
frequency PWM waveform in the second leg causes
frequency,
electromagnetic
distortions of the output voltage when crossing the
interference. The high-frequency EMI effect is
zero because the modulating waveform is stepwise
smaller than that in the first PWM scheme.
varying (from zero to the maximum value, or vice
-Switching transistors in one leg of the inverter H
versa) at this time.
which
decreases
bridge with the low fundamental frequency decreases power losses.
The third PWM scheme
-All the transistors in the H bridge are switched at
-This scheme cannot distinguish which transistors
the high frequency (fc) only in the first half of the
are switched at the low frequency fm and which are
fundamental period, and in the second half, they are
switched at the high frequency fc (compared with the
steadily switched ON or OFF, which decreases
2nd scheme); all the transistors should be the same
electromagnetic interference and power losses
fast switching type.
compared to the first PWM scheme. -There are no issues with the synchronisation of the waveforms in both H bridge legs when the voltage waveform crosses zero because the modulating waveform is never stepwise varying at this time. -Ease of implementation in the control of the impedance networks (Z-Source).
General
-During the measurements, the same hardware model (PCB and components) was used, and only the software was different for each PWM scheme. -The same processor and the same CPU frequency in the inverter control system were used. -The same switching frequency was used in all of the PWM schemes.
III. ELECTROMAGNETIC COMPATIBILITY INVESTIGATION The measurements were performed in a certified three-meter anechoic chamber equipped with CHC Franconia. Specialised equipment, according to [19], that was sensitive to any disturbances that were radiated in the frequency range of 0.03-1 GHz and to any conducted disturbances in the range of 0.15-30 MHz was used to perform the measurements. In addition, a near-field probe was used (Fig. 5a) to verify the results that were obtained. All of the measurements that are presented are relative and were
8 obtained after testing under identical conditions. The tests were carried out using the same experimental model (Fig. 5b) that was subjected to a change in the three control algorithms (using an ARM 7 microprocessor), the so-called PWM modulation scheme. The experimental setup that was analysed was designed in accordance with the accepted principles of electromagnetic compatibility and in accordance with engineering practice [20-26]. During the inverter design, a number of simulations on the usage of the heat sink were performed. Improperly installed radiators that do not account for the appropriate amount and distribution of connections [27] become unintentional antennas and can disrupt the operation of the entire system. It is very important to choose the appropriate heat sink fins [28] and the appropriate locations of the heat sink fins over the heat source [29-30].
a) The near field from the probe that was used can be observed in picture.
b) The experimental model that was tested in an anechoic chamber (Franconia CHC).
c) Simplified view of the switching elements and heat sink.
d) Source position (switches) – bottom side of heat sink.
Fig. 5. Experimental and numerical models.
It is obvious that an increased radiation level is observed at the resonant frequencies of the heat sink. Due to the dimensions of the heat sink, the resonances are expected at the following frequencies (1)
( f r ) m ,n , p
c 2 r
m n p , [ Hz] X Y h 2
2
2
9 where c is the speed of light and m, n, and p denote the number of half-cycle field variations along the x, y, and z directions, respectively. X and Y represent the dimensions of the heat sink (length and width) along the x and y directions, and h is the distance between the heat sink and the ground plane. Because h is very small (h
