electronics Article
Evaluation of LDMOS Figure of Merit Using Device Simulation Aiman Salih and Jiann-Shiun Yuan *
ID
Department of Electrical and Computer Engineering, University of Central Florida, Orlando, FL 32816, USA;
[email protected] * Correspondence:
[email protected]; Tel.: +1-407-8235719
Received: 16 March 2018; Accepted: 26 April 2018; Published: 29 April 2018
Abstract: The benefit of the super-junction (SJ) technique at the low-voltage (30 V) range is investigated in this work. Optimizations such as adding a buffer layer to the device have been used, but simulation and theoretical evidences show that the benefits of the SJ technique are marginal for 30 V applications. The floating P structure proved to be a good replacement for SJ devices at the 30 V range due to a simpler fabrication process as well as performance gains achieved with optimization. Also, a new idea of combining the floating P layer with a shallow trench isolation layer is proposed and simulated using TCAD, yielding the figure of merit (RDS(on) × QG ) of 5.93 mΩ-nC, which is a 39% improvement on the standard floating P device. Keywords: breakdown voltage; gate charge; LDMOS; RDS(on) ; Super-junction; STI
1. Introduction Efficient power supplies with fast transient response and accurate voltage regulation for low-voltage applications are becoming more important in today’s market. This can be mainly attributed to the fast growth and increase in demand for data-centers, as well as the massive increase in the amount of data being transmitted. It is estimated that the amount of annual global data-center traffic will increase from 4.7 zettabytes in 2015 to 15.3 zettabytes in 2020, where 1 ZB = 240 gigabytes [1]. Also, the user base of consumer cloud storage is predicted to increase from 47 in 2015 to 59% in 2020 [1]. With the current system design of data-centers, there is a significant volume of these low-voltage power devices in use when it comes to voltage regulation [2]. As a result, it is critical to optimize the design of these power devices such that high efficiency and performance are achieved in data-center power regulators. The laterally double-diffused metal oxide semiconductor (LDMOS) transistor offers higher levels of integration for integrated circuits (ICs) [3]. As a result, the LDMOS is viewed as a viable solution for advanced systems on a chip (SoC), which have power integrated within the solution combining both high speed digital logic CMOS and high power LDMOS devices onto the same silicon chip [4]. These SoCs are often found in Internet of Things (IoT) applications. LDMOS devices have also found a footing in advanced integrated power electronics modules and electric vehicles that are now rampant in the market. The work presented gives a viable solution for improving upon the design of 30 V power devices. The super-junction (SJ) technique, which involves the use of consecutive N and P pillars in the device’s drift region and is well established in the high voltage (600 V) range, is tested here for the low-voltage range. In [5] the authors attempt to integrate the SJ technique within their low-voltage device design, but from [6,7], and further investigation here, it can be seen that the SJ technique may not be preferred for low-voltage applications. An alternative approach to designing a 30 V power device is proposed by replacing the SJ pillars and the shallow trench isolation (STI) with a floating p-type layer in the drift region. Electronics 2018, 7, 60; doi:10.3390/electronics7050060
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30 30 V V power power device device is is proposed proposed by by replacing replacing the the SJ SJ pillars pillars and and the the shallow shallow trench trench isolation isolation (STI) (STI) with with aa floating p-type layer in the drift region. floating p-type layer in the drift region. Electronics 2018, 7, 60 2 of 10 This This paper paper contains contains five five sections. sections. Following Following the the introduction, introduction, Section Section 22 discusses discusses the the low-voltage Super-Junction LDMOS that was investigated in this work. Section 3 covers all of the low-voltage Super-Junction LDMOS that was investigated in this work. Section 3 covers all of the details floating PP layer device and how be to SJ details for the thecontains floatingfive layer device and explains explains how itit can can be used used to replace replace SJ devices devices at at This for paper sections. Following the introduction, Section 2 discusses the low-voltage low-voltages (30 V range). Section 4 presents a new concept of combing both STI technology low-voltages (30 V range). Section 4 presentsina this newwork. concept of combing both STIthe technology with Super-Junction LDMOS that was investigated Section 3 covers all of details forwith the aa floating to aa device with aa very low of (FOM) (Q G × RDS(on)). Section 5 floating P layer layer to generate generate device with very low figure figure of merit merit (FOM)at (Qlow-voltages G × RDS(on)). Section floating P Player device and explains how it can be used to replace SJ devices (30 V 5 gives a summary. gives Section a summary. range). 4 presents a new concept of combing both STI technology with a floating P layer to generate a device with a very low figure of merit (FOM) (QG × RDS(on) ). Section 5 gives a summary. 2. 2. Low-voltage Low-voltage SJ SJ LDMOS LDMOS Analysis Analysis 2. Low-voltage SJ LDMOS Analysis Figure Figure 11 shows shows aa conventional conventional LDMOS LDMOS used used in in our our simulation, simulation, while while the the structure structure of of the the SJ SJ LDMOS device is displayed in Figure 2. The SJ LDMOS in Figure 2 contains N and P SJ pillars. Figure 1 shows a conventional LDMOS used in our simulation, while the structure of the SJ LDMOS device is displayed in Figure 2. The SJ LDMOS in Figure 2 contains N and P SJ pillars. Shallow trench isolation is in drift This in absorbing the electric LDMOS device is displayed in Figure 2. The SJ LDMOS in Figure contains and P SJ pillars. Shallow Shallow trench isolation (STI) (STI) is used used in the the drift region. region. This2assists assists inN absorbing the peak peak electric field that commonly occurs at the edge of the gate [8]. Both the conventional and SJ devices are trench (STI) is used thethe drift region. This assists in absorbing the peak electric field that field isolation that commonly occursinat edge of the gate [8]. Both the conventional and SJ devices are simulated using two-dimensional (2D) and three-dimensional (3D) Sentaurus Device TCAD. For the commonly occurs at the edge of the gate [8]. Both the conventional and SJ devices are simulated using simulated using two-dimensional (2D) and three-dimensional (3D) Sentaurus Device TCAD. For the conventional itit was possible itit in environment, the SJ two-dimensional (2D) and three-dimensional (3D) Sentaurus TCAD.while For the conventional device, device, was possible to to simulate simulate in aa 2D 2D Device environment, while theconventional SJ LDMOS LDMOS is is simulated in 3D. The SJ LDMOS is quite unique in that the SJ N and P pillars do not exist on the front device, it was possible to simulate it in a 2D environment, while the SJ LDMOS is simulated in 3D. simulated in 3D. The SJ LDMOS is quite unique in that the SJ N and P pillars do not exist on the front facing 2D but pillar array placed within of device, requiring aa 3D The SJ LDMOS is section, quite unique in that the SJ Nis P pillars dothe notwidth exist on the facing 2D cross facing 2D cross cross section, but the the pillar array isand placed within the width of the the front device, requiring 3D simulation [9]. section, but the simulation [9].pillar array is placed within the width of the device, requiring a 3D simulation [9].
Figure LDMOS device. Figure 1. 1. Conventional LDMOS device. Figure 1. Conventional Conventional LDMOS device.
Figure 2. LDMOS device. Figure 2. Super-junction Super-junction LDMOS device. Figure 2. Super-junction LDMOS device.
Table Table 11 lists lists the the super-junction super-junction LDMOS LDMOS key key device device dimensions. dimensions. Table 1 lists the super-junction LDMOS key device dimensions. Table 1. device dimensions. Table 1. Super-junction Super-junction device dimensions. Table 1. Super-junction device dimensions.
Parameter Parameter cell pitch cell channel pitch channel LL channel tLbuff tbuff tbuff tSJ tSJ tSJ WSJ WSJ WSJ
Parameter cell pitch
lSTI tSTI
Size Size 8 µm 1.4 µm 81.4 µm µm 1.42 µm µm 2 µm 2 µm 0.6 µm 0.6µm µm 0.6 0.5 µm 0.5µm µm 0.5 Size 8 µm
2.5 µm 0.3 µm
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lSTI tSTI
2.5 µm 0.3 µm
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Specific On Resistance (Ω−mm2)
The device simulation uses the following physics models: Old Slotboom model [10] for the effective intrinsic carrier density; while doping dependence [11], high field saturation [12], and The device simulation uses the following physics models: Old Slotboom model [10] for the Lombardi [13] models are used for the mobility dependence. Shockley Reed Hall [14], Auger [15], effective intrinsic carrier density; while doping dependence [11], high field saturation [12], and and Okuto avalanche models [16] for the recombination and breakdown current. Lombardi [13] models are used for the mobility dependence. Shockley Reed Hall [14], Auger [15], and Figure 3 compares the on-state resistance (RDS(on)) and gate charge (QG) between the Okuto avalanche models [16] for the recombination and breakdown current. conventional device and the SJ device. Both devices have a breakdown voltage of 30 V. The Figure 3 compares the on-state resistance (RDS(on) ) and gate charge (QG ) between the conventional conventional device has a FOM of 123 mΩ-nC while the SJ device has a FOM of 51 mΩ-nC. Note that device and the SJ device. Both devices have a breakdown voltage of 30 V. The conventional device has RDS(on) and QG are both normalized to an active area of 1 mm2. RDS(on) was examined at the 1 A device a FOM of 123 mΩ-nC while the SJ device has a FOM of 51 mΩ-nC. Note that RDS(on) and QG are both operating point in the linear region. QG was extracted from the gate voltage (VGS) versus QG plot in normalized to an active area of 1 mm2 . RDS(on) was examined at the 1 A device operating point in the Sentaurus. linear region. QG was extracted from the gate voltage (VGS ) versus QG plot in Sentaurus. 3 Super-junction Conventional 2
1
0
100
200
300
400
500
600
Breakdown Voltage (V) Figure 3. 3. Simulated results ofof conventional and SJ SJ devices’ BVDss vs.vs. SpSp RDS(on) Figure Simulated results conventional and devices’ BVDss RDS(on)..
FromTable Table 2 we at the same operating voltage the low-voltage has a From 2 we cancan seesee thatthat at the same operating voltage of 30 of V, 30 theV, low-voltage SJ has aSJslight slight increase in R DS(on) , but a lesser amount of charge is accumulated at the gate terminal. This increase in RDS(on) , but a lesser amount of charge is accumulated at the gate terminal. This leadsleads the SJ device to an have an overall improved lowerthat than of the conventional It is SJthe device to have overall improved FOM, FOM, lower than of that the conventional device. device. It is worth worth pointing that G leads to improved losses, while lower RDS(on) helps pointing out that out lower QGlower leadsQto improved switchingswitching losses, while lower RDS(on) helps reduce reduce conduction losses. Conduction losses are significant in switching power supplies at low conduction losses. Conduction losses are significant in switching power supplies at low frequency [17]. frequency [17]. The conduction losses become an even more critical factor when looking at most The conduction losses become an even more critical factor when looking at most modern soft switching modern soft switching topologies. Soft switching topologies reduce switching losses topologies. Soft switching topologies significantly reduce the significantly switching losses by the switching at either by switching at either zero current or zero voltage [18]. zero current or zero voltage [18]. Table Conventional versus device specific RDS(on)and andQQGG.. Table 2. 2. Conventional versus SJ SJ device forfor specific RDS(on)
Conventional Conventional RDS(on) 87 mΩ-mm2 2 RDS(on) 87 mΩ-mm 2 QG 1.4 nC/mm 2 QG
1.4 nC/mm
SJ Device SJ Device 113 mΩ-mm2 2 113 mΩ-mm 0.45 nC/mm22 0.45 nC/mm
The lack of improvement in RDS(on) of the examined SJ LDMOS device reduces or negates the The of lack of improvement of the examined SJ LDMOS device reducesas or anegates theof benefit using SJ for the 30 in VR range. (1) shows the on-state resistance function DS(on) Equation benefit of using SJ for the 30 V range. Equation (1) shows the on-state resistance as a function of breakdown voltage (BVDss) for both the conventional and SJ devices [6]: breakdown voltage (BVDss) for both the conventional and SJ devices [6]:
R DS(on) =
√ 5 a· B· BVDss 2 µn ·ε· A
conventional
q·µn · ND · A
SJ device
1 7 a· B 6 · BVDss 6
(1)
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where BVDss is the breakdown voltage, a is a constant that discerns between low-voltage and high voltage devices (a = 6.21 for a 30 V conventional device & a = 1.87 for a 600 V conventional device, and a = 6.9 for a 30 V SJ device & a = 2.07 for a 600 V SJ device), B is the radiative recombination constant, µn is the electron mobility, ε is the silicon permittivity, ND is the drift doping, and A is the active area. Equation (1) is often used to derive the silicon limit line (RDS(on) × active area). In capturing RDS(on) in Equation (1) as a function of BVDss, the analytical equation uses the constant a, whose value changes depending on the breakdown voltage of the device. This difference stems from the design of the device and the growth of drift region length as the device size gets larger for higher breakdown voltages. It is worth pointing out that the RDS(on) model presented in Equation (1) is based on a dominant drift resistance. As the size of the device and drift length decrease, the ratio over which the drift resistance contributes to the overall resistance also decreases. For example, for a 600 V device the drift resistance is 96.5% of the total resistance [6]. However, for a 30 V device, the drift resistance is only 29% of the overall on-state resistance. Figure 3 gives a plot of simulated results using Equation (1) comparing the BVDss versus RDS(on) trend for both the super-junction device and the conventional device. From Figure 3 it is evident that for devices with BVDss less than 200 V the conventional device achieves a lower RDS(on) than that of SJ, but this trend is reversed for devices with BVDss greater than 200 V. For this reason, and also from our obtained simulation results, it is evident that the use of SJ technique to design power devices is more suitable to design high voltage power devices [19] than low-voltage ones. The off-state breakdown voltage and on-resistance can be expressed by the analytical equations below: q BVDss =
Ecrit 2 − EL 2 · tSJ
R DS(on) · A =
tSJ · Wn ε · µn · EL
(2)
(3)
where Ecrit is the critical breakdown electric field for silicon, EL = SJ pillars lateral electric field value, tSJ is the SJ pillar depth, Wn is the SJ pillar width. The SJ technique also comes with some process complexities. These arise from the meticulous need to accurately balance the implantation charge required to realize the N and P pillars in the fabrication process. Any implantation imbalance between the pillars leads to a significant reduction in the device’s breakdown voltage [7]. Another issue stems from the scaling of these SJ pillars for low-voltage applications: Equations (2) and (3) list the BVDss and RDS(on) dependence on the depth and width of the SJ pillars [20]. Most modern SJ manufacturing, such as in [21], rely on ion implantation. However, the need to scale down the SJ pillars while at the same time still ensuring their optimal performance may make their fabrication process too challenging and costly, due to the ion scattering that becomes more problematic when features are small. 3. LDMOS with Floating P-Type Layer The implementation of a floating p-type layer in place of the STI gate edge region is a technique that is examined for the LDMOS device; the method is also implemented in [22]. The technique was investigated for low-voltage devices to measure the possibility to outperform SJ in this voltage range. Figure 4 shows a cross section of the device considered. It can be seen from Figure 5 that the device has a simpler 2D cross section when compared to that of the SJ LDMOS. Its device dimensions are given in Table 3. The device cell pitch has also been modified and reduced from 8 µm to 3 µm. This achieves a higher cell density improving the on-state characteristics of the device. Table 2 lists some of the key device dimensions.
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dimensions are are given given in in Table Table 3. 3. The The device device cell cell pitch pitch has has also also been been modified modified and and reduced reduced from from 88 dimensions µm to 3 µm. This achieves a higher cell density improving the on-state characteristics of the device. µm to 3 µm. This achieves a higher cell density improving the on-state characteristics of the device. Table 22 lists lists some of the the key key device device dimensions. dimensions. Electronics 2018,some 7, 60 of 5 of 10 Table
(a) (a)
(b) (b)
(c) (c)
(d) (d)
(e) (e)
(f) (f)
Figure 4. 4. Floating P layer device process flow cross sections (a) gate poly & gate gate ox ox patterned patterned on on Figure Figure 4. Floating P layer device process flow cross sections (a) gate poly & gate ox patterned on surface of wafer (b) N-well & P-well implanted (c) floating P layer deposited (d) source n-type layer N-well & P-well P-well implanted implanted (c) floating P layer layer deposited deposited (d) source n-type n-type layer surface of wafer (b) N-well contacts and and PP+++ body body contact formed. deposited(e) (e)oxide oxidespacers spacersformed formed(f) (f)N N+++ contacts deposited (e) oxide spacers formed (f) N deposited bodycontact contactformed. formed.
Figure 5. 5. Floating Floating PP LDMOS LDMOS device. device. Figure Figure 5. Floating P LDMOS device.
A process process simulation simulation for for the the p-type layer layer device was was developed. developed. The The process simulation sheds A Table 3.p-type LDMOS withdevice floating p-type dimensions. process simulation sheds light on how the added device features can be incorporated with relative ease, especially especially when when light on how the added device features can be incorporated with relative ease, compared to the complex SJ process. Figure 4 shows cross sections of the device throughout the process. compared to the complex SJ process. Figure 4 shows crossSize sections of the device throughout the process. Parameter cell pitch channel L tbuffer lp-layer tp-layer
3 µm 0.34 µm 2 µm 0.61 µm 0.4 µm
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A process simulation for the p-type layer device was developed. The process simulation sheds light on how the added device features can be incorporated with relative ease, especially when compared to the complex SJ process. Figure 4 shows cross sections of the device throughout the process. The device is built on a lattice p-type silicon wafer. The process is self-aligned to the gate: as such, the gate dielectric and the gate poly are initially deposited and patterned on the surface of the silicon wafer using the same mask. The P and N wells are then formed using the same mask with a combination of positive and negative photoresist, such that each dopant is deposited on either side of the gate. A dose of 3 × 1013 cm−2 with an energy of 150 keV is used for the N well, while a dose of 4 × 1013 cm−2 with an energy of 100 keV is used for the P well. The junction depth of the N well is around 1.35 µm, while the junction depth of the P well is around 1.40 µm. For the floating p-type structure, implanting the dopants just under the edge of the gate on the drain side proved challenging, due to the fact that the process is self-aligned to the gate and the thickness of the polysilicon does not permit to implant the dopants directly. To solve this, an angled implant at varying energies was used to achieve the desired structure just under the gate edge. Four different doses of 3.5 × 1012 cm2 were used to obtain the desired profile; the energies used are in the following order: 20, 40, 80, and 160 keV. The process is completed by implanting the phosphorus dopants for the source; a dose of 4.5 × 1013 cm2 is used with an energy of 70 keV. The dopants were activated using rapid thermal annealing (RTA) for 5 mins to stay within the thermal budget. Similarly the P+ body dopants were introduced as well as the N+ contact dopants, RTA is also used here to activate the dopants. This floating P LDMOS process displays the feasibility and replicability of making the floating P device. The process advantage coupled with the performance improvement achieved with further optimization shows how the floating P layer device can outperform SJ devices at the 30 V application. Table 4 gives a comparison of the RDS(on) and QG between the SJ device and the floating p-type layer device. Both devices have a breakdown voltage of 30 V. The FOM of both devices can be determined. The SJ device has a FOM of 51 mΩ-nC while the floating P layer device has a FOM of 9.75 mΩ-nC. Note that both RDS(on) and QG are both normalized to an active area of 1 mm2 . The performance enhancement seen in Table 4 stems from the cell pitch optimization that was given to the floating P device. This led for the device unit cell to occupy less area resulting in an improved normalized RDS(on) and QG values. Table 4. SJ versus floating P device for specific RDS(on) and QG .
RDS(on) QG
SJ Device
Floating P
113 mΩ-mm2 0.45 nC/mm2
63 mΩ-mm2 0.16 nC/mm2
4. LDMOS with STI Region Surrounded by P-Type Layer It was observed that the peak electric field of the floating P LDMOS device occurred on the surface of the p-type layer as shown in Figure 6. It is known that the critical electric field of silicon is around 5 × 105 V/cm; the electric field on the surface exceeds that of the critical electric field as the device approaches breakdown and is the major source of impact ionization in the device. To counter the effects of the surface peak electric field, it was necessary to replace the material of the affected region with a material that has a higher critical electric field. Since the affected region is on the surface of the device, it is feasible with an SiO2 -filled trench realized at the same time and in the same way with the STI used in the fabrication process, as demonstrated in Figure 7.
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Figure 6. Floating P device electric field distribution. Figure6.6.Floating FloatingPPdevice deviceelectric electricfield fielddistribution. distribution. Figure
STI STI width width
p+ n+ p+ n
+
Gate Gate
p p-
-
(a) (a)
Drain Drain n+ n+ nn-
p+ n+ p+ n
+
Gate Gate
p p-
-
Drain Drain n+ n+ nn-
(b) (b)
Figure 7. STI surrounded by floating P LDMOS (a) centered (b) staggered oxide. Figure Figure7.7.STI STIsurrounded surroundedby byfloating floatingPPLDMOS LDMOS(a) (a)centered centered(b) (b)staggered staggeredoxide. oxide.
Table 5 gives the performance of the LDMOS device when the STI surrounded floating P layer Table 5 gives the performance of the LDMOS device when the STI surrounded floating P layer technique applied. devices are designed with a breakdown voltage of 30 V. floating The simulation Table is gives the Both performance of the LDMOS device when the STI surrounded P layer technique is5applied. Both devices are designed with a breakdown voltage of 30 V. The simulation results show that the Both device with the layerahas a FOM ofvoltage 9.75 mΩ-nC the device technique is applied. devices are floating designedP with breakdown of 30 V.while The simulation results show that the device with the floating P layer has a FOM of 9.75 mΩ-nC while the device with STI plus floating P layer has a floating FOM of P5.93 mΩ-nC. That is a 39% improvement the FOM. results the device layer has a FOM while thein with with STIshow plus that floating P layerwith hasthe a FOM of 5.93 mΩ-nC. That isofa9.75 39%mΩ-nC improvement indevice the FOM. From our understanding of the current state of art, the implementation of such floating P layer with STI plus P layer has a FOM of 5.93 That is a 39% improvement in the FOM. From our From our floating understanding of the current statemΩ-nC. of art, the implementation of such floating P layer with a STI region isof athe new design that ledthe towards the givenoflow FOM value observed by device understanding current state of art, implementation such floating P layer with a STI region a STI region is a new design that led towards the given low FOM value observed by device simulation. is a new design that led towards the given low FOM value observed by device simulation. simulation. Table5.5.Floating FloatingPPversus versusSTI STIw/floating w/floatingPPdevice devicefor forspecific specificRRDS(on) DS(on) and Table and Q QG. . Table 5. Floating P versus STI w/floating P device for specific RDS(on) and QG. G
Floating P STI + Floating P FloatingPP STI STI + Floating Floating + Floating P P 2 2 RDS(on) 63 mΩ-mm 22.8 mΩ-mm 2 2 2 2 DS(on) 6363 mΩ-mm mΩ-mm RRDS(on) mΩ-mm 2 22.822.8 mΩ-mm 2 QG 0.16 nC/mm 0.26 nC/mm 2 2 2 2 Q 0.16nC/mm nC/mm nC/mm QGG 0.16 0.260.26 nC/mm From Table 5 one can notice that there is a slight increase in the gate charge of the STI plus From Table 5 one can notice that there is a slight increase in the gate charge of the STI plus floating P device can be attributed to the wider surfaceinarea of thecharge oxideof inthe contact withfloating silicon From Table which 5which one can that there a slight theofgate STI with plus floating P device cannotice be attributed to is the widerincrease surface area the oxide in contact silicon attracting a higher total number of charges. Despite this slight increase in Q G , the on-state resistance P device which cantotal be attributed tocharges. the widerDespite surfacethis areaslight of theincrease oxide inincontact with siliconresistance attracting attracting a higher number of QG, the on-state was reduced by a significant amount. The increase in QG is due to the larger MOS capacitor plate a higher total number of charges. Despite this slight increase in Q , the on-state resistance was reduced was reduced by a significant amount. The increase in QG is dueG to the larger MOS capacitor plate area at the gate terminal caused by the addition of the STI region. The reduction in R DS(on) stems by aat significant increase in addition QG is dueoftothe theSTI larger MOSThe capacitor plateinarea at the gate area the gate amount. terminal The caused by the region. reduction RDS(on) stems primarilycaused from the decrease of the depth ofregion. the p-type layer, as some of it is occupied by STI, leading terminal by the addition of the STI The reduction in R stems primarily from the primarily from the decrease of the depth of the p-type layer, as -some ofDS(on) it is occupied by STI, leading to a thinner space charge region to layer, be formed in the inisthe N buffer layer, which is in contact with decrease of the depth of the p-type as some of it occupied by STI, leading to a thinner space to a thinner space charge region to be formed in the in the N- buffer layer, which is in contact with the P layer. Since the bufferinlayer is the lowly- doped, any changes the P layer dimensions would lead charge region to be theisin bufferany layer, which in isinin the P layer. Since the the P layer. Since theformed buffer layer lowlyNdoped, changes thecontact P layerwith dimensions would lead to sizable variation in the depletion width. The smaller space charge region causes a reduction in the buffer layer is lowly doped, any changes in the P layer dimensions would lead to sizable variation to sizable variation in the depletion width. The smaller space charge region causes a reduction in thein device sheet resistance which leads to the lower on-state resistance. device sheet resistance which leads to the lower on-state resistance.
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the Electronics depletion width. The smaller space charge region causes a reduction in the device sheet resistance 2018, 7, x 8 of 10 Electronics 2018, 7, x 8 of 10 which leads to the lower on-state resistance. The performance ofthe thedevice devicewas was optimized optimized by by adjusting the size and placement of the the oxide TheThe performance ofof byadjusting adjusting the size and placement of oxide the oxide performance the device was optimized the size and placement of STI region. Figure 8 plots the performance of the device when the STI is staggered by shifting ititto to STISTI region. Figure 8 plots the performance of the device when the STI is staggered by shifting to the region. Figure 8 plots the performance of the device when the STI is staggered by shifting it the left. An STI width of around 0.25 µm was the optimal design point giving the desired 30 V left.the Anleft. STI An width of around 0.25 µm was the optimal design point giving the desired 30 V breakdown STI width of around 0.25 µm was the optimal design point giving the desired 30 V breakdown and theisR Requal DS(on) value is equal to 22.8 mΩ-mm22the Reducing thefrom STI width width from 0.25 µm to to 2 . Reducing the DS(on) value is equal to 22.8 mΩ-mm .. Reducing the STI from µm andbreakdown the RDS(on)and value to 22.8 mΩ-mm STI width 0.25 µm to0.25 smaller values smaller values will increase the on-resistance and decrease the off-state breakdown voltage, as values will increase the decrease the off-state breakdown voltage, as willsmaller increase the on-resistance andon-resistance decrease theand off-state breakdown voltage, as shown in Figure 8. shown in in Figure Figure 8. 8. For For example, example, when when the the STI STI width width is is reduced reduced from from 0.25 0.25 µm µm to to 0.125 0.125 µm, µm, the the R RDS(on) DS(on) shown For example, when the STI width 2is reduced from 0.25 µm to 0.125 µm, the RDS(on) increases from increases from from 23 23 to 23.3 23.3 mΩ-mm mΩ-mm2 and and the the breakdown breakdown voltage voltage decreases from from 30 to to 29 29 V. V. On On the the 2 and increases to 23 to 23.3 mΩ-mm the breakdown voltage decreases fromdecreases 30 to 29 V. On30 the other hand, when other hand, when the STI width is increased from 0.25 µm to 0.375 µm, the R DS(on) decreases to 22.7 hand, is when the STIfrom width0.25 is increased fromµm, 0.25 the µm R to 0.375decreases µm, the Rto DS(on) decreases to 222.7 the other STI width increased µm to 0.375 22.7 mΩ-mm but mΩ-mm22 but but the the breakdown breakdown voltage voltage decreases decreases 29 29 V. V. Figure Figure 99DS(on) plots the the performance performance when when the the STI STI is is the mΩ-mm plots breakdown decreases V. Figureof9the plots the performance whenthe theoptimal STI is centered respect centered voltage with respect respect to the the29 mid-point P type type layer. In In this this case, case, width for forwith the STI STI centered with to mid-point of the P layer. the optimal width the to the mid-point of the P type layer. In this case, the optimal width for the STI centered with respect centered with with respect respect to to floating floating P P type type region region is is around around 0.28 0.28 µm. µm. Similarly, Similarly, reducing reducing the the STI STI width width centered to floating P type region is around 0.28 µm. Similarly, reducing the STI width from 0.28 µm to smaller from 0.28 µm to smaller values will increase the on-resistance and decrease the breakdown voltage from 0.28 µm to smaller values will increase the on-resistance and decrease the breakdown voltage (seewill Figure 9). When When the STI STI width width is is decreased from 0.28 µm to to 0.125 0.125 µm, (see the R RFigure DS(on) increases from values increase the the on-resistance and decrease the 0.28 breakdown voltage 9). When the STI (see Figure 9). decreased from µm µm, the DS(on) increases from 2 and the breakdown voltage drops to about 29 V. On the other hand, when 2 and 22.8 to 23.3 mΩ-mm the width is decreased from 0.28 µm to 0.125 µm, the R increases from 22.8 to 23.3 mΩ-mm 2 DS(on)to about 29 V. On the other hand, when the the 22.8 to 23.3 mΩ-mm and the breakdown voltage drops STI width is increased from 0.28 µm to 0.375 µm, the R R DS(on) decreases to 22.5 22.5 mΩ-mm22from but the the µm breakdown voltage drops tofrom about 29 µm V. On other when the STI width is increased 0.28 STI width is increased 0.28 to the 0.375 µm,hand, the DS(on) decreases to mΩ-mm but breakdown voltage decreases 29 V as well. 2 to 0.375 µm, the RDS(on) decreases mΩ-mm but the breakdown voltage decreases 29 V as well. breakdown voltage decreases 29 to V 22.5 as well.
Figure8.8. 8.STI STIstaggered staggered with with respect totofloating floating P type type region. Figure withrespect respectto floating P type region. Figure STI staggered P region.
Figure 9. 9. STI STI centered centered with with respect respect to to floating floating P P type type region. region. Figure
Figure 9. STI centered with respect to floating P type region.
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From Figures 8 and 9 one can see that that the staggered STI achieves an overall better performance as far as the on-state resistance is concerned. Also, the staggered STI achieves a lower QG compared to the centered STI. This is due to the smaller surface area of the oxide under the gate field plate. 5. Conclusions This work investigates the super-junction LDMOS figure of merit (RDS(on) × QG ) for the 30 V application. The Sentaurus TCAD device simulation results indicate that the super-junction technique may not be suitable for low-voltage applications due to limited performance improvement in specific on-state resistance versus breakdown voltage. The process difficulties faced with creating long pillars for small feature sizes and charge balancing between the P and N pillars when the super-junction device is fabricated are added unfavorable factors for low-voltage super-junction device applications. A replacement for the super-junction technique is suggested by removing the super-junction pillars and shallow trench isolation region and adding a floating p-type layer. This technique shows improvement in the device performance upon optimization. A process simulation for the device was developed; this process demonstrated the feasibility and replicability of using this technique in real application. Lastly a new technique of surrounding the shallow trench isolation region with a P type layer is introduced which to our understanding is a new design to achieve a low figure of merit. The figure of merit (RDS(on) × QG ) improved, going from 9.75 mΩ-nC down to 5.93 mΩ-nC for the floating P device. Author Contributions: Aiman Salih performed the device design and simulation as well as wrote the manuscript. Jiann-Shiun Yuan provided suggestion for simulation and revised the manuscript. Both of them proofread the final manuscript. Funding: This research was supported in part by the National Science Foundation for the Industry/University Cooperative Research Center on Multi-Functional Integrated System Technology (MIST), grant# IIP-1439680 and IIP-143964. Acknowledgments: The authors would like to thank Dr. Patrick Shea at Renesas Electronic Corporation for discussions. Conflicts of Interest: The authors declare no conflicts of interest.
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