Embedded True Random Number Generator in Actel FPGAs 1 ˇ Martin Simka , Miloˇs Drutarovsk´y1 , Viktor Fischer2 1
2
Department of Electronics and Multimedia Communications, Technical University of Koˇsice, Park Komensk´eho 13, 04120 Koˇsice, Slovak Republic {Martin.Simka,Milos.Drutarovsky}@tuke.sk Laboratoire Traitement du Signal et Instrumentation, Unit´e Mixte de Recherche CNRS 5516, Universit´e Jean Monnet, 10, rue Barrouin, 42000 Saint-Etienne, France
[email protected] Abstract In high level security systems the unpredictability and unrepeatability of a random sequence is ensured by its generation in a true random number generator (TRNG) based on a physical phenomenon. Although the method based on randomness extraction from tracking jitter of phase-locked loop (PLL) is universal and applicable in wide scale of FPGAs or other digital circuits with analog PLLs, only implementations in Altera FPGAs were presented so far. This paper summarizes possible TRNG configurations and relation between PLL and TRNG parameters. Next, we analyze the possibility to implement presented class of TRNGs in Actel FPGAs and we provide the step-by-step instructions for the design of the TRNG in the selected family. The Actel FPGAs are shown to be a suitable target platform for the discussed type of TRNG.
Keywords: random number generator, phase-locked loop, cryptography, field programmable gate array. I. I NTRODUCTION Several cryptographic algorithms and protocols expect as their input some random values that are used as session keys, initial vectors, padding values etc. The security of cryptographic systems lies in a level of randomness of the input variables. In the high level security systems the unpredictability and unrepeatability of the random sequence is ensured by its generation in a true random number generator (TRNG) based on a physical phenomenon. Hence, there is a need for reliable, well-understandable and generally applicable method for implementation of the TRNG. In the case of digital circuits and nowadays very popular reconfigurable field-programmable gate arrays (FPGAs), the situation is even more difficult, what is caused by very limited sources of randomness suitable for a reliable TRNG implementation. One of the methods that could fulfil the mentioned conditions for TRNG implementation was proposed in [1] by the co-authors of this paper. Although the method is universal and applicable in wide scale of FPGAs or other digital circuits in general, featuring analog phase-locked loops (PLLs), only implementations in Altera FPGAs were presented so far. In this paper we summarize possible TRNG configurations and relation between PLL and TRNG parameters. We analyze the possibility to implement the TRNG based on the proposed
method in Actel FPGAs and provide the step-by-step instructions for the design of the TRNG in the selected family. The rest of the paper is organized as follows: Section II summarizes the basics needed to understand the method and analyzes possible configurations and parameters of the TRNG. Section III provides a description of the clock generators in Actel FPGAs. Section IV gives an analysis of the TRNG implementation in Actel FPGAs. Finally, in the last section we make some conclusions and suggestions for a future work. II. TRNG WITH RATIONALLY RELATED CLOCKING SIGNALS The method for generation of truly random values based on extraction of the random tracking jitter using two rationally related clocking signals was firstly published in [1]. The method is applicable in digital circuits containing a clock circuitry able to generate clocking signals with frequencies related in a certain ratio. Modern FPGAs include PLLs with a relatively wide range (depending on the family) of the synthesized frequencies. Following our experience with the TRNG implementation in Altera devices, we believe that Actel FPGAs are suitable for proposed PLL-based TRNGs, too. Below we provide some basic background of the method needed for an analysis of the possible TRNG configurations presented later. Let us have two clock signals CLK and CLJ with frequencies in the given ratio: FCLJ KM = , FCLK KD
(1)
where KM and KD are multiplication and division factors, which can be composed of the internal PLL dividers depending on the TRNG configuration. During one period TQ defined as: TQ = KD TCLK = KM TCLJ (2) the input clock signal CLJ is sampled KD times by another clock signal CLK . The output signal is periodic1 with the period TQ as long as the condition GCD(KM , KD ) = 1
(3)
is fulfilled, i.e. KM and KD are relative prime. The worst-case distance between the two closest edges of CLK and CLJ during the period TQ is given as [1] MAX(∆Tmin ) =
TCLK GCD(2KM , KD ) . 4KM
(4)
The basic principle of the true random number generation by an extraction of the tracking jitter included in clock signal CLJ using clock signal CLK is illustrated on Fig. 1. Advantage of the method lies in the fact that the jitter includes a random part, which is always present in the clock signal and cannot be removed by environment changes or any other intentional or unintentional interventions. Then the objective of a designer is to set the frequencies of the clock signals in a way, that it would be possible to sample the random part of the tracking 1 In case of the signals not influenced by a jitter the output signal of the sampling gate is periodic, if a jitter is present the subsequent periods are not identical, but differ only in some random samples and constant samples form major part of the periodic waveform.
TQ
TQ KM
CLJ
samples KD
CLK OUT DT critical samples
Fig. 1. Sampling the tracking jitter included in CLJ clock signal on raising edge of the CLK signal (illustrated for KM = 5 and KD = 7)
jitter. This means, that the sampling and sampled edges of the clock signals are kept in a distance comparable to the random jitter width. The samples taken from the areas influenced by the jitter (around the edges, called also as the critical samples) contain an entropy and can by used for generation of the random numbers, while the other samples have a constant logical value and do not contain any useful information. There are three options how the PLLs can be configured in the TRNG in dependency on chosen FPGA: with one PLL, with two parallel PLLs and with two (or more) cascaded PLLs (see Fig. 2). If KM and KD are chosen so that MAX(∆Tmin ) < σjit
(5)
we can guarantee that during the period TQ the sampling edge of CLK will fall at least once into edge zone of CLJ (where the edge zone means the time interval around the edge with a width smaller than σjit and σjit is a standard deviation of the jitter). The output signal OU T from the sampling gate is further processed in XOR decimator as it was explained in [1]. In some cases, especially in low-cost FPGAs, only one PLL is available for the TRNG (see Fig. 2a) ) and the other (if available) are used for the rest of the system. If there are no or only some acceptable restrictions2 for the input clock frequency of the logic part out of the TRNG, then one or more PLLs can be shared by the TRNG and the user logic. In most cases the use of two PLLs is largely sufficient to fulfil the condition (5). Usually, the option with two parallel PLLs is used (see Fig. 2b) ). In cases when the range of PLL divisors is not satisfactory (again, this is the case of the low-cost FPGAs e.g. in the paper discussed Actel ProASICplus FPGAs), a cascade of two (or more, if available) PLLs can be applied (see Fig. 2c) ). Each configuration permits to achieve different characteristics (defined in [5]) depending on parameters of PLLs, namely maximum input, output and voltage-controlled oscillator (VCO) frequency, multiplication and division factors, etc. and in this way the needed frequency can be synthesized. The parameters of the considered three generator configurations 2
By acceptable we mean the requirements for the clocking frequency, which are in a certain range that is suitable also for the TRNG to achieve the working condition (5).
CLJ
PLL
a)
CLI
D
Q OUT
CLK CLJ
PLL1 CLI
D
b)
OUT PLL2
PLL1
c)
Q
CLK
CLJ
PLL2
CLI
D
Q OUT
CLK
Fig. 2.
Configurations of TRNG with: a) one PLL, b) two parallel PLLs and c) two cascaded PLLs TABLE I PARAMETERS SETTINGS FOR DIFFERENT TRNG CONFIGURATIONS configuration / parameter
one PLL
FCLK
FCLI
FCLJ
MCLJ DCLJ
FCLI
two parallel PLLs MCLK DCLK
FCLI
MCLJ DCLJ
FCLI
two cascaded PLLs FCLI MCLJ1 MCLJ2 DCLJ1 DCLJ2
FCLI
KM
MCLJ
MCLJ DCLK
MCLJ1 MCLJ2
KD
DCLJ
DCLJ MCLK
DCLJ1 DCLJ2
S
1
1
4MCLJ
4MCLK MCLJ
1 4MCLJ1 MCLJ2
FCLI DCLJ
FCLI DCLK DCLJ
FCLI DCLJ1 DCLJ2
R
are summarized in Tab. I. The TRNG parameters, which can be obtained for the proposed configurations in Actel FPGAs are presented in the following section. The sampler sensitivity on the jitter S = FCLI MAX(∆Tmin )
(6)
is derived from (4). Decreasing MAX(∆Tmin ) for a fixed FCLI requires maximization of multiplying coefficients (M ). For the output bit-rate R = 1/TQ , which can be derived from (2), it holds that the increasing R for a fixed FCLI requires minimization of dividing coefficients (D). Of course, optimization cannot be done independently. There are system
TABLE II C LOCK C IRCUITS IN ACTEL FPGA S family
# of PLLs
output frequency
dividers range
max. output period jitter
ProASIC3(E)
1 (6)
0.75-350MHz
NA
180ps for fout = 24MHz 90ps for fout = 100MHz 70ps for fout = 350MHz
ProASICplus
2
m fin n×post−scale
m = 1-64 n = 1-32 post − scale= 1-4
±1% for fout < 10MHz ±2% for 10MHz < fout < 60MHz ±1% for fout > 60MHz
Axcelerator
8
fin m n
m =1-64 n = 1-64
long-term: 1% of fout or 100ps short-term: 50ps +1% of fout
limits expressed by the condition R = 4FCLK FCLJ . MAX(∆Tmin )
(7)
We can conclude, that the use of two PLLs in either parallel or serial (cascaded) configuration can increase significantly sensitivity on the jitter and the output bit-rate of the generator, depending on the available range of multiplication or division factors or both. In the equations presented in Tab. I it is shown from which PLL coefficients (dividers) the factors KM and KD are composed. The factor KM has a direct influence on the value of MAX(∆Tmin ) (see Eq. 4). While for the configurations with one PLL or several cascaded PLLs KM is composed only from multiplying coefficients, in case of the parallel configuration the dividing coefficient is included. This should be considered especially in cases when not all the PLL coefficients have identical range. III. C LOCK GENERATOR CIRCUITRY IN ACTEL FPGA S In this part we analyze properties of clock generators and clock conditioning circuits embedded in Actel FPGAs. With permanent increase of variability of systems implemented on FPGAs, designers have different requirements on clock circuits integrated inside FPGAs. Applications from communication or signal processing area demand multiple flexible and low-jitter clock sources. In complex system-on-chip applications, in- and output data signals come from several sources outside the chip, therefore precise skew compensation is needed. The clock conditioning circuits included in FPGAs usually enable to perform following functions (in dependency on FPGA vendor and family): clock phase adjustment, clock delay minimization, clock frequency synthesis, spread-spectrum clock modulation, static or dynamic configuration of circuits parameters, etc. A core of clock circuitry embedded in Actel FPGAs forms a PLL circuit surrounded by several delay lines, clock multipliers/dividers, and circuits for interconnections between internal clock network and external pads. Number and functionality of PLLs depends on chosen FPGA family. Table II presents basic parameters of the PLLs and clock circuits for flash based FPGA devices from Actel (Axcelerator [2], ProASICplus [3], ProASIC3(E) [4]).
IV. A NALYSIS OF TRNG IMPLEMENTATION IN ACTEL FPGA S In this section we explain how the parameters of the clock circuitry influence the parameters of the presented TRNG. Analysis should answer if the Actel FPGAs are suitable for the discussed randomness extraction method and what parameters of the TRNG are achievable. As a target family for TRNG implementation the ProASICplus was chosen. This low-cost FPGA family based on flash technology offers two well-configurable PLLs on a chip. We selected an evaluation board [6] provided with ProASICplus APA300-PQFP208 device [3] for experiments and measurements. We used an on-board oscillator with frequency 40MHz as a reference input clock source. The board has separated power supply for the PLLs and for the rest of the chip what enables to analyse the impact of power supply violations (from off-chip manipulations, or from activity of the on-chip logic by interconnection of the power supplies) on the generated sequences. There are two on-chip PLLs available for the frequency synthesis in the chosen ProASICplus device. There exists following limitations for the frequencies of signals connected to PLL circuits: fin = 1.5 − 240MHz, fout = 6 − 180MHz and fVCO = 24 − 180MHz. As it was already mentioned in Table II the PLL output frequency of the PLL fout is derived from the input frequency fin by application of the dividers: fout = fin
m fVCO = n×p p
(8)
where p states for post-scale divider and fVCO is the output frequency of the VCO. To compare the discussed configurations and find out the ranges of TRNG parameters one can follow in the next way. The frequency ranges of the two rationally related clocking signals are given by the frequency ranges of the PLL dividers and the input frequency (using equations from Tab. I). From the ratio of the frequencies it is possible to set the parameters KM and KD and then also check the basic condition that has to be fulfilled for the functionality of the TRNG following (5). The size of the jitter σjit can either be measured on the target device (if needed equipment is available), or just estimated (considering the ranges given in vendor’s documentation) and then specified after experiments with generator’s settings. Knowing the frequencies of the clocking signals and parameters KM and KD it is easy to find the period TQ (2) and then the output bit-rate R = 1/TQ . To give an overview on what ranges of MAX(∆Tmin ) are achievable in different PLL configurations we summarize them in Table III, setting the input frequency of the PLLs to FCLI = 40MHz. One should note that the intervals are only theoretically achievable or could be slightly different in practical cases, since some limitations were not taken into account (e.g. the limited output and input frequency for cascaded configuration, limited number of combinations of dividers etc.) and for simplification we assume that the condition (3) is always satisfied. From Tab. III one can see that the smallest values of MAX(∆Tmin ) can be reached with the cascaded configuration. While the frequencies range is the same as for the other configurations, the number of combinations of frequency dividers is higher what offers better possibilities for matching the FCLJ frequency to the fixed FCLK . As expected, the lowest sensitivity is achievable by using only one PLL. On the other side, if the size of the jitter is large enough, this configuration is the most effective in area consumption. In addition, the sensitivity can
TABLE III ACHIEVABLE SENSITIVITY ON JITTER USING TWO CLOCK SIGNALS IN ACTEL P ROASIC PLUS (FCLI = 40MH Z ) configuration
MAX(∆Tmin )
two PLLs one PLL two cascaded PLLs
0.17ps - 41ns 10.85ps - 41ns 0.084ps - 41ns
be increased by application of the delay line [1]. In practical cases the configuration with one PLL is not usable, as the number of random samples and their entropy is low because of the low sensitivity S . As a solution one can add the second PLL in parallel or cascaded configuration. It was already mentioned, that the parallel configuration has a disadvantage in controlling two clock signals instead of one as it is in case of the cascaded configuration. On the other hand, a disadvantage of the cascaded configuration could be the fact that the tracking jitter is composed of components produced in the all PLLs in the cascade. Hence, the parameters of the jitter vary for different settings of PLLs. Achievable sensitivity is in the worst case comparable, in other cases much higher than is the size of jitter (usually around 10-100ps) therefore we can conclude that the proposed method is feasible to implement and is suitable for Actel FPGAs. Also our first experimental results (not published yet) confirmed the expectations. While the configuration with one PLL does not provide generated sequences with required parameters, the configurations with two PLLs generate the random values passing the standardized sets of statistical tests (e.g. NIST tests). V. C ONCLUSIONS We summarized the required theory needed for basic understanding and design of the TRNG based on the randomness extraction method with two rationally related clocking signals. The description of the clock generating circuitry in Actel FPGAs provided the overview of the parameters that should be taken into account by implementation of the TRNG using this method. We also explained the way how the basic parameters of the TRNG can be computed and what the relation between them and target device parameters is. Following the presented results it should be possible to implement the TRNG with required parameters. The analysis of the three basic configurations of the TRNG makes possible to choose the one that is the most suitable for a certain application, taking into account the available number of PLLs, possible ways of their interconnections, requirements for other clock signals and their frequencies, output bit-rate, quality of the generated sequence and above all the jitter size. We can conclude that the Actel FPGAs are suitable for implementation of the TRNG based on discussed method, and achieved parameters are comparable with the ones from Altera FPGAs. As a next step the experimental verification of all the presented results should follow.
R EFERENCES [1] V. Fischer and M. Drutarovsk´y, “True Random Number Generator Embedded in Reconfigurable Hardware,” in Cryptographic Hardware and Embedded Systems, 4th International Workshop – CHES 2002 (B. Kaliski, C. Koc, and C. Paar, eds.), vol. 2523 of Lecture Notes in Computer Science, (Redwood Shores, California, USA), pp. 415–430, Springer-Verlag, Aug. 13–15, 2002. [2] Actel Corporation, Axcelerator Family PLL and Clock Management, Application Note, June 2003. [3] Actel Corporation, Using ProASICplus Clock Conditioning Circuits, Application Note, Dec. 2004. [4] Actel Corporation, ProASIC3(E) Flash Family FPGAs, Datasheet, Jan. 2005. ˇ [5] V. Fischer, M. Drutarovsk´y, M. Simka, and N. Bochard, “High Performance True Random Number Generator in Altera Stratix FPLDs,” in Field-Programmable Logic and Applications – FPL 2004 (J. Becker, M. Platzner, and S. Vernalde, eds.), vol. 3203 of Lecture Notes in Computer Science, (Lueven, Belgium), pp. 555–564, Springer-Verlag, Aug. 2004. [6] Actel Corporation, ProASICplus Evalueation Board, User’s guide, 2002.
