Energy Efficient Implementation, Power Aware ...

Energy Efficient Implementation, Power Aware Simulation and Verification of 16-bit ALU using Unified Power Format Standards Roopa R. Kulkarni

S. Y.Kulkarni

Department of Electronics and Communication Engg., Gogte Institute of Technology, Belgaum, Karnataka, India [email protected]

Department of Electronics and Communication Engg., M. S. Ramaiah Institute of Technology, Bangalore, Karnataka, India [email protected]

Abstract—With the increase in the demand for high performance and high speed VLSI systems such as network processors in networking or SOCs in communication and computing has shifted the focus from traditional performance parameters towards the analysis of power consumption. The power budget and management among the domains of a system is of real concern. Hence, the power aware design using clock gating, power gating, dynamic voltage scaling and frequency scaling are the most used design techniques. Employing such low power techniques at the RTL creates new design and verification challenges. The challenges are: how can one domain be power downed, how can it be put back to power up state and do they retain or restore the previously computed data and still function correctly. These can be answered and implemented using new methods of implementation and verification using the unified power format (UPF)standards for low power intent designs.

In equation (1): α is the switching activity, c the capacitance, v the supply voltage and f the frequency of operation. From the relation it is observed that the dynamic power is proportional to the frequency and the switching activity. Several power management or energy efficient techniques are: clock gating, power gating, frequency scaling, dynamic voltage scaling or using of a sleep transistor to turn ON and OFF the elements in the design.

This paper presents the work carried out in applying the metioned techniques to the 16-bit ALU functional blocks.The paper discusses the power aware verification flow, power intent using UPF and managing the power among the domains or the functional blocks in a low power design. The implementation of this advanced RTL simulation and verification technique is carried out using QuestaSim Power Aware Verification tool. Simulation results efficiently prove the validation of the applied UPF standards in designing the 16-bit ALU . Keywords-RTL Verification, Power Aware, UFP standards, Isolation, Retention, Power Dissipation, Leakage Power.

I.

INTRODUCTION

The main sources of power dissipation are: static power and dynamic power. Static Power dissipation is due to the leakage current that flows through the transistors when in the OFF state. Dynamic power is also the switching power which is associated with the switching activity. Dynamic power is defined as Pdynamic = α * c * v2f

(1)

Most of the power management techniques use a SLEEP mode method, wherein portion of the system that is inactive is put in the OFF state. This is advantageous as the leakage current of the domain in the SLEEP state is nullified and the power consumption is reduced. This can be achieved by isolating such domains from the power supply, clock or the inputs. However, this technique results in the loss of the state in the domains when switched OFF. To overcome this, an additional circuitry is needed which retains the data when in OFF state and restores, when put to ON state. In implementing these techniques power states are used to match the performance and availability requirements against power objectives. These objectives, in turn, determine when power gating is used to shut down or bring up a power domain based on when its functionality is needed. Today's network processors (NP) need to support heavy traffic without degrading the performance. This is achieved by the NPs which are designed for parallel processing using parallel processor architectures called processing elements. These processing elements (PE) are also called as the microengines. The study of such NPs show that the power consumed by the PEs is more compared to the other elements: register unit and next neighbor register. The PE constitutes an ALU which performs the basic operations such as arithmetic and logical operations, rotate and shift operation , integer multiplication along with the processing of the packets. This parallelism technique motivates the use of power gating technique as there are more than one PE in the NPs, which are not operating simultaneously. Such PEs can be put to SLEEP mode which implies power is put OFF to that PE.

This paper aims at applying these techniques to a 16-bit ALU. The advanced RTL verification method of coding and simulating using UPF is explored and justified. Section II briefs on the review of the techniques and the related work carried out. In section III, the description of unified power format standards is dealt. The implementation of a 16-bit ALU using the UPF is discussed in section IV. Results of the implementation is discussed in section V. The concluding remarks and future scope of the technique is discussed in section VI. II.

RELATED WORK

Literature survey carried out in this paper aims at understanding the concepts of UPF standards and their usage in verification of SOC at much earlier stage of the design. Hence, all the papers referred describe the UPF standards, coding, implementing and verifying at the simulation which leads to the optimal design of power aware intent SOCs. In reference [1], power aware design is introduced at earlier stage of SOCs. This helps in power reduction which lowers design complexity and verification. In [2], the authors provide the detailed and comprehensive approach to power aware verification using UPF standard. The various power management design techniques, specification of power state tables, signal isolation, state retention are all dealt in detail. This paper also provides information on implementing the power aware technique to a chip and simulation results are obtained. Power dissipation contains two components: dynamic as well as static. Dynamic power is proportional to the square of supply voltage and leakage power is proportional to it. The tutorial in [3], explains the influence of voltage on the power management techniques. The tutorial also describes the technique that influences simulation and formal verification. The author in [4] proposes a novel approach to verify battery lifetime which is made of 3 parts. Firstly, semifunctional use cases, secondly specification used to automatically drive the test cases and finally the fast simulation and power estimation to meet the design requirement. In this section of related work, the author has discussed the implementation of various power management technique, but with millions of gates on a SOC, these techniques can be applied with the modification of the RTL [5] code that defines the functional impacts of power gating, retention and isolation be verified at the earlier stage of design process. Most of the design are disconnected i.e.,the high level architecture power management which inturn control or relates the lower level power domains are not related. To bridge this gap, the influence of low-level power domain assertions to the architecture power intent is proposed in [7]. Using the UPF extracted assertion the inter-domain properties can be formally verified globally. The author in [9] describes the need for power management technique which puts OFF some portion of the design to SLEEP mode. The paper explains power gating, multi-voltage and UPF, about static verification technique such as detecting missing level shifters, incorrect level shifter, formal verification technique using UPF specific assertion and sequence based assertion. All these are applied at the RTL as power intent is

visible from the UPF. Finally, the introduction of new verification methods from the industrial point of view in [12] explains the verification landscape which provides large metrics, simulation method and formal methods. The author explains the challenges that are faced when introducing the new verification techniques from technical as well as developers point of view. III.

UNIFIED POWER FORMAT STANDARDS

UPF provides the ability for electronic systems [8] to be designed with power as a key consideration early in the process. It accomplishes this through the ability to allow the specification of implementation-relevant power information early in the design process — RTL (register transfer level) or earlier. The need for the UPF is due to: HDLs which do not adequately support the specification of power distribution and management, and vendor-specific formats are non-portable and create opportunities for bugs via inconsistent specifications. A. Supply Net Designing electronics to meet low power [8] design constraints requires the specification of a power supply network that can control the distribution of that supply to minimize energy consumption. UPF supports the specification of the power supply distribution network so the supply network can be automatically implemented at a relatively abstract level. The supply network consists of supply ports, switches, and supply nets. Supply network objects are defined within the context of a power domain. Supply ports provide the supply interface to power domains and switches. Switches control the supply distribution. Supply nets connect supply ports. The commands used are: • create_power_domain domain_name[-elements list] [-include_scope] [-scope instance_name] • create_supply_port port_name -domain domain_name[-direction ] • create_supply_net net_name -domain domain_name [-reuse] [-resolve < unresolved | one_hot | parallel >] • create_power_switch switch_name -domain domain_name -output_supply_port { port_name supply_net_name } {-input_supply_port { port_name supply_net_name }}* {-control_port { port_name net_name }}* {-on_state {state_name input_supply_port {boolean_function}}}* [-off_state { state_name {boolean_function} }]* The create_supply_net command creates a supply net. If domain is not specified, the supply net is created in the current scope, and the supply net is available for use by tools to power cells in any domain created. B. Isolation Strategies Isolation strategies means adding the isolation cells either at the input, output or both so that a particular design is isolated from the rest of the design. Isolation cells are logic gates that determine the values of a power domain’s input or output port when the domain is powered down [11].

Isolation cells are necessary because each power domain represents a design area comprised of particular features, and each feature corresponds to an area of physical silicon. Even though they may represent different power domains that can be independently powered ON and OFF, these areas of silicon remain physically connected; therefore, when one domain is turned OFF, it is still connected electrically to other domains. • set_isolation ISO_Proc -domain - applies_to - clamp_value isolation_signal - isolation_sense C. Retention Stratergies To maintain the state of registers and latches during SLEEP mode, retention elements are employed that can retain their data when in SLEEP mode [11]. The register value is restored after power up if the value was saved successfully before power down and the restore protocol executed successfully. Otherwise, the register value remains unknown until it is set, reset, or a new value latched into it. These elements will behave as normal memory elements when the power is switched ON and the power control signals are not asserted. The command used : • set_retention -domain save_signal {Name} -restore_signal {Name}

IV.

IMPLEMENTATION OF 16BIT ALU

In this paper, a 16-bit ALU is implemented to understand the power aware simulation and verification using unified power format. From the survey and study of [1]-[3] the ALU is implemented. The ALU designed consists of two blocks namely the arithmetic and logical block. The arithmetic block performs the arithmetic operations namely addition, subtraction, division, multiplication, increment and decrement using select signal sel[2:0]. The logical block performs the logical operations namely: AND, OR, XOR, XNOR, complement and shift using the select signal selL[3:0]. The isolation cells are added at the inputs. When the isolation cell ISO1 is put to ON state the inputs will not be provided to the arithmetic block and hence no output. Or in other words the arithmetic block is put in power down mode. Similarly when ISO2 is ON, the logical block is put in power down mode, thus there is no output from the logical block. The ALU is designed using the power aware simulation and verification technique using the unified power format IEEE standard. The power domains are specified, supply nets are defined, control switches are added and finally the data retention is implemented so that the data is not lost when the domains are put to power ON from its OFF state. The block diagram is as shown in the figure 1.

alu sw ctl

logic sw ctl

alu sw

logic sw

VDD rail Ain

PD-Logic

PD-Arithm I

Logical

Arithmetic

Bin

I

Storage Cell R

Storage Cell R

Clock Sel[2:0]

VSS rail

SelL[2:0]

Power Domain TOP Figure1: Block diagram of a 16-bit ALU using concept of UPF

As seen from the block diagram shown in figure 1, there is a TOP power domain which consists of two power domains. The power domain defined for the arithmetic unit is PD-Arithm and for the logical unit is PD-Logic. Two switches namely: alu_sw and logic_sw are created which control the power entering the blocks. There are two control signals namely: alu_sw_ctl and logic_sw_ctl,when logic HIGH, the supply is provided to the respectively functional unit. The two 16-bit inputs are provided to the arithmetic and logical unit through the isolation cells I. As discussed in the previous sections, when any functional block is powered down, it is in SLEEP state, hence when powered ON it should regain its state. To do this the retention cells are added which restore the data of the functional unit when powered ON. Operation: The two 16-bit inputs are provided to the two functional units. The processing of data happens only when the functional units are in ON state or when powered up. The power to these units is controlled by the control switch provided to each. For example, when the control signal alu_sw_ctl is OFF then the power will not be provided to the arithmetic block and if the isolation is ON, then no input is provided, hence it is put into the OFF or SLEEP state. This implies, only the logical unit will process the data. The design is implement right from creation of the supply net, control switches, isolation cells and retention cells by coding using unified power format. The design is synthesized using the Precision Synthesis tool. The RTL Top view schematic of the ALU showing the arithmetic and logical block is as shown in the figure 2. V.

SIMULATION RESULTS

The design is implemented using Verilog HDL along with the unified power format and the user constrain file.

The ALU is simulated as two functional blocks namely arithmetic and logical block. Initially, the individual units are simulated. The simulation result of arithmetic functional unit is as shown in the figure 3. A 16-bit ALU is coded along with the unified power format and implemented to analyze the power aware design at the RTL. The UPF code consists of adding the control switches, defining the supply for the two functional blocks, assigning the retention register and the isolation cells. 'QuestaSim Power aware simulator is a power full tool which provides the power analyses and verification at the simulation level. The ALU designed is simulated using the QuestaSim simulator. The QuestaSim simulation flow for the power aware modeling accepts the normal HDL code along with the UPF defining the power parameters. The simulator identifies all the sequential elements inferred by the RTL design, overlays the design with power control network, adds the appropriate retention cell and dynamically modifies the behavior of the design to reflect the specified low power design intent in power down and up situation. The simulation results are as shown in the figure 4 and 5. The implementation of power aware simulation technique is initially applied to the arithmetic block. As seen from figure 4 the isolation cell ISO1 is ON, during which the previous state of the arithmetic operation that is alu_out is saved, then the control switch is on, the output is also restored during isolation. When the block is to be powered up, firstly the data is restored, the functional block is powered and then the isolation signal is removed. During this process though input is provided to both the units, only the logical operation is performed. This implies that the arithmetic block can be put into the SLEEP mode, hence the ISO1 is ON while ISO2 is OFF. This method of supplying the power only to the required function unit and isolating the others leads to power reduction.

Figure 2: RTL Schematic of ALU

Figure 3: Simulation of the arithmetic functional unit

Arithmetic control switch

Save Arithmetic output Restore Arithmetic output

Isolate Arithmetic input

. Figure 4: Arithmetic Block is isolated

Save Logical output Restore Logical output

Arithmetic output

Figure 5: Isolating the Logical block, output at the Arithmetic block

Isolate Logical input

The implementation of power aware design was also verified by applying the isolation to the logical unit and evaluating the arithmetic operation as shown in figure 5. From the simulation results shown in figure 5, when the power switch logic_sw_ctr is OFF the logical output data is saved using the retention cell. After the logical input data is isolated only the arithmetic block execute the inputs and the result is available at alu_out. In this process the ISO2 is ON, while the ISO1 is OFF. Now the design saves the logical output, and when the isolation is put to OFF state the output is restored. VI.

CONCLUSION AND FUTURE SCOPE

The motivation to implement this design was to apply the power aware simulation and verification to a 16-bit ALU. In this paper, the simulation power intent verification is efficiently implemented for an 16-bit ALU, consisting of two functional units namely: arithmetic and logical. The design and implementation of 16-bit ALU is carried out with the basics of reference [1]-[3]. From the simulation results, it can be proved that the unified power format coding technique at the simulation can lead to power reduction. The addition of supply nets, defining various power domains leads to power aware intent design. The retention cells and isolation cells ensure the retention of data isolation of power to the those modules which are SLEEP or OFF state. This power intent method can be implemented on SOCs or Network On Chip, where the device have more than one functional blocks and not all are functioning simultaneously. In this paper, the level shifters and power states have not been defined. The paper does not define the power states and voltage levels for each of the power domains. This could be done as a future scope in optimizing the simulation to obtain the optimal results. ACKNOWLEDGMENT The author would like to express gratitude to Mr. Raghava of Trident TechLabs, Bangalore for the technical support rendered in using the tool efficiently.

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