Evaluating the Effects of Branch Prediction Accuracy on the Performance of SMT Architectures Ronaldo Gonçalves 1, Maurício Pilla 2, Guilherme Pizzol 3, Tatiana Santos 4, Rafael Santos 5, Philippe Navaux 6 1
Departamento de Informática, Universidade Estadual de Maringá Avenida Colombo 5790, CEP 87020-900, Maringá, PR, Brazil {
[email protected]} 2,3,4,6 Instituto de Informática, Universidade Federal do Rio Grande do Sul Avenida Bento Gonçalves 9500, CEP 91501-970, Porto Alegre, RS, Brazil {pilla, gpizzol, tatiana,
[email protected]} 5 Departamento de Informatica, Universidade de Santa Cruz do Sul Av. Independencia 2293, CEP 96815-900, Santa Cruz do Sul, RS, Brazil {
[email protected]} Abstract Branch instruction occurrence reduces the parallelism exploited from the source code of singlethreaded applications. In order to reduce the branch penalty, several branch predictor techniques have been proposed. Branch predictors allow the fetch unit to continue fetching instructions along a predicted path after a conditional branch has been detected. Such techniques, when used in conventional superscalar architectures, may reach more than 95% of accuracy. These same techniques are also used in SMT architectures. However, SMT architectures may have a different behavior due to the parallelism exploration in several threads. Moreover, the effects supported by one thread may influence also the performance of other threads. In this work, we vary the accuracy of the branch predictor in order to evaluate the impact on the performance of a SMT architecture. Even though the SMT and superscalar have a different behavior, we observed that the effect of the improvement in the prediction accuracy is similar for both architectures.
1. Introduction With the increase in the complexity of applications, many researches have been done in order to design faster microprocessors. These architectures, which are currently being designed, use aggressive hardware techniques to 1
PhD student supported by CAPES PhD students supported by CNPq 3 Undergraduate student supported by CNPq 4 PhD student 6 PhD advisor at the II/UFRGS
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explore efficiently the instruction level parallelism (ILP) and also the application level parallelism (ALP). In this context, two approaches can be emphasized: the superscalar [22] and the SMT [23] architectures. Superscalar architectures are used in many state-of-art microprocessors, such as Pentium [2], PowerPC [4], MIPS R10000 [16] and UltraSparc [26]. These architectures have several functional units and they can explore directly by hardware the instruction level parallelism (ILP). SMT architectures (Simultaneous MultiThreaded) have a larger amount of hardware in order to store different executions context and so, they may also explore the application level parallelism, executing instructions from different threads. Unfortunately, this parallelism is limited by many reasons, such as control dependencies [12]. Branches disrupt the instruction flow reducing the chances of parallelization. Nevertheless, many successful branch prediction techniques were developed and used in superscalar architectures, providing high accuracy rates. Some sophisticated techniques can reach 98% of accuracy. In spite of these accuracy rates are very high accuracy rates, the occurrence of a few mispredicted branches make the processor to execute instructions along wrong paths, reducing the performance. Moreover, the performance may be affected by another 3 reasons. The first one, is the pollution in the L1 I-cache. When a fetch of a wrong path is performed, useful instructions may be replaced in the cache and cache misses may increase. The second reason is regarding the memory bus. Hence, while a wrong path miss is being processed, using the bus, another miss generated by the correct flow may be waiting to be served. Finally, the pipeline has to be flushed in each misprediction, turning out that some
processing already done become useless. Currently, these same techniques are used in SMT architectures, but there is not any study evaluating if their use achieves the same effectiveness and if mispredictions cause the same impact as in a superscalar architecture. Besides, SMT architectures may have a different behavior because the performance reached by one thread may influence the performance of other threads. Thus, an analysis relative to the branch prediction utilization in these architectures is addressed by this work. Also in this work we evaluate the effect of different branch predictor accuracies in the performance of a superscalar and a SMT architectures. Additionally, we want to find out if the behavior of SMT architectures is similar to the behavior of superscalar architecture. This work is organized as follow. Section II presents a review of previous works, approaching questions related to branch prediction and SMT architectures. Section III introduces the simulation environment, showing configurations, benchmarks and methodology used. Next, section IV explains the simulations and analyses the obtained results. Finally, in section V conclusions and future works are presented.
2. Related works The performance of modern processors is limited by two well-known instruction dependencies [10, 22]: data and control dependencies. Many techniques have been proposed to overcome this limit. The data dependency can be reduced by data prediction techniques [13], register renaming [16] and dynamic scheduling. Control dependencies can be reduced by branch prediction techniques, multi-path execution [1, 17, 19] and trace cache mechanism [18]. Regarding branch prediction, several techniques were proposed, achieving different levels of accuracy. Smith [21] analyzed several branch prediction techniques, and he found an average accuracy rate between 76.68% and 92.55%. Later, Yeh and Patt [28] proposed the adaptive two-level branch predictor, where the behavior of correlated branches can be captured and stored in two levels of tables. They reported accuracy of 97% in SPEC benchmarks, against 93% of others mechanisms. McFarling [15] developed a branch prediction mechanism which combined others mechanisms, achieving accuracy rates up to 98.1%. Young et al [29] analysed schemes for correlated branch prediction. Uht et al [25] presented an overview of branch prediction mechanisms that are used in some of the state-of-art microprocessors. Kesller [11] presented the complex prediction mechanism used in Alpha 21264, which is an example of how complex are the branch prediction mechanisms implemented in modern microprocessors. Due to exploiting instruction level parallelism from single-threaded applications, superscalar architectures
require efficient mechanisms to overcome branch penalties. The researches in this area have been trying to reach perfect prediction (100% accuracy) because 5% or less of misprediction is enough to harm the performance of superscalar architectures. As SMT architectures can extract parallelism also from different threads it is necessary to evaluate the impact of these branch predictors over the performance of such architectures. SMT [23] have been proposed to execute instructions from many threads simultaneously [9, 27, 23, 5]. These architectures are able to hide high latencies from some threads by scheduling instructions from other threads. Moreover, SMT architectures take advantage of idle resources, e.g., functional units. However, the cache system suffers because memory addressing conflicts among threads, generated by compiler [14]. Consequently, many works on SMT have addressed this question. Tullsen [24] showed that instruction fetch must favor threads with less instruction in the pipeline. Hily [8] showed that caches require high associativity to sustain many threads. Gonçalves [6] showed analytically that cache miss rate can be reduced if a prefetch scheme directed by process scheduling is used. Also in 1999, Sigmund [20] concluded that cache replacement policy is a fundamental issue when memory bandwidth is restricted.
3. Simulation environment The simulation environment used in this paper consists of two different simulators, both developed using the most detailed simulator from the SimpleScalar Tool Set [3], called sim-outorder. This simulator supports out-oforder issue and execution, based on the Register Update Unit (RUU). It also supports non-blocking caches and four types of branch predictors: two-level, perfect, bimodal, combined (bimodal and 2-level adaptive). Its pipeline is composed of six stages: fetch, dispatch, issue, execute, writeback and commit, as shown in Figure 1. Our first simulator is an extended sim-outorder which includes a mechanism that allows the user to determine the branch prediction accuracy. When a branch instruction is reached, the mechanism draws a random real number. If this number is smaller than the pre-determined accuracy, the predictor forces a correct prediction. In this case, if the target or the direction predicted is wrong, the predictor adjusts to the right values, otherwise it keeps the original prediction. On the other hand, if the random number is greater than the desired accuracy, the predictor forces a misprediction. In this way, if the target was correct, the predictor redirect the fetch to the wrong address, adding the correct penalty, otherwise it keeps the wrong prediction. It is important to note that his mechanism does not simulate wrong target addresses. The simulated misprediction is related only to the direction of the branch, taken or not-taken. Whenever the branch is
predicted correctly as taken, the correct branch target address is used. i-cache i-tlb fetch i-queue decode ruu-q
ls-q Register Update Unit issue
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instructions from different slots in a round-robin sequence limited by the architecture width. Eight benchmarks from SPEC 95 [SPE 95] were simulated, mixing integer (gcc, ijpeg, li, and perl) and floating-point applications (fpppp, mgrid, swim, and wave5). We simulated 4 different combinations of 4 benchmarks each one (2 integers and 2 floating-points) in order to compute the average performance for the SMT with 4 threads (SMT-4), and one combination for the SMT with 8 threads (SMT-8). All simulations are executed until one of the benchmarks in each workload complete 250 millions of instructions, from which 50 millions of initial instructions are skipped to reduce the warm-up stage. Table 1 shows reference latencies considered in our simulations. In our analysis we have measured the performance in IPC (Instructions per Cycle).
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Table 1 Reference latencies Types of latencies
Figure 1 Superscalar architecture Using the branch predictor described above, our second simulator [7] implements a SMT architecture, which is part of the SEMPRE project [5]. This simulator was developed through replication of all resources from sim-outorder simulator in order to maintain and execute many contexts, as shown in Figure 2. Note that for this architecture, each thread is an independent application, thus dependencies among threads are not considered. Also, all applications on that architecture were executed under the same branch prediction accuracy, what does not reflect the impact of multiple threads over the prediction accuracy. But this is out of the scope of this work. i-cache system smt-fetch i –queue system smt-decode
smt-issue shared fus
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Figure 2 SMT architecture The resource set containing register file, tables and queues, used to maintain the context of one thread is called slot. The Fetch stage fetches up to one instruction block per cycle or up to the first taken branch composed by instructions from only one thread at a time selected in a round-robin fashion. The remaining stages schedule
1 ; 6 ; 30 (18 + n*2) 1 2 1 Div oper Mult oper Sqrt oper Div oper Mult oper
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Table 2 Hardware configurations
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Superscalar
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w = 8, l2-c = 512k, l1-c = 32k, 10 fus = 3 IA, 3 FA, 2 LS, 1 IM, 1 FM, ruu = 32 e, lsq = 16 e. w = 16, l2-c = 1M, l1-c = 64k, 17 fus = 5 IA, 5 FA, 3 LS, 2 IM, 2 FM, ruu = 64 e, lsq = 32 e.
w = 16, l2-c = 1M, l1-c = 64k, 17 fus = 5 IA, 5 FA, 3 LS, 2 IM, 2 FM, ruu = 64 e, lsq = 32 e. w = 64, l2-c = 4M, l1-c = 256k, 68 fus = 20 IA, 20 FA, 12 LS, 8 IM, 8 FM, ruu = 256 e, lsq = 128 e.
w = 16, l2-c =1M, l1-c = 64k, 17 fus = 5 IA, 5 FA, 3 LS, 2 IM, 2 FM, ruu = 64 e, lsq = 32 e. w = 128, l2-c = 8M, l1-c = 512k, 136 fus = 40 IA, 40 FA, 24 LS, 16 IM, 16 FM, ruu = 512 e, lsq = 256 e.
The experiments are divided in six groups, using as criteria the simulated architecture (superscalar or SMT) and the number of allocated resources (small or large), as shown in Table 2. Also, we have simulated two different workloads for the SMT architectures 4 and 8 threads but we configured the resources accordingly. The small hardware represents state-of-art configurations based on various existent microprocessors. The large hardware
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Our interest is to analyze the application behavior on SMT architectures, changing the branch prediction accuracy and comparing with that obtained on superscalar architecture. Thus, our first simulations were made with the superscalar architecture. We varied the accuracy of the branch predictor and gathered the respective IPCs. Note that the predictor was specially designed to allow to get the desired accuracy independently of the scheme used. In fact, the simulator is based on perfect prediction, where always the correct outcome is available and, accordingly with the prediction accuracy required, some mispredictions are intentionally forced. Figures 3 and 4 show the number of instructions per cycle (IPC), for each benchmark, as a function of the branch prediction accuracy. In both small and large architectures the benchmarks presented a similar behavior, in spite of the better performance obtained by the larger architecture. The benchmarks mgrid and fpppp are not largely affected by branch prediction improvement, presenting almost constant performance. Although these benchmarks show increasing in performance from the small to the large architecture even for the lowest prediction accuracies. The benchmarks, ijpeg and li, have showed the significant improvements when the prediction accuracy is improved. That means, that these benchmarks are more sensitive to the branch prediction thus their performance is directly affected by the branch prediction accuracy. However, we can see that when hardware is increased, the benchmarks mgrid and fpppp do not rely on the branch prediction itself thus they take full advantage of the available resources. ijpeg and li need a more efficient predictor to overcome the performance achieved by the benchmarks mgrid and fpppp. In the small superscalar architecture, the benchmark ijpeg overcomes mgrid when the accuracy is about 75%, and the benchmark li overcomes fpppp when the accuracy is close to 55%. In the large superscalar architecture these points are raised to 85% and 78%, respectively. Figure 5 shows the average performance in both superscalar architectures. Actually, we can note that, when the branch prediction accuracy is improved, the large architecture performance increases more intensively than the performance obtained by the small superscalar architecture. This fact happened because when the predictor is better there are more possibilities to exploit instruction level parallelism. However, this advantage is possible only when resources are available. On the other hand, when the hardware is enlarged there are more
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4. Evaluating the effects of branch prediction accuracy
possibilities to exploit instruction level parallelism, so we can also see improvements in performance from the small to the large architectures for the same prediction accuracies. Although there is a performance increase, in this case the increase is more significant for higher prediction accuracies.
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Figure 4 Performance of the large superscalar Another important issue in Figure 5 is that the small superscalar architecture with perfect accuracy achieves the same performance as the large one with accuracy near to 75%. In those circumstances, all efforts that are being done to improve the predictors could be directed to expand the hardware, achieving the same results. Indeed, the cost of each implementation should be considered in order to determine the best cost-benefit but it is clear that the performance is a combination of various aspects. For example, it is not possible to have an IPC greater than 2 for the small architecture even considering perfect branch prediction. However, for the large architecture this could be possible using a 85% accuracy branch predictor. Furthermore, the improvement of accuracy from 95% to 100% causes an increase of about 7% and 9% in the global performance to small and large architectures, respectively, as shows Figure 6. In this Figure, the speedup bar is the improvement of an architecture with a given
predictor accuracy, in terms of average IPC, over the immediately previous accuracy simulated. For example, the speed-up for the large architecture using a 85% accurate branch predictor over the performance of the same architecture using a 80% accurate predictor is around 8%. No results are presented for accuracies of less than 50%. A verage P e rfo rm an c e of the S u pers c a la r A rc h itec tures
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parallelism so, the more accurate the predictor the more instructions these benchmarks will produce to enter the functional units. As the predictor gets better, mispredictions are reduced and more instructions become available for dispatch. That is why the performance of one thread can interfere on the performance of other threads. On the SMT-8 there are resources to support all threads, even when more parallelism is available as the predictor accuracy increases.
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We also analyzed the SMT-4 architecture. Figures 7 and 8 show the performance of each benchmark in both small and large SMT-4 architectures, respectively. In both architectures, the benchmarks ijpeg and li have reached the best performances again. Also, on the large SMT-4, the benchmarks mgrid and fpppp kept the same behavior observed on the superscalar architecture presenting a flat performance throughout all configurations. Notice that on the small SMT-4, benchmarks mgrid and fpppp were penalized by the branch prediction improvement. In the SMT architectures, the functional units are shared among all threads. Even though threads (benchmarks) are scheduled one each a time, the pool of functional units is shared among them. Then, when the predictor accuracy is increased, there is a chance for more parallelism, in this way reducing the amount of available resources. Some benchmarks have more implicit
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Figure 8 Performance of the large SMT-4 Figure 9 shows the global performance of both SMT-4 architectures (small and large). The performance is the sum of the individual IPCs for the benchmarks used in each simulation, see section III. The biggest impact of the branch prediction accuracy increase was found in the larger architecture, as in superscalar architectures. However, there is no intersection between the SMT-4 curves for the performance of the small and large architectures. Even though the SMT-4 small architecture has similar resources when compared to the superscalar large architecture, the performance is even better. The reason is because in the SMT architecture there are multiple threads, in this case four. When multiple threads are being executed, there is more room to exploit the parallelism either in the thread level or in the instruction
Global Performance of the SMT-4 Architectures
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prediction accuracy improvements. Analyzing their codes we verified that the number of instructions per branch is near to 70~80 (average size of basic block). Thus the performance of these benchmarks is not limited mainly by the accuracy of the predictor, but it depends basically on the data dependencies and available resources. Speed-up over the Prediction Accuracy Improvements
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level. Notice that the performance of the small SMT-4 is limited by resource conflicts as the improvements in the prediction accuracy do not impact in the global performance at all. Therefore, the performance of the large SMT-4 shows more significant improvement as the predictor accuracy increases. Despite the small SMT-4 achieves a better performance than the large superscalar architecture, the performance curve is flat. This means that the predictor does not need to be as accurate as in the superscalar because the resources are being used essentially by multiple threads. Hence, the parallelism at the instruction level is not the key role in this scenario.
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Figure 9 Global performance of the SMT-4 Figure 10 shows the speed-up over the improvement of branch prediction accuracy as described previously. In this graph, we can see that the perfect branch prediction in the large SMT-4 architecture implies in a speedup about 18% over the same architecture with branch prediction accuracy of 95%. In the large SMT-4 we have observed that the predictor affects the performance because the resources available allow also to exploit more instruction level parallelism. In the small SMT-4 the resources are enough to exploit only the thread level parallelism. We concluded that when thread level is the main parallelism being exploited the accuracy of the predictor does not interfere at all. To measure the impact of the branch prediction accuracy in more aggressive SMT architectures, we have made simulations with 8 simultaneous tasks. Figure 11 shows the performances for each benchmark in a small SMT-8. In this graph, it is possible to see clearly that the increase in the number of tasks generates an overhead making the performance decrease even when the prediction accuracy is improved. When comparing with the small SMT-4 (Figure 7) we see that the lack of resources in this case harms the performance of some benchmarks. Figure 12 shows the results achieved by the large SMT-8 architecture. Once again the experiments confirm that the benchmarks mgrid and fpppp are not affected by
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Figure 12 Performance of the large SMT-8 The comparison between the global performance of
both small and large SMT-8 architectures is shown in Figure 13. We can note that the small SMT-8 architecture was almost not affected by the accuracy increase. As in the small SMT-4 (Figure 9) the availability of resources compared with the number of threads does not allow the instruction parallelism to be exploited as well. Therefore, the large SMT-8 presents a wide improvement as the prediction accuracy increases. This happens because there are resources enough to allow the instruction level parallelism to be exploited as well as the thread level parallelism. In this case, we see a significant improvement, if compared with any other previous case analyzed in this work. Global Performance of the SMT-8 Architectures
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Figure 13 Global performance of the SMT-8 Figure 14 shows the speed-up over the prediction accuracy for the small and large SMT-8 architectures. In fact, the small SMT-8 architecture has its speed-up reduced with the increase in the prediction accuracy. As we can see in Figure 13, there is no improvements in performance as the accuracy is increased.
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Figure 14 Speed-up over the prediction improvements
Thus, as the speed-up measured is the ratio between the performance of one architecture over the same architecture with a 5% less accurate predictor then the speed-up is reduced as the predictor accuracy is increased. On the other hand, the large SMT-8 architecture shows a
speed-up of 18% when the accuracy is increased from 95% to 100%.
5. Conclusions In this work we presented a comparison between a superscalar and a SMT architecture based on the impact of the branch prediction accuracy improvements. We analyzed both architectures under different scenarios which comprised different configurations (i.e., resources available) and different prediction accuracies. For the superscalar architecture we figured out that branch prediction improvements presented always some benefit in terms of performance. The better the predictor the better the performance. Although we observed improvements over the increase in the predictor’s accuracy the improvements from 95% to 100% are in the range of 7% to 9%. The superscalar architecture used in this simulations has a six stages pipeline. For deeper pipelines the improvements in the branch prediction accuracy might result in more gains, considering the misprediction penalties would affect more the performance. Regarding the SMT architectures we observed two different behaviors. First, for the small SMT we saw a flat performance curve when varying the branch prediction accuracy. In these cases the prediction did not affect the performance. If the ratio between the number of threads and the number of resources (threads/resources) is high, it means that probably the thread level parallelism is prioritized. Hence, instruction level parallelism is not the most important factor in the performance and prediction accuracy does not affect it as in the superscalar architecture. Second, for the large SMT we observed an improvement either by increasing the resources or the prediction accuracy. In these architectures the amount of available resources used was enough to exploit both thread and instruction level parallelism. When instruction level parallelism affects directly the performance then the prediction accuracy has an important role in the performance as well. In the large SMTs the ratio between the number of threads and the number of resources tends to be lower than in the small SMTs. Despite the SMT-8 architecture have twice more resources than SMT-4, it executes 8 applications while the SMT-4 architecture executes only 4. In this way, the resources available are the same for each application. We can conclude that when we increase resources and also proportionally the number of tasks on a SMT architecture, the global performance increases in the same ratio as well. For this reason, the effect of the improvement of the branch prediction in both architectures are also similar. If the ratio “number of threads / amount of resources” decreases, the performance benefits caused by increasing
the branch prediction accuracy can be higher than 18%. As presented in Figure 14 for the large SMT-8, 18% was the highest speed-up obtained when increasing the prediction accuracy from 95% to 100%. If more resources were available, the ratio “threads/resources” would be smaller and the speed-up could be higher than 18%. Even though the SMT and superscalar have a different behavior, we observed that the effect of the improvement in the prediction accuracy is similar for both architectures. For future works, the design of a branch prediction mechanism with variable branch target address prediction would allow the study of the effects of branch target address misprediction in both superscalar and SMT architectures. Another important issue is that the performance of the branch predictor can be affected by the multiple threads contexts. This was not in the scope of this work, but a study of this effects could be done.
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