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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 56, NO. 7, JULY 2009

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Extended Operation of Cascade Multicell Converters Under Fault Condition Pablo Lezana, Member, IEEE, and Gabriel Ortiz

Abstract—Multilevel converters are an interesting alternative for high power drives, due to their good quality output signals. Despite their advantages, the large number of components required increases the fault probability. Among the multilevel topologies, the cascade multicell converter presents advantages when operating under internal fault conditions, due to its high modularity. Previous works proposed to compensate the unbalanced operation due to a fault by changing the canonical fundamental output phase shift to precalculated angles, depending on the fault condition. This solution assumes that, if the maximum output phase voltage on each leg is used, the maximum line-to-line voltage will be at a maximum as well. This paper shows how this assumption is not always valid and presents the optimum angles and modulation indexes that must be used in order to obtain the maximum balanced load voltages. Index Terms—Converters, fault tolerance, multilevel converters.

N OMENCLATURE x x X N n vY vy A−B−C

Electrical variable. Phasor of electrical quantity x. Magnitude of electrical phasor x. Load neutral point. Inverter neutral point. Load voltage for phases a, b, and c, where Y ∈ {A, B, C}, respectively. Inverter voltage for phases a, b, and c, where y ∈ {a, b, c}, respectively. Number of operative cells on phases a, b, and c, respectively, where {A, B, C} ∈ Z+ . I. I NTRODUCTION

A

FTER two decades, multilevel converters are still in continuous development in fields such as Static Compensators [1]–[3], photovoltaics [4]–[6], topologies [7]–[9], and modulation and control techniques [10], [11]. All the multilevel topologies, namely, neutral point clamped [12], cascade multicell (CM) [13], [14], and flying capacitor [15], require a large amount of components [16] in order to distribute the voltage (and, hence, the power) among them. An associated issue related to a high number of components is an increase Manuscript received December 11, 2008; revised February 4, 2009. First published April 14, 2009; current version published July 1, 2009. This work was supported by the Chilean Research Fund (FONDECYT) under Grant 1085111. P. Lezana is with the Departamento de Ingeniería Eléctrica, Universidad Técnica Federico Santa María, Valparaíso, Chile (e-mail: [email protected]). G. Ortiz was with the Departamento de Ingeniería Eléctrica, Universidad Técnica Federico Santa María, Valparaíso, Chile. He is now with the Power Electronic System Laboratory, Eidgenoessische Technische Hochschule, Zürich, Switzerland (e-mail: [email protected]). Digital Object Identifier 10.1109/TIE.2009.2019771

Fig. 1.

(a) Eleven-level CM converter. (b) H-bridge cell fed by a diode bridge.

in the probability of internal fault. However, most multilevel converters allow themselves to be reconfigured in order to work in an under-rated operation mode [14], [17]. This paper is focused on the CM converter operation after an internal fault condition has been detected, either by sensing each power switch or using a more sophisticated method [17]–[19]. A good characteristic of CM converters is that faulty cells can be isolated from the system by using an external switch [T in Fig. 1(b)] that even allows the faulty cell to be replaced by a new one without turning off the system [20]. Then, the problem becomes how to obtain the highest power level with the remaining operative cells. In [21], the redundant states of the CM converter are used to avoid the switching states that are no longer available due to the fault. As space-vector modulation is used, the well-known hexagon obtained from the α−β transformation changes its geometry, and depending on the fault, a nonregular hexagon or even a rhombus is obtained. Then, a diminished maximum balanced stationary voltage vector, defined by a circular trajectory, is reached. A different approach is used in [20], where triangular carrierbased PWM modulation is used. In this paper, the fundamental output voltage phase shifts are used to recover the balanced operation. As the phase shift between the inverter output voltages is no longer 120◦ , a fundamental component is injected into the common mode voltage between the inverter and load neutral points, which not only increases the load voltages but also the voltage stress on the motor bearings, which can lead to a parasitic current sent through them [22], [23].

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Fig. 2. Fasorial diagram of the 11-level CM. (a) Normal operation. (b) Operation under fault 5-5-3. (c) Balanced operation under fault 5-5-3 according to [20].

This paper is focused on the same approach as [20]. An additional degree of freedom is used to calculate the proper fundamental phase-shift angles, in order to provide a solution for faults not covered in that work. As will be shown in Section III, in some cases, a higher balanced line-to-line voltage can be obtained if the modulation index in the higher output inverter voltage is properly set. Moreover, this not only can increase the power delivered to the load but also significantly reduces the possibility that some cells start to regenerate power (a problem briefly announced in [24]), which can severely damage the converter. Experimental results obtained with an 11-level laboratory prototype are provided to validate the analytical background. II. CM I NVERTER A. Normal Operation The CM inverter introduced in [13] and [14] is based on the cascade connection of several structures, known as cells, as shown in Fig. 1(a). Generally, each cell is composed by an H-bridge inverter and an isolated dc voltage source, which can be obtained from the following: 1) a diode bridge fed by a secondary of a multipulse transformer and a capacitive dc link [14] [Fig. 1(b)]; 2) a photovoltaic panel [4], [6]; 3) batteries [25]–[27]. However, other topologies have been proposed in literature [28], [29]. As the cells are connected in series, the total output voltage for i cells per phase is  vyi , y ∈ {a, b, c} (1) vy = vyn = i

as shown in Fig. 2(a) for a five-cell-per-phase CM inverter. On the other hand, each H-bridge can generate up to three voltage levels between its terminals vyi ; then, the maximum number of voltage levels that can be reached is ˆl = 2i + 1.

(2)

Many modulation techniques have been developed for this topology [3], [10], [30]–[32]. In this paper, the phase-shifted

PWM modulation will be used, due to its easy implementation, modularity, and real application [33]. B. Operation Under Internal Fault As previously stated, the CM inverter is a fully modular structure. In the case of internal fault of one or more cells per phase, they can be bypassed and hence isolated from the system through an external switch T , as shown in Fig. 1(b), while the load can be powered by the rest of the inverter cells. However, while the converter works in fault state, the load will be fed by unbalanced voltages, unless special control and/or modulation schemes are considered. In [20] and [24], this unbalance, generated by the asymmetrical inverter voltage magnitudes, is compensated by changing the natural 120◦ fundamental phase shift between the output voltages, by solving the nonlinear equation system Va2 +Vb2 −2Va Vb cos(α) = Vb2 +Vc2 −2Vb Vc cos(β) = Vc2 +Va2 −2Vc Va cos(γ) α + β + γ = 360◦

(3) (4) (5)

where α = ∠(va , vb ), β = ∠(vb , vc ), and γ = ∠(vc , va ). In the following sections, the notation A-B-C will be used to denote different fault operation cases, where A, B, and C will indicate the number of operative cells in the respective phase. As an example, for an 11-level CM, if two cells fail in phase c, this notation will lead to 5-5-3. This case is shown in Fig. 2(b), where the inverter and line-to-line voltages are clearly unbalanced. Then, if the load is an electrical machine, pulsating torque will be observed. By using (3)–(5) to rebalance the load voltages, the fundamental output voltage phase-shift angles obtained are α = 95◦ β = 132.5◦ γ = 132.5◦ . Then, a balanced line-to-line voltage of 7.36 per unit (p.u.) (an operation 15% lower than normal) is reached, as shown in Fig. 2(c). Table I summarizes the fundamental phase-shift compensation (FPSC) angles and the maximum line-to-line voltage for

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LEZANA AND ORTIZ: EXTENDED OPERATION OF CASCADE MULTICELL CONVERTERS UNDER FAULT CONDITION

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TABLE I FPSC TECHNIQUE APPLIED TO AN 11-LEVEL INVERTER

Fig. 4. (a) Calculation of the proper modulation index according to the proposed method. (b) Proposed method applied to 5-3-2 fault.

between them is 180◦ ; thus, l = a + b reaches a magnitude of l = a + b.

(6)

This condition is also valid for phasors and, hence, for lineto-line voltages. For a 4-3-2 operation, the angle between vb and vc is β = 187◦ ; then, the line-to-line voltage is close to 5 p.u. On the other hand, for a 5-3-2 operation, the angle is β = 120◦ , reducing the line-to-line voltage to 4.36 p.u. To reach β = 180◦ , for 4-3-2, it would be necessary to “push” the inverter neutral point n toward the triangle formed by the line-to-line voltages, which is not possible because phase a cannot increase its voltage over 4 p.u. to keep balanced lineto-line voltages. For 5-3-2, however, it is necessary to “pull” n toward the line-to-line triangle. Fortunately, this can be easily done by reducing the total voltage of va from Va to Va , by properly adjusting the modulation index in this phase only. Using Fig. 4(a), Va and the fundamental phase-shift angles can be calculated as follows:  Va = Vb2 + Vb Vc + Vc2 (7) √  3 Vb + Vc α = arcsin (8) 2 Va γ = 180◦ − α β = 180◦ . Fig. 3. Operation under fault after the fundamental phase-shift method is applied: (a) 5-3-2 and (b) 4-3-2 faults.

the possible faults of an 11-level CM inverter. Note, however, that, for some fault conditions, there is no available solution. III. P ROPOSED M ETHOD A. Load Voltage Improvement The previously described method is based on the idea that higher inverter voltages will lead to higher load voltages, which seems to be an obvious assumption. However, it can be observed from Table I that, in fault operation, that idea is not always true. As an example, the operation state 5-3-2 gives a balanced line-to-line voltage of 4.37 p.u., while 4-3-2 gives 4.96 p.u., which is 13.5% higher with one cell less in phase a. Both fault conditions, after the FPSC, are shown in Fig. 3. In mathematics, it is a well-known fact that the biggest difference between two vectors a and b will occur when the angle

(9) (10)

Then, for the 5-3-2 operation [see Fig. 4(b)], Va = 4.36 p.u., α = 74◦ , and β = 96◦ , reaching the maximum theoretical balanced line-to-line voltage of 5 p.u. Note that the proposed method can be applied only when the solution achieved by the traditional FPSC locates the inverter neutral point outside the line-to-line triangle. Table II shows the calculated magnitudes and angles for such cases. It is important to remark that the proposed method can also find a solution for all cases. B. Load Power Factor Effect In [24], a relevant drawback of FPSC is mentioned. Depending on the fault and in the load parameters, an inverter phase can receive instead of supply power to/from the load. Then, the cell capacitors of such phase will tend to increase their voltages, which can lead to their destruction, unless clamping circuits or active rectifiers at the input side of each cell [29], [34] are used. This phenomena can be explained through Fig. 5. The balanced load voltages vA , vB , and vC generate balanced load

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TABLE II BENCHMARK BETWEEN PROPOSED TECHNIQUE AND PREVIOUSLY REPORTED METHOD

to load voltage phase shift, it is necessary to locate the inverter and load neutral points. By setting the origin at point c, the coordinates for both neutral points are   Vll Vll , √ (12) vN = (xN , yN ) = 2 2 3   Vc Vc Vb (Vc − Vb cos(ξ)) , sin(ξ) vn = (xn , yn ) = Vll Vll  β, β < 180◦ (13) ξ= ◦ 360 − β, β ≥ 180◦

Fig. 5. fault.

Phase-shift relationships between inverter and load variables under

currents ia , ib , and ic , where the phase shift between the currents and the voltages φo depends on the load characteristic. On the other hand, the phase shift between the inverter voltages and the load current will not only depend on the load characteristic but also on the phase shift between the inverter and load voltages φa , φb , and φc , according to ϕy = ∠(vy ,iy ) = φy − φo ,

y ∈ {a, b, c}.

(11)

Then, for each inverter, phase load can be seen as follows: 1) mainly resistive ϕy ≈ 0◦ ; 2) mainly inductive ϕy < 0◦ ; 3) mainly capacitive ϕy > 0◦ ; 4) an active load 90◦ < ϕy < 270◦ . As previously explained, this last case is the most critical and must be avoided if diode-based rectifiers are used at the input of the cells; therefore, restrictions in the FPSC or load characteristics must be used. Note that the method proposed in Section III-A also applies an FPSC, and thus, the previously described phenomena affects it too. To calculate the maximum load angle value that avoids the dc-link voltage increase φˆo or the equivalent maximum inverter

where Vll = |vab | = |vbc | = |vca |. Then, the load to inverter phase shifts are   Vll − 2xn φa = arcsin 2V   a yn − 30◦ φb = arcsin Vb   yn φc = arcsin − 30◦ . Vc

(14) (15) (16)

Note that all the phase shifts are different and depend on the magnitudes of their respective inverter voltages. By using (11), the maximum values for φˆo can be calculated for any fault. Table II shows the values for φˆo for each case, where the proposed method can be used. Note that, compared with FPSC, the proposed method not only lets a larger voltage be applied to the load but also a larger load angle can be used, increasing the operation range of the system and improving the availability of the system for all cases. IV. R ESULTS The proposed compensation technique was tested in an 11-level 4-kW CM prototype shown in Fig. 6. This prototype is based on IR4GPC30 insulated-gate bipolar transistors, each one switching at 1 kHz. The overall converter is controlled by a TMS320C6713 DSP, which generates the references for the 15 cells, and an XC3S400 field-programmable gate array (FPGA), which handles all the peripherals required for the modulators. The experimental results of the proposed fault correction strategy on the load voltage improvement and the load power

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LEZANA AND ORTIZ: EXTENDED OPERATION OF CASCADE MULTICELL CONVERTERS UNDER FAULT CONDITION

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fundamental amplitude dramatically to nearly 200 V, which can lead to unbearable stress on the machine bearings. The compensation proposed in Section III-A is applied at t = 200 ms. A small increase in the line-to-line voltages can be seen in Fig. 7(b), which leads, as predicted by Table II, to an increase of the output current amplitude by ≈14.25% in relation to the previous situation [Fig. 7(c)]. It can be noted from Fig. 7(d) that the proposed method reduces the fundamental amplitude of the common mode voltage, generating a more bearable operation condition for the load. B. Load Power Factor Effect in 5-4-1 Fault Fig. 6.

Schematic of the experimental prototype. TABLE III MOST RELEVANT CONVERTER PARAMETERS

factor will be independently analyzed through the 5-3-2 and 5-4-1 faults, respectively. For each of the tests, the most relevant converter parameters are summarized in Table III. A. Load Voltage Improvement in 5-3-2 Fault The electrical variables for the reconfiguration sequence in this case can be seen in Fig. 7. At up to t = 40 ms, the system operates in normal conditions. In Fig. 7(a), it is clearly seen that balanced 11-level voltages are generated at the inverter output, while, as can be seen in Fig. 7(c), balanced nominal currents are provided to the load. Fig. 7(d) shows that the common mode voltage through normal operation is only composed by high frequency commutations. The fault occurs at t = 40 ms, when two cells on phase a and three cells on phase c fail and are instantly short circuited. In Fig. 7(a), the effect of this fault is shown, where phase b now operates with seven levels while phase c operates with only five levels. As, up to this moment, no compensation has been applied, line-to-line voltages become unbalanced [Fig. 7(b)], providing unbalanced currents to the load [Fig. 7(c)]. It is important to notice from Fig. 7(d) that, after the fault, the common mode voltage has a significant fundamental component. As discussed in Section II-B, balanced line-to-line voltages, and, hence, load voltages, can be obtained by adjusting the phase angle between the inverter output voltages through Table I. This compensation is applied at t = 120 ms, obtaining balanced line-to-line voltages while inverter voltages are unbalanced, as shown in Fig. 7(a) and (b), respectively. The effect of the FPSC on the output currents can be seen in Fig. 7(c), where balanced currents are obtained with considerably less amplitude in relation to normal operation. An important drawback of this reconfiguration strategy is its effect on the common mode voltage. Fig. 7(c) shows that this voltage increases its

To test the proposed method on the load power factor, the converter was tested under the 5-4-1 fault using the respective parameters shown in Table III. It should be noted that, under these conditions, the load presents an angle of φo ≈ 40◦ , which is larger than the allowed load angle of φo = 10.9◦ that can be driven using the method proposed in [20]. The results for this test are shown in Fig. 8. Up to t = 40 ms, the converter operates under normal conditions, applying balanced 11-level voltages on its output [Fig. 8(a)] and, hence, balanced currents to the load [Fig. 8(b)]. As can be seen in Fig. 8(a), after t = 40 ms, one cell on output phase b and four cells on output phase c present internal faults and are short circuited immediately. Naturally, under this condition, output currents, shown in Fig. 8(b), become unbalanced. The compensation through Table I is applied at t = 120 ms. As mentioned in Section III-B, due to the load and operation characteristics, after this compensation is applied, the remaining cell on phase c receives energy from the output. The diodebased rectifier does not allow power to be taken from the dc link to the grid; thus, this energy is stored in the dc-link capacitor, increasing its voltage. This situation is shown after t = 120 ms in Fig. 8(c). It can be seen that the dc-link capacitor of the operating cell on phase c increases its voltage by almost 50% in four fundamental cycles. If no actions are taken, the sustained operation under this condition will lead to the destruction of the operating cell in phase c. At t = 200 ms, the fundamental phase angles and the amplitude of phase a are changed to the proposed values shown in Table II. Under these conditions, the dc-link voltage of the operating cell on phase c decreases dramatically, finally reaching its normal value. In addition, balanced and 8.8% higher output currents are provided to the load [see Fig. 8(b)], allowing the load to be continuously driven in these conditions. V. C ONCLUSION The modularity of the CM converter lets balanced currents be provided to the load even under faulty operation. In this paper, an enhancement to the FPSC fault correction strategy was proposed for the CM converter. Under certain fault conditions, the new strategy can increase the power supplied to the load. Moreover, the fundamental component of the common mode voltage is considerably reduced when applying the new reconfiguration strategy, creating a more bearable operation condition for the load.

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Fig. 7. Waveforms for a 5-3-2 fault at t = 40 ms. (a) Inverter voltages. (b) Line-to-line voltages. (c) Output currents. (d) Common mode voltage.

Fig. 8. Waveforms for a 5-4-1 fault at t = 40 ms. (a) Inverter voltages. (b) Output currents. (c) DC-link voltage of a cell in phase c.

In addition, the effect of both revised reconfiguration strategies on the load power factor was deeply studied. It was shown that, by using the existing reconfiguration technique on some

particular faults, it is probable that the load will provide power to one or more output phases, increasing the voltage of their dc-link capacitors. On the other hand, by using the proposed

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reconfiguration strategy, the load operating range is considerably increased, allowing to continuously provide balanced voltages to the load at all operating conditions. All the previously mentioned features were validated through experimental results. R EFERENCES [1] J. A. Barrena, L. Marroyo, M. A. R. Vidal, and J. R. T. Apraiz, “Individual voltage balancing strategy for PWM cascaded H-bridge converterbased STATCOM,” IEEE Trans. Ind. Electron., vol. 55, no. 1, pp. 21–29, Jan. 2008. [2] Q. Song, W. Liu, and Z. Yuan, “Multilevel optimal modulation and dynamic control strategies for STATCOMs using cascaded multilevel inverters,” IEEE Trans. Power Del., vol. 22, no. 3, pp. 1937–1946, Jul. 2007. [3] W. Song and A. Q. Huang, “Control strategy for fault-tolerant cascaded multilevel converter based STATCOM,” in Proc. 22nd Annu. IEEE APEC, Feb. 2007, pp. 1073–1076. [4] O. Alonso, P. Sanchis, E. Gubia, and L. Marroyo, “Cascaded H-bridge multilevel converter for grid connected photovoltaic generators with independent maximum power point tracking of each solar array,” in Proc. IEEE 34th Annu. PESC, Jun. 2003, vol. 2, pp. 731–735. [5] S. Busquets-Monge, J. Rocabert, P. Rodriguez, S. Alepuz, and J. Bordonau, “Multilevel diode-clamped converter for photovoltaic generators with independent voltage control of each solar array,” IEEE Trans. Ind. Electron., vol. 55, no. 7, pp. 2713–2723, Jul. 2008. [6] P. Flores, J. Dixon, M. Ortuzar, R. Carmi, P. Barriuso, and L. Moran, “Static var compensator and active power filter with power injection capability, using 27-level inverters and photovoltaic cells,” IEEE Trans. Ind. Electron., vol. 56, no. 1, pp. 130–138, Jan. 2009. [7] M. Ma, L. Hu, A. Chen, and X. He, “Reconfiguration of carrier-based modulation strategy for fault tolerant multilevel inverters,” IEEE Trans. Power Electron., vol. 22, no. 5, pp. 2050–2060, Sep. 2007. [8] C. Rech and J. R. Pinheiro, “Hybrid multilevel converters: Unified analysis and design considerations,” IEEE Trans. Ind. Electron., vol. 54, no. 2, pp. 1092–1104, Apr. 2007. [9] G. Mondal, K. Gopakumar, P. N. Tekwani, and E. Levi, “A reducedswitch-count five-level inverter with common-mode voltage elimination for an open-end winding induction motor drive,” IEEE Trans. Ind. Electron., vol. 54, no. 4, pp. 2344–2351, Aug. 2007. [10] J. I. Leon, R. Portillo, S. Vazquez, J. J. Padilla, L. G. Franquelo, and J. M. Carrasco, “Simple unified approach to develop a time-domain modulation strategy for single-phase multilevel converters,” IEEE Trans. Ind. Electron., vol. 55, no. 9, pp. 3239–3248, Sep. 2008. [11] A. Shukla, A. Ghosh, and A. Joshi, “Improved multilevel hysteresis current regulation and capacitor voltage balancing schemes for flying capacitor multilevel inverter,” IEEE Trans. Power Electron., vol. 23, no. 2, pp. 518–529, Mar. 2008. [12] A. Nabae, I. Takahashi, and H. Akagi, “A new neutral-point-clamped PWM inverter,” IEEE Trans. Ind. Appl., vol. IA-17, no. 5, pp. 518–523, Sep. 1981. [13] M. Marchesoni, M. Mazzucchelli, and S. Tenconi, “A nonconventional power converter for plasma stabilization,” IEEE Trans. Power Electron., vol. 5, no. 2, pp. 212–219, Apr. 1990. [14] P. W. Hammond, “A new approach to enhance power quality for medium voltage drives,” IEEE Trans. Ind. Appl., vol. 33, no. 1, pp. 202–208, Jan./Feb. 1997. [15] T. A. Meynard and H. Foch, “Multi-level choppers for high voltage applications,” J. Eur. Power Electron. Drives, vol. 2, no. 1, pp. 45–50, Mar. 1992. [16] S. S. Fazel, S. Bernet, D. Krug, and K. Jalili, “Design and comparison of 4-kv neutral-point-clamped, flying-capacitor, and series-connected hbridge multilevel converters,” IEEE Trans. Ind. Appl., vol. 43, no. 4, pp. 1032–1040, Jul./Aug. 2007. [17] C. Turpin, P. Baudesson, F. Richardeau, F. Forest, and T. Meynard, “Fault management of multicell converters,” IEEE Trans. Ind. Electron., vol. 49, no. 5, pp. 988–997, Oct. 2002. [18] H. Son, T. Kim, D. Kang, and D. Hyun, “Fault diagnosis and neutral point voltage control when the 3-level inverter faults occur,” in Rec. IEEE PESC, Aachen, Alemania, Jun. 20–25, 2004, vol. 6, pp. 4558–4563. [19] P. Lezana, J. Rodriguez, R. Aguilera, and C. Silva, “Fault detection on multicell converter based on output voltage frequency analysis,” in Proc. 32nd Annu. IEEE IECON, Nov. 2006, pp. 1691–1696. [20] J. Rodríguez, P. Hammond, J. Pontt, R. Musalem, P. Lezana, and M. J. Escobar, “Operation of a medium-voltage drive under faulty con-

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Pablo Lezana (S’06–M’07) was born in Temuco, Chile, in 1977. He received the M.Sc. and Doctor degrees in electronic engineering from the Universidad Técnica Federico Santa María (UTFSM), Valparaíso, Chile, in 2005 and 2006, respectively. From 2005 to 2006, he was a Research Assistant with the Departamento de Electrónica, UTFSM. Since 2007, he has been a Researcher with the Departamento de Electricidad, UTFSM. He contributed to one chapter in the Power Electronics Handbook (Academic Press, 2007). His research interests include power converters and modern digital control devices (DSPs and fieldprogrammable gate arrays). Dr. Lezana received the IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS Best Paper Award in 2007.

Gabriel Ortiz was born in Chuquicamata, Chile, on September 13, 1984. He received the M.Sc. degree in electronics engineering from the Universidad Técnica Federico Santa María, Valparaíso, Chile, in 2008, where he joined the power electronics group early in 2007 and, during his Master thesis, worked on the reconfiguration of regenerative and nonregenerative cascaded multilevel converters under fault condition, obtaining maximum qualification on his thesis examination. He is currently working toward the Ph.D. degree at the Power Electronic Systems Laboratory, Eidgenoessische Technische Hochschule, Zürich, Switzerland.

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