Fast solution of nonlinear equations using parallel ... - Springer Link

Analog Integrated Circuits and Signal Processing, 6, 135-156 (1994) © 1994 Kluwer Academic Publishers, Boston. Manufactured in T h e Netherlands.

Fast Solution of Nonlinear E q u a t i o n s Using Parallel A n a l o g H a r d w a r e J. A. BOND, J. E DORSEY, M. BROOKE, J. MAGILL AND J. TABLER School of Electrical Engineering, Georgia Institute of Technology, Atlanta, GA 30332

Received March 26, 1993. Revised December 22, 1993. Editor: M. Ismail

Abstract. Parallel analog circuits are introduced for the solution of systems of nonlinear algebraic equations and the integration of systems of differential equations. Both simulations using HSPICE and a hardware implementation are presented which show how the circuitry can be used to solve: the power flow and transient analysis problems for power systems, and the simulation of a jet engine. In all cases solutions are obtained in better than real time. The results are comparable in accuracy to digital solutions of the same problems.

1. Introduction The'. rise to preeminence of the general purpose digital computer over the past several decades has been so swift and spectacular that there currently seems to be little speculation about alternative computing technologies. While it is certainly true that digital technology will continue to be the central force in computing, analog VLSI technology has progressed to the point where it is worth considering some alternative approaches to computing for specific problems. What we are suggesting is that it may now be cost effective to build specialized computers that solve problems that are still intractable with a general purpose digital computer. In this paper we discuss two such problems: the integration of the differential equations that represent the dynamics of a large power system, and the integration of the nonlinear differential equations for a jet aircraft engine. It is currently impossible to integrate either of these sets of equations in real time using a digital computer. In the case of the power system equations the difficulty is the dimension of the problem.. Large power systems can have as many as 1000 generators, each requiring a minimum of a second order differential equation to represent it. The problem is further complicated by the fact that the differential equations are coupled to a large set of nonlinear algebraic equations, called the power flow equations which must be solved recursively multiple times in each integration step. In the case of the jet aircraft engine the

number of differential equations is small, but the rates of change of the derivatives are so large that an extremely small integration time step is required. In both cases the ability to integrate the equations in real time, or faster than real time, would provide a major advance in the control of these systems. For the jet aircraft engine, knowing the behavior of the engine in advance opens the door for predictive control to prevent compressor surge and stall, and to achieve higher performance by designing engines that can operate closer to surge and stall than is now possible. For power systems, being able to simulate the behavior to a disturbance in better than real time would help system operators to make more timely decisions that could prevent unwanted oscillations and instabilities. In this paper we will concentrate on the solution of the dynamic equations of a power system, and summarize some results on the solution of the equations for the jet aircraft engine. For the power system problem, the approach we will present in this paper uses a combination of analog and digital circuitry. Other applications, such as jet aircraft engine control, will require minimal digital circuitry. For the power system problem, the role of the digital circuitry is data management. The digital circuitry will hold the data that defines the topology of the power system, i.e. how the load buses and generators are interconnected, plus known parameter values, and use the data to: 1) configure the analog circuitry to represent the power system topology, 2) initialize the analog

136

Bond, Dorsey, Brooke, Magill and Tabler

circuitry, and 3) retrieve the solution from the analog circuitry. The analog circuitry provides the massive parallelism that allows all the differential equations to be integrated at once, and all the power flow equations to be solved simultanenously. The analog circuits used are very simple. This means that for this specific problem, we can apply the effective computing power of an Intel-486 to each dynamic equation by using a handful of precision multipliers, and a few analog zero order holds. The result is an extremely compact VLSI circuit that eliminates the processor interconnection problems of general purpose parallel digital computers, and is ideally suited for onboard applications such as aircraft or spacecraft control, where size and weight are important factors. The power system problem represents a demanding test bed for this new approach because the equations required to represent a large power system are among the largest examples of differential, algebraic equations (DEA's). Because of their size and complexity, these equations were one of the first applications for digital computers [2]. The proposed computing circuitry can achieve, for the transient period following a disturbance, the same accuracy as a digital computer while providing a speed increase of four orders of magnitude. As we will show, the only limitation to successfully scaling up the proposed computing technology to large scale systems is the accuracy of analog VLSI multipliers. We have already developed VLSI multipliers that are linear to within one percent. We address the problem of multiplier accuracy with HSPICE Monte Carlo simulations that use imprecise multipliers. In the next section we review the results of a previous paper [1] which shows how the power flow equations can be solved by a completely parallel hybrid computing scheme. We also introduce modifications to the original scheme that greatly increase the stability of the solution. In section three we introduce a scheme for integrating differential equations using analog circuitry. Section four presents the results of both a computer simulation, and a hardware implementation of the integration scheme for the case of one generator against an infinite bus. Section five discusses the transferral of the proposed circuitry to VLSI technology. Section six presents the application of this technology to the better than real time simulation of a jet engine. In section seven we discuss the HSPICE model of the multiplier and the fabrication of the multipliers.

In closing we note that the discussion of the power flow equations in the next section is included to make the paper as readable as possible for a general audience. The techniques proposed here have much wider application than simply power system analysis and consequently we do not wish to discourage readers unfamiliar with power system jargon.

2.

Design of the Analog Power Flow Solution Circuit

In a previous paper [1] we developed a method for solving the power flow equations simultaneously using analog circuitry. The power flow equations are a set of n - 1 complex or 2n - 2 real equations for n - 1 complex or 2n - 2 real unknown variables. In the simplest case the unknowns are the complex voltages for the system buses. The givens are the power consumed (load) and the power produced (generation) at each bus. In the more practical case we change the known and unknown quantities at certain buses, for instance at a generator bus we fix the voltage magnitude and leave the reactive generation as an unknown. There are other variations, but we always have n - 1 complex or 2n - 2 real equations and the same number of unknowns. The power system is modeled as buses (nodes) with fixed load and generation, interconnected by transmission lines modeled as fixed admittances. The power delivered to any bus is found by first computing the sum of the current entering the bus and then multiplying the conjugate of the current by the voltage at the bus:

= Z

-

-

-

m#n j.

:

-

+

-

S.)

m#n

p~ = e~i~ + I~J~ q,~ :

enj,~ - Ai,~

where {~ + 3J~ is the sum of the current entering bus n via transmission lines, Ohm + 3Bnm is the admittance of the transmission line connecting buses n and ra (an admittance of zero corresponds to the absence of a transmission line), en + 3fn is the voltage at bus n, and p,~ + 3qn is the power delivered to bus n. We note for completeness that 3 = v/Z-[.

Fast Solution of Nonlinear Equations Using Parallel Analog Hardware

fl" f2

137

el- e2

G12~

-B 1

B12

Current

Current Mirror

®

®

Mirror

Q

t'f 121

(9

J21 J12

112 Fig. 1. Blockdiagramof original line unit.

~n ]l,n

I

Z J,~

-e I

fl

]-

e,

]"

f,

Fig. 2. Blockdiagramof original bus unit.

Two circuits, one for the load bus and one for the tran:smission line, perform the above forward computations. Figures 1 and 2 are block diagrams of the line and bus units originally reported. The blocks rely on three subcircuits: multipliers, summers, and current mirrors. The multiplier, covered in more detail later, accepts two differential voltage inputs and produces a current output. Summation is performed by combining currents at a current controlled source. The current mirrors, shown in Figure 1, produce both a positive and negative version of the input current, and are used to distribute currents needed in more than one summation.

Offsets and nonlinearities can be added to the behavioral model of the VLSI multiplier shown in Figure 1 by using a polynomial input source. In the bus unit a current summing junction continuously compares the power delivered to the bus to the fixed load at the bus, and obtains the difference. This difference is a complex number p ~ + 3 q ~zx, with real part p ~ = p~ - pO and imaginary part q~ = q~ - qO The various bus units described in this section use this error as a feedback signal to update the bus voltages. In general this methodology can be applied to any set of algebraic equations. The difficulty arises in

Bond, Dorsey, Brooke, Magill and Tabler

138

developing an update law, that is a description of how the unknown variables are adjusted based on the error to the solution. In developing a continuous time update law to solve a set of nonlinear equations, it is necessary to determine the location of the solution relative to the present 'approximate' value of the solution, just as would be the case for a discrete update law using a digital computer. Indeed, the power flow equations have been solved for several decades using variations and combinations of the Gauss-Seidel and Newton-Raphson update laws. For power systems, we can get a reasonable idea of the direction to the solution at each bus by using the following well known [3] equations for the real power Pij and reactive power Qij transmitted between buses i and j as shown in Figure 3: p~j =

IWdlVjl sin(Si X

-

6j) (1)

we increase (decrease) the real power flow from bus i to j mainly by increasing (decreasing) the angle difference between the buses. Similarly, the flow of imaginary power depends primarily on the difference in the voltage magnitudes of the two buses, since for small angle differences cos(Si - 5j) is roughly one. In a real power system there are multiple connections between buses. To put the discussion of update laws into a more rigorous framework, we develop the following sensitivity equations for the change of the real and reactive power at bus n in terms of the voltage V~ at bus n. The real and reactive power flowing into bus n from the lines connected to it can be written as 2

Pn = --Vn E ~nrn men -- Vn E vm [Gnm COS ~mn -~ Bnm sin 5,~n] rnT~n 2 qn = Vn .)~ B~m TO.~n

[V~I~ - IVj IlVd cos(5, - 6j)

Qij =

- vn E

X

Vm [Gnm sin 6r~n - Bnm cos 5mn],

men

where Vi = IV l and Vj = IgjlcJd are the complex voltages at buses i and j respectively. We note for the nonexpert that these equations use the simplifying assumption that the impedance of the line connecting the two buses is purely inductive, that is ZUne = 3X. The line resistance, small compared to the imaginary component, is generally neglected. In keeping with the notation of the power community we use capital letters for (steady-state) phasor voltages. In developing the equations for the continuous update law, we will use lower case notation. The equations for Pij and Q~j provide a starting point for finding an update law. Under normal operating conditions the angle difference between two buses directly connected by a transmission line is small, on the order of five to ten degrees, and the voltage magnitudes are all normalized to a nominal value of 1.0 per unit (p.u.). Since the real power depends on sin(Si - 5j) Bus i

Bus j

where v~ = IV~l, ~ = Arg(Vn) and 6m~ = 5~ - ~5~. We represent the complex power components pn and qn by lower case letters since they are time varying quantities within the analog circuit. We next develop the sensitivities of Pn and qn to Vn using polar coordinates, even though we ultimately will write the update law for Vn in Cartesian coordinates. It simply proves easier to obtain the result using polar coordinates. The four partial derivatives of interest are:

Op~ -OVn

2Vn ~ Vnrn rnT~n -- E Vm[GnmC°SSmn ~- Bnmsin(~mn] m¢n

Op~

--

= - v,~ 2__, v . ~ l u ~ , ~ s i n

t-

- B~.~ cos o . ~ j

]

rn¢n

Oq~ Ov = 2vn E

Bnm

men - ~

v~[an~ sinSm~ - B~m cosS~n]

rnCn

Oqn 05~ Ground

Fig. 3.

-Vn E Power transfer between two buses.

mT~n

Vm[-GnmcOSdrnn - BnmsinSmn]

Fast Solution of Nonlinear Equations Using Parallel Analog Hardware The unit of voltage is usually normalized so that [V,~I ~ 1, and the unit of conductance such that B~m ~ - 1 . The impedance between buses n and m is Z~m = R + j X , where the ratio R / X is small ( on the order of 0.1 or less), and both R and X are positive. Similarly, the reciprocal of Zz, called the admittance of the line, is

Yt

=

l/Z1

= G~m

+

jBnm,

where the parameter Bnm is negative and much larger in magnitude than Gnm, which is positive. In lightly loaded power systems, the difference in voltage angle, (~mn, is small, and grows larger in magnitude as more power is transmitted. Thus, reasonable first approximation are G n m = 0 and B~m = -1, v~ = 1, sin 8mn = O, and cos 8mn = 1. With these assumptions, Opn/OV n and Oqn/05 n are zero or small. Further, Opr~/OS~ = - g and Oqn/Ovn = -g, where g is the number of lines connected to bus n. This is essentially the same result we obtained earlier using the twe bus example. This analysis leads to the following simple (original) update law: e~=q~

and

f n = P n~

(2)

The update law is implemented by passing the currents equal to p~ and qn~ through capacitors connected to ground and buffering the voltage to the rest of the circuit as in Figure 2. .This update law, reported in a previous paper [1], gaw~ good results. However, it does not always converge to the desired solution for all initial bus voltages. This is not unexpected, since the discrete update laws ~,

jlm(vn) ,~t',

d2

~,

dl

d3

I" ~ I

qZ/'/

New v n

Fig. 4. Effect of update law on Vn.

'~ Re(vn)

139

implemented on digital computers do not always converge for an arbitrary starting point either. This simply says we should not really expect any better convergence from the analog circuit than can be obtained with the digital search techniques. This simple update law assumes that the solution is near 1 + 30, where adjustments to the imaginary part of the voltage rotate the voltage vector and adjustments to the real part of the voltage scale the voltage vector. When the starting voltage is not near 1 + 30, these adjustments fail. By redirecting the rotation and scaling commands, based on the present solution voltage, the region of convergence can be expanded. We can do this by multiplying Vn by the 'update vector' q~ + 3P~ so that our update law becomes

L

=pl

A

'

(3)

where Pl is the rotation matrix that expresses the multiplication by q~ + 3P~. Equation (3) expresses the directional update of Vr~. Since the direction of change in Vn is relative to the direction of Vn, the effect on V~ can best be seen in Figure 4. I f p ~ is negative, as expressed by vector d3 or d4 in Figure 4, Vn is rotated clockwise which increases the flow of real power into bus n. If q~ is negative the update law also shortens Ivn I, increasing the reactive flow to the bus. If q~ is positive, [v~ I increases, decreasing the reactive flow to the bus. Ifp~ is positive, as expressed by vector dl or d2, the rotation is counterclockwise, which decreases the real power flow to the bus. Again, the sign ofq~ determines the magnification of Vs. If @ is negative, the directional update, or derivative, points inward causing IV,~I to decrease, thereby increasing the reactive power flow to the bus. If q~ is positive, the directional derivative points outward so that ]V~I increases and the reactive flow is decreased. Figure 4 also shows the relationship between existing discrete update (or search) algorithms that would be used on digital computers and the analog update law. In the digital implementation d4 would be an actual vector, added to V~ to obtain the new estimate, labeled 'new' Vn in the figure. The analog update works precisely the same way except that the updates are continuous in time. By using this update law and multiple starting points we obtain a convergence 'portrait'

140

Bond, Dorsey, Brooke, Magill and Tabler 2,

0

~0 O

-1.

-2 -2

I

-1

I

0 Real Part of Voltage at Bus 1

1

Fig. 5. Convergenceof bus voltagefor updatelaw based on Pl. for load bus '1' in a simple three bus power system, as shown in Figure 5. The new update law clearly changes Vn properly, but it has the drawback, evident in Figure 5, that if the voltage vector is zero there will be no adjustment. The update law introduces a new stable equilibrium point at the origin. When the voltage value falls below a certain value, it becomes impossible to deliver the demanded power. At this point the update law's attempt to increase reactive flow by decreasing JVn [, and to increase the real power flow by rotating Vn clockwise, results in a spiral into the origin. This difficulty arises only at load buses where for small IVnl th6 directional derivative points in the direction d4. At generator buses, [Vnl is held constant at a value near 1.0 and cannot spiral into the origin. To remedy this problem, we add a second rotation at load buses. In matrix form, this rotation is

IV~l= -(1-1Y,~l =)] P= =

(1 - I y ~ l =)

IGI =

When tV~I is away from zero, the off diagonal elements in the rotation matrix are essentially zero and we have a scaling matrix. When levi is near zero, we have a rotation counterclockwise of about 90 ° . This has the desired effect of changing a directional derivative from the d4 direction towards the d3 direction. Combining the two rotations, the update law for load buses becomes: IVnl2

(1 -IGI 2) p~

q~

- ( 1 -IVnJ z) 1

Iv~l 2 In

(4)

"

The matrix formulation is useful for seeing how the update law works. For implementation purposes, it is convenient to carry out the multiplications indicated above and reduce the update law to the following equations.

Fast Solution of Nonlinear Equations Using Parallel Analog Hardware

141

O

;>0

q-i

O

-1

-2 -2

-i

; Real Part of Voltage at Bus 1

1

2

Fig. 6. Convergence of load bus voltage for update law based on Pl and P2.

k~

- fnp

and kf = 2 aOn

2

2

% +f¢~

ek=

+

ks) ks -

and

Figure 6 shows that all starting points converge to the correct solution. Figure 7 shows how the update law is implemented. To evaluate the error characteristics of the various bus circuits discussed to this point, HSPICE simulations of the circuits were built. For no multiplier error the HSPICE simulations matched exactly the SIMNON simulations shown in Figures 5 and 6. Thirty runs of HSPICE were made for each of the bus circuits. For

these runs random errors were introduced with the constraint that, overall, the multipliers exhibited one percent nonlinearity. Figure 8 shows the result for the third bus circuit. The solutions, for a particular starting point, now lie in a pattern about the original single solution which is shown by the solid 'dot.' The standard deviation is 2.9mV for the real part e, and 1.4mV for the imaginary part f . The patterns for the other two circuits are similar and in fact are 'tighter' since these circuits have fewer multipliers. Even for the third circuit, which has the best global convergence properties the error in IVn] is about 0.266%, while the standard deviation of the angle is about 0.13 °, and represents an even smaller percentage error. Having established the update law for a load bus, we do the same for a generator bus. We already have a starting point for that update law, namely the first rotation matrix we applied to the load bus. Before proceeding, we discuss the various roles of the power flow solution in power system analysis.

142

Bond,Dorsey, Brooke, Magill and Tabler

-e,

-Q~

Q1

~ I CMirrreonrt 0~

,_

'l,reo:l

m

F~Q cM~re~ t

:ol

e~ Vl 2

T

T F/g. 7. Block diagram of third bus unit circuit.

The power flow is the single most used tool for analyzing power systems. As discussed earlier the power flow equations have no dynamics; a generator is modeled as a node (or bus) that produces a certain fixed amount of real power. In the network representation of the power system, a generator bus represents the external terminal of the generator.

to use. In its simplest form the intermediate circuitry is a complex impedance, and the generator dynamics are the Newtonian equations of motion, the so called swing equations. This is the model that we will use since it is the model used to determine the behavior of the system immediately after a major disturbance, such as a fault.

When we discuss the dynamic behavior of a power system in the next section, the power flow reappears in a support role, determining the power balance between the generators and the network (including load) at each integration step. To use the power flow in this latter role we have to account for the generators by connecting the terminal bus of the generator to an internal bus through some intermediate circuitry. This intermediate circuitry is a function of the generator model we choose

For this simple representation of the generator, the internal voltage will change in angle but not in magnitude, during a disturbance. We determine the change in the internal angles by numerical integration. During each integration step these internal voltages will be fixed and a power flow solution obtained for the generator terminal buses and the load buses. For either type of power flow, a generator terminal bus is modeled by a fixed real power output and a fixed

Fast Solution of Nonlinear Equations Using Parallel Analog Hardware -216

!

I

i

i

i

143

--r

-217 -218 x

-219

x

x

x

x

x

x

x

x

-220 x

x x x x

-221

x

X

x

x

-222

x*

x

-223 -224 764

, 766

, 768

, 770

I 772

, 774

, 776

778

Fig. 8. Scatter plot of third bus solutions.

voltage magnitude. The unknowns are thus voltage angle and generated reactive power. The update law for the voltage must hold the voltage magnitude constar~Lt while adjusting the voltage angle to deliver the desired real power to the system. The update law for voltage takes the place of that for reactive power and is of similar form. The voltage magnitude is computed and then compared with the desired fixed voltage. The difference is used to adjust the voltage. Real power error is handled similarly to the load bus method. The following equations describe the analog computations for generator bus voltage solution: vn

=

ivo?

_

%2 -

&

L

f~

fn

As can be seen, v nA has simply replaced q~ as the ondiagonal elements of the rotation matrix. For implementation, these equations are rewritten as dn =: e n v n~ -

fnP~n

and

•

=

f n V n~ + enp~n

(5)

In this section we have developed the necessary circuitry to do a power flow solution for a power system

of arbitrary size totally in parallel. As reported in [1] we have successfully implemented the simplest of the various proposed circuits. The ability to do a power flow in a matter of milliseconds is of itself of major importance, since the power flow is widely used for power system analysis. The solution of the power flow is also an important part of our next goal which is to show how the power flow circuitry can be combined with additional circuitry to solve a problem of even more interest to system operators, namely the transient stability problem. Transient stability refers to a power system's dynamical behavior immediately after a major disturbance, when the generators start to swing apart. To prevent this, automatic relaying is employed to counteract the disturbance and keep the generators in synchronism. The term 'first swing' stability is sometimes used, meaning that if all generator angles swing apart and then make a first swing back, the system is deemed stable. This first swing always occurs within the first second following a disturbance, and typically within the first quarter second. The behavior of the power system during this period can be determined by digital computer, but it takes on the order of minutes to obtain the first second of

144

Bond,Dorsey, Brooke, Magill and Tabler

actual system response, because the differential equations for all machines have to be solved sequentially using iterative techniques. This is true even if a parallel digital computer is employed, because no existing (or planned) parallel digital computer has enough processors to assign a processor to each generator. In the next section we lay out the circuitry which allows us to effectively put a processor on each generator and solve the transient stability problem in a completely parallel fashion. This means that we will obtain one second of actual system response in about one milli-second of computing time, as opposed to minutes of computing time with current digital hardware.

3. Analog Simulation of Generator Response In this section we develop a method of integrating the dynamical equations of a power system using analog circuits. The overall circuit is developed from a small set of analog 'building block' circuits that perform the mathematical functions of multiplication, division, summing and taking a square root. These building blocks are combined with an analog zero order hold (ZOH) operation. The integration is done exactly as it would be done on a digital machine, but using a smaller set of mathematical functions. That is, we rewrite the differential equations for the dynamics of the power system as difference equations which can then be solved iteratively to produce the time response of the power system. The ZOH is necessary to hold values from a previous time step needed in the solution of the difference equations. This is essentially what happens in a digital computer, but there is an enormous difference in the speed at which the difference equations can be solved for the following reasons. First, a digital computer will have, at best, a small number of processors, relative to the number of differential equations of the power system. These processors will have to sequentially update the difference equations for all the generators. In the analog implementation, the difference equation for all generators are updated simultaneously since there is a dedicated 'integration circuit' for each generator. Second, with a digital computer the power flow equations have to be re-solved by iterative search several times for each update of the difference equations. Roughly half the cpu time required to update the dynamical equations by one time step is spent solving the power flow equations.

By contrast, in the analog implementation a separate power flow circuit solves all the algebraic equations for the power flow simultaneously in about 10 -6 sec. Using a digital computer it takes several minutes of cpu time to get 0.1 sec. of actual power system response. With the analog approach it takes about 10 -4 sec. of computing time to get 0.1 sec. system response. Thus, the increase in speed is four or five orders of magnitude. Equally important, the speed of solution of the analog scheme is independent of the size of the power system, while for digital solutions, whether by single processor or parallel processors, the time for solution increases with the size of the power system. For this paper we implemented the explicit Euler integration method. The time step of 0.01 seconds of real time is necessary for accuracy. A generator's power capacity together with its rotor inertia set an upper bound on the frequency of oscillation. For the example used in this paper the bound is 3 Hz, so that a time step of 0.01 sec. gives better than 30 time samples per cycle. The typical integretation strategy used in the utility industry is a predictor/estimator technique requiring two load flow solutions per integration step. This means we can either double our load flow circuitry for the same solve time, or double the solve time. Since the analog circuitry solves in roughly 100 microseconds, doubling this time is not a significant degradation in performance.

3.1. Developmentof Analog Swing Equation Solution The continuous time swing equation for a generator is 1

_

=

where Aw is the generator's electrical speed with respect to the nominal or synchronous electrical speed of the system, M is the inertia, Pm is the mechanical power delivered to the generator, P~ is the electrical power generated, and 6 is the generator's electrical angle with respect to the synchronous electrical angle of the system. Although we will use analog circuitry to solve these equations, we do not use the continuous equations but rather the discrete time difference equations:

Fast Solution of Nonlinear Equations Using Parallel Analog Hardware

At ..p

Acok+l = 2XaJk + - ~ (

(6)

rn -- Pe)

(7)

5k+1 = ~k + A t A w k + l ,

where k is the discrete time index and At is the time step. In the course of implementing these difference equations with analog devices, four different circuits were devised. We provide here a discussion of how and why this succession of circuits evolved. In this section two new blocks are introduced, division and square root. These circuits are each implemented with two multipliers and a capacitor to integrate current. Both circuits use one multiplier to generate stable feedback about the other multiplier. One differential input of the feedback multiplier is used to determine the error while the other input adjusts the sign of the feedback gain for stability. The forward multiplier computes the inverse operation (multiplication or squaring) the result of which is compared to the desired result (the dividend or square root). The feedback current is passed through a capacitor whose voltage is the output of the circuit. The square root circuit uses a diode in parallel with the capacitor to restrict the sign of the result. Figure 9 illustrates the division circuit, while Figure 10 the square root circuit with forced positive output. The swing equations, as given by equations (6) and (7), are not compatible with the analog devices used to solve the equations. The voltages in a power system are most easily visualized in polar coordinates as rotating vectors with magnitude and phase angle. The swing equation for each generator is written in terms of the angle of the internal voltage of the generator. For first swing analysis, the magnitude of the internal

z y/x

i

voltage is assumed constant. The angles of the various generators are generally measured relative to the angle of a particular generator, or some weighted average of all the generator angles of the system. This formulation leads to the explicit use of sine and cosine functions, functions that cannot easily be implemented with analog devices, and it is necessary to convert the differential equations to Cartesian form. Let Iv~l/o = e~ + 3f~,

where en = [Vn] cos0 and fn = Iv~I sin0, and then rewrite the swing equation in terms of e~ and f~, rather than the angle of the generator. We refer to en as the 'in-phase' voltage and fn as the 'quadrature' voltage. The swing equation is now compatible with the implementation of the power flow circuitry previously developed which uses the in-phase and quadrature voltages, to determine Pc, the electrical power consumed by the power system. This formulation is also compatible with the dynamic range and accuracy of the analog devices used to solve both the power flow equations and the swing equations. In a digital simulation, the in-phase and quadrature voltages are computed using formulas that require the sine and cosine of the angle differences between generator voltages. In a transient simulation these angle differences can easily be on the order of ?r/2 radians. To calculate the sine or cosine of such large angles accurately requires many terms of the Taylor series. To maintain speed and compactness the analog circuit computes sine and cosine functions only under very special circumstances. The first implementation is based on the computation of ~ given LX6, At, e, and f , where 2x(5 is the

..,dq

z=~ Y

Fig. 9. Divisioncircuitusing two multipliers.

145

Fig. 10. Positiveoutputsquareroot circuit.

146

Bond, Dorsey, Brooke, Magill and Tabler At 2

G1,2V2 i

G~2V£~)~

.2.J

Fig. 11. Differential machine speed update (common to all implementations).

difference between the machine's angle and the synchronous system angle. We note that we have dropped the bus subscript to simplify the notation. Once the in-phase voltage, e, is computed, f is determined by f = v/-Vff - e 2, where V 2 = e 2 + f2 is the constant magnitude of the generator internal voltage. The difference equations are

At 2 A&+~ = A6k + --~-(Pr~ - G ) ek+l

=

ek -

fk+l

~___ i V 2

fkAgk+l

--

2 1 ek_l_

The first equation, common to all implementations, is illustrated in Figure 11. This implementation has two weaknesses. First, circuit inaccuracies may cause e to be greater than V and the squareroot circuit will fail. Second, f will be both 1

positive and negative at various times in a given simulation, yet the equations yield only the magnitude of f. The second implementation is based on multiplying e + 3f by exp(3A6 ), where A~ = A w A t . Implementing this requires the computation of sin(AS) and cos(AS). The approximations sin(x) ~ x and cos(x) ,.~ x/1 - x 2 are based on the following rationale. While it is true that the angle of a generator can vary widely over the transient period, the angle is a continuous function of time, and if we make our update period At small enough the step to step variations in 6 are small and the approximations hold. In the case of a digital computer solution, reducing the size of At would be disastrous in terms of cpu time. For the analog implementation, reducing At is cost effective because of the complete parallelism of the computations. The difference equations for this approach, as illustrated in Figure 12, are: At 2 A6k+l = A6k + --~-(Pro - G ) ekq_ 1 ~- e k .~/1 -- A~2q_ 1 -- fk" A~k+l

fk+l = fk " ~ l -- A ~ + l + ek . ASk+l

t;

f:

A~

The third implementation builds on the second by including a computation to insure that e 2 + f2 remains equal to v 2 despite errors in the analog multiplications, summations, and ZOHs. This additional computation, yields the following difference equations: A t 2 .p,

e+

f+

Fig. 12, Computation of voltage updates for secondimplementation,

ek+ 1 =

ek "X/1 -- &5~+ 1 -- fk " 2X6k+l

Fast Solution of Nonlinear Equations Using Parallel Analog Hardware

and

147

become very negative, which insures stability and the correct sign of the output.

fk+l = fk .~/1 - AS~+ i + ek - ASk+i

Nk+~ = Ok+ 1 =

e2

fz

Nk+lek+ 1

and f~+1 =

Nk+ifk+1

The third implementation has too many multiplier circuits. A fourth implementation reduces the circuit's complexity by approximating cos(A6) with 1. This eliminates three multiplies and a squareroot and improves the analog circuit's overall accuracy despite the approximation. Again, we can make this approximation because the small step size, At, keeps A5 very small. The difference equations, for the fourth implementation are: At2 "R ASk+~ = ek+i =

ASk + - ~ - - ( .~ -- P~) ek

-

fk

"

ASk+~

and j%+l =

fk + ek • A5~+1

-/'V)~+I =

e2+1 _+_f2k + l

ek+ 1 =

4.

Simulation and Hardware Implementation

k + l -~- k + l

The difference equation formulation of the swing equations presented in the previous section was validated both by HSPICE simulation and discrete component implementation, using the case of one generator against an infinite bus. An infinite bus is a bus for which the voltage and angle stay constant no matter how much power is delivered to or demanded from the bus by the connecting transmission system. The mechanical equivalent is a rigid wall to which a spring and mass system (the rest of the power system) is attached. The use of an infinite bus eliminates the need to explicitly solve the power flow equations which have already been validated. The stability of the combination of the power flow and integration circuits is not an issue since they do not form a closed loop (the ZOH is designed to never close the loop). Hence, the infinite bus model provides a legitimate validation of the integration circuitry. The HSPICE simulation was performed to validate that the use of multipliers with some nonlinearity would not destroy the circuit's performance. The hardware implementation using analog adders and multipliers demonstrates that the circuit, at the breadboard level, can perform the computation at 1000 times real time.

.Nk+lek.t_ 1

and fk+l = N k + l f k + l

The final implementation, as shown in Figure 13, reduces the circuit's complexity by using an implicit (closed loop) circuit to normalize the generator terminal voltage. This eliminates both the squareroot and the division circuits, improving the analog circuit's overall accuracy. The accuracy gains come from the reduced number of multiplies in the forward computation path. The normalization circuit uses the magnitude error signal, V12 _ ek+12 _ f2k_bl, in current form to charge the capacitor to the appropriate voltage for scaling the output. The diode insures that the scaling voltage does not

^+

2-

) f~

Fig. 13. Computationof voltageupdatesfor final implementation.

148

Bond, Dorsey, Brooke, MagiU and TabIer 1.5

"6 ;> o

0.5.

O

0

-0.5

I

1

I

I

2 3 Real Time in Seconds

I

I

4

5

Fig, 14. Digital simulation of swing equation for one machine against an infinite bus.

The system of a classical generator connected to an infinite bus is modeled by the equations

£ce

= 1 ( P r o - Pc)

A5 = Ace Pe = GV2 -- G V cos(A6) - B V sin(Ae) where Ace is the difference between the generator's electrical speed and its rated speed, M is the generator's rotational inertia, Pm is the mechanical power delivered to the generator, P~ is the electrical power generated by the generator, A5 is the electrical phase angle of the generator's terminal voltage relative to the voltage angle of the infinite bus, G + 3B is the admittance of the transmission line connecting the generator and the infinite bus, and V is the magnitude of the generator's terminal volt: age. The parameter values chosen for the simulation are M = 0.00256 sec. 2, Pm = 0.27318

p.uMW, G + 3 B = 0.1-31.0p.u. f~-i a n d V = 1.03. p.u.V. The voltage at the infinite bus is chosen to be 1 / 0 ° p.u.V. To make the system oscillate the initial conditions were chosen to be: Ace(t = 0) = 0.0 and 6(t = 0) = 0.17453 rad. The baseline is five seconds of system response using a conventional transient stability program on a digital computer, as shown in Figure 14. The oscillation does not decay since the generator's damping is not included. This case is more than adequate for analyzing our experimental results. Figure 15 shows the HSPICE simulation results for the final circuit of section three using multipliers with 1% composite nonlinearity and a time step of 0.01 sec. of real time. Four Monte Carlo simulations are shown. The oscillations grow or shrink and do not have precisely the correct frequency. However, the results for the first four cycles are accurate enough to establish transient stability which only requires that the first swing be accurate.

Fast Solution of Nonlinear Equations Using Parallel Analog Hardware

149

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Figure 16 was captured from the hardware implementation. The results are better than for the HSPICE simulations. One reason is the ZOH scale factor was set by hand in the hardware while the Monte Carlo HSPICE runs were left with a scale factor of unity. Another factor was the multipliers were of a higher accuracy than their specification. The same time step of 0.01 sec. of real time used in the conventional digital computer simulation of the difference equation was used, but the total computing time is 5ms, because the ZOH clock period in the analog circuit was 10#s. Thus the analog circuit was able to simulate 5 seconds of system response in one thousandth of real time. The period of oscillation and the damping are correct. To prevent damping of the response an adjustable gain stage is placed before the ZOH for A5 to provide tuning. This tuning property can also be accomplished on VLSI designs as well, but was not used in the HSPICE simulations.

3_d

,

,

,

I

~.6

,

,

,

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of final implementation.

The hardware implementation circuit is shown in Figure 17. The multiplier block is a Burr Brown MPY534JD. Eleven multipliers, three initializing ZOHs, and one gain stage were used to implement the circuit. The first two multiplies compute Pe, the electrical power delivered by the generator. The next multiply determines A6k+l from the difference of Pm and Pe. Note that Awk+l is not available in the circuit. Since Awk+l is a scaled version of A~k+l, the circuit was simplified by removing the multiply and using A5 as a state instead. The next two multiplies compute the unnormalized value ofe+3f. The last six multiplies compute the normalized generator terminal voltage, e + 3f. Figure 18 shows a functional diagram of the initializing ZOH. The analog switches are Harris HI3201-5's and close when the switch input is a logic low. The initializing ZOHs operate in two modes. When the signal Init is logic high, the ZOH operates as expected. When Init is logic low, the ZOH passes the analog input, INITVALUE,to the (analog) signal OUPUT. These

150

Bond, Dorsey, Brooke, Magill and Tabler 1.5

et0

"6

0.5

0

-0.5

L

1

I

I

2 3 Real Time in Seconds

I

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Fig. 16. Simulation of one machine against an infinite bus using analog components.

specially designed ZOHs accept a 50 percent duty cycle clock and never form a short between INPUT and OUTPUT. This is important since connecting the inputs and the outputs of the analog circuit would cause the time step calculation to be corrupted. While the clock is low, the ZOHs input signal, INPUT, is used to charge the first capacitor. When the clock is high, the first capacitor is used to charge the second capacitor which is buffered to OUTPUT. The digital logic and the analog switches provide a 'break before make' feature to keep the input signals INITVALUE and INPUT signals from shorting together, and to keep INPUT from immediately affecting OUTPUT. Having demonstrated the concept of the hybrid power system computer, it is necessary to show that the circuits can be implemented in a form that meets the needs of the power system operator. The next section speaks to the issues of scalability, flexibility, compactness, and programmability at the VLSI level.

5.

Considerations of Implementation at the VLSI, Board, and System Levels

In this section we discuss issues involved with building a general purpose analog power system simulator. By general purpose we mean a simulator that 1) has a modular design that can accomodate a power system of any size by simply adding additional units, 2) has an adjustable topology, 3) is compact in size, and 4) can be reconfigured in terms of circuit parameters, initial conditions and topology from a digital computer. By a scalable design we mean a design that does not require any new intuition or design effort to increase the size of the system that can be simulated by the analog hardware. The simulator layout described below fits this idea, given the assumptions that the power system's interconnection is dominantly two dimensional, is relatively sparse, and that the stability property of the load flow solution mechanism remains similar.

Fast Solution of Nonlinear Equations Using Parallel Analog Hardware

151

At 2

61,2712

e,y2.Of

Aa7

e7

^+ el

) f,+ ~n~

Cl°ek Fig. 17.

Schematicof a hardwareimplementation.

The proposed simulator layout addresses the issue of adjustable topology by using a fixed topology for the basic simulator units which are themselves programable in function. Flexible line, bus, and generator units make it possible to interconnect the simulator into any two dimensional topological combination. Line units capable of making two adjoining bus units act as one unit and bus units capable of allowing transmission lines to cross without interaction are examples of flexiblility.

Compactness is addressed by using VLSI technology and minimizing interconnections, on the VLSI chips, between chips on a board, and among boards of the simulator. Using VLSI, large patches of a power system can be well interconnected on each chip. But chip to chip interconnections are affected by the limited number of pins on a package. Further the system size would be limited by the board size since the interconnection of boards is also a limiting factor. Here is another place where power system interconnection sparsity allows

152

Bond, Dorsey, Brooke, Magill and Tabler

ill

f +15 V Initial ~Value I-15 V Fig. 18. Circuitryof zero-order-holdwith initialization. reduced interconnection requirements for the analog units.

generator, and line unit's functionality, many more system topologies are possible with this fixed layout.

It is also required that the system's reconfiguration be accomplished without manual adjustment. The issue of digital reconfigurability has to do with the speed with which a system can be prepared for a specific simulation and its ultimate utility as an automated tool. The proposed design includes a digital communication scheme which interconnects all units in the simulator to solve the problem of parameter adjustment, topology modification, and state measurement.

Each line unit can be switched to be a 'null' line unit. Two buses connected by a null line unit operate as one bus. Both bus units sum up the incoming complex currents. Only one uses the overall sum to drive the load flow solution. This process can be extended to any number of contiguous buses to form a super bus. The properties of the super bus that allows for topological diversity are the additional number of transmission lines, the additional number of attachable generators, and the ability to break out of the rectangular bus interconnection scheme.

The proposed layout of the VLSI chips is rectangular and uniform in nature. Each bus unit has four line units and four generators to which it can connect. Each line unit connects to two bus units. Each generator can connect to one of the four adjoining buses. This layout by itself is overly restrictive in terms of the topologies that can be realized. By modifying the bus,

Each bus unit can be switched to be a 'cross-over' bus. This is only necessary if a power system cannot be represented on paper without transmission lines crossing. In general power systems do have lines which cross but don't interconnect.

Fast Solution of Nonlinear Equations Using Parallel Analog Hardware

Each generator unit can be switched to be a diagonal line unit. This flexibility allows for loops of an odd number of buses without making use of a super bus;. This also allows for a single bus to connect to all eight adjacent buses. Not immediately evident is the fact that this allows a subtle form of shifting a piece of the system's topology so that fewer bus elements are left: unused on a chip. A strongly interconnected part of the grid, without generator units, which is initially laid out in a rectangular grid can have some fraction of it shifted to one side or the other by exchanging vertically associated ties for diagonally associated ties. Thi.s shifting causes what would be two fixed shaped parts of the grid to change shapes to accomodate one another. Creative system modeling can also help with the topology. By replacing a transmission line with a series of transmission lines and intermediate buses with zero loads, a transmission line can reach further than the next bus.

gine behavior. The dynamics of the engine are quite fast, requiring a small integration time step to assure stability of the numerical solutions. Accurate solution may require 10,000 integration steps per second. Since the simplest complete engine model has 16 state variables, real time simulation is very difficult on a computer small enough to be used for onboard control. Thus, the analog computing scheme proposed in this paper offers the proper mix of speed and compactness for aircraft control. At the present time we have constructed a simulator for a simplified compression system [4] consisting of a compressor, followed by a duct, which leads to a plenum and a more complete engine model. These results have been reported in [ 10]. For the simple compression system, the results from the analog simulation compare favorably with the the digital simulation in [5]. Both simulations run at ten times real time with good accuracy. We are currently constructing a full engine simulator and will report those results in the near future.

7. 6.

153

VLSI Multiplier Issues

Simplified Compression System Simulator

In a study of the dynamics of aircraft gas turbine engines, two important phenomena appear, known as rotating stall and surge. Rotating stall is a very inefficient operating condition in which many of the blades in the engine's compressor are stalled. Surge is a related condition which is characterized by a limit cycle producing large oscillations in the pressures and mass flow rates inside the engine. Surge can cause catasrophic failure, or at the very least, 'blow out' of the flame in the combustion chamber. An analysis of engine performance reveals that the most efficient operating condition is close to the boundary beyond which stall and surge will occur. Hence, recent work in engine technology has been aimed at deriving mathematical models which describe the stall and surge dynamics (as well as other engine behavior) and to design stabilizing controllers which guarantee that the most efficient operating conditions can be safely maintained. The design of these controllers hinges on the real time and better than real time simulation of the engine dynamics. Real time simulation has been achieved for simplistic engine models but not for complete engine dynamics, even on large computers, due to the complexity of the nonlinear differential equations which describe en-

The above work relies heavily on the existence of a compact and accurate multiplier implemented in VLSI. Such a multiplier has been developed, fabricated, and tested. The multiplier is based on a linear transconductance cell, and has differential inputs and a current output [6], [7]. The design differs from that in [7] in that cascaded current mirrors are used for improved current tracking. Also, cascaded current sources have been employed to allow a wider voltage swing range. Figure 19 is a photograph of the multiplier. To achieve the necessary precision in the fabricated multipliers, EEPROMs are used as pre-emphasis devices [8]. The effectiveness of the approach has been explored [9]. The EEPROM devices make it possible to use very compact multiplier cells which otherwise would not have the necessary accuracy. The HSPICE simulations included in the paper used a polynomial source which models the inaccuracies of the fabricated multipliers. The model is as follows. X

=

X..V--X_

X

:

aO + a l x -V a 2 x 2 -V a3 x 3

y = y+-y_ y = bo+bly+b2y ~+b3y ~ z

=

xy+co

154

Bond, Dorsey, Brooke, Magill and Tabler

Fig. 19. Photographof transconductancemultiplier.

where x+, x_, y+, and y_ are the differential inputs, a0, b0, c0, a2, b2, a3, and b3 are uniformly distributed random variables with a mean of zero, and al and bl are uniformly distributed random variables with a mean of one. The maximum error of z - x y was determined by setting y to ±1 while sweeping x from - 1 to 1. The magnitude of the random variation was set to fit the maximum error seen in the fabricated multipliers.

8.

Conclusions

The general purpose digital computer is such a dominant feature of the landscape of computing technology that it is very difficult to focus on other less imposing features. In this paper we have tried to do just that, presenting an alternative approach that uses analog arithmetic units to implement, in a parallel fashion, the computation of the solution of the power flow equations, the simulation of a three state model of an electric power generator, and the simulation of a simplified jet aircraft engine compressor. Using simultaneous analog computations, we were able to solve and simulate faster than general purpose digital machines. We also outlined a simple general purpose unit for use in simulating power system responses. The power of our approach is complete parallelism and it works remarkably well for specific applications. For the applications we have presented here the technology is cost effective. In the case of power systems,

the proposed computing strategy could be built for far less than the network of digital machines it would take to do the same task at the same speed. In the case of jet aircraft engine control, the cost of the design would be recovered through volume, that is by using the controller on thousands of jet engines. In addition the size and weight of a digital computer that could accomplish the same task would be prohibitive. The landscape that lies between the general purpose digital machine and the specialized analog machines described in this paper is largely unexplored. One obvious question is: how general can the specialzed machines be made? The answer to this question is far from clear, but worth investigating. It may be possible to identify classes of problems that can all be solved by a somewhat more flexible interconnection scheme than that presented here. We do not currently have the answer to this problem, but we are beginning to investigate it: Another area that surely deserves attention are hybrid designs where the digital portion plays a bigger role than it does in the power simulation example presented here. For many applications digital computation may still be the best answer, but there may be pieces of the computational problem that can be handled more effectively by analog circuitry. Identifying these problems, and designing the analog circuitry to be as modular and general as possible are worthy research topics. Our next research steps include investigating the fabrication of VLSI building blocks for simulation of

Fast S o l u t i o n of N o n l i n e a r E q u a t i o n s Using Parallel A n a l o g H a r d w a r e

155

power system response to contingencies, designing a circuit to solve economic dispatch of electric power generation, building jet engine simulators, and for the purposes of nonlinear system simulation designing a 'cell' which incorporates some set of flexibly interconnected nonlinear arithmetic units coupled with a Runge-Kutta step computation and a ZOH. The pursuit of these initiatives are a few of the neccesary steps in the development of this technology as an engineering design and application tool.

References Tabler, J., Brooke, M., Dorsey, J. and Aryani,S., "Solutionof the Powerflow EquationsUsing ParallelAnalogComputing," submitted to InternationalJournal of ComputingSimulation.

John Bond received the BSEE and MSEE degrees in Electrical Engineering from the Georgia Institute of Technology in 1986 and 1990 respectively. Between 1986 and 1989 he also worked at the Georgia Tech Research Institute in the area of radar signal processing. He is currently pursuing his doctoral work at Georgia Tech in the area of analog design with application to power systems.

Stagg, Glenn W. and El-Abiad,Ahmed H., Computer Methods in Power SystemAnalysis,McGraw-HillBook Company, New York, NY, 1968, pp. I-2. Elgerd, Olle I., ElectricEnergySystemsTheory,An Introduction, 2nd Edition, McGraw-HillBook Company,New York, NY, 1982, p. 61. Greitzer, E. M., "Surgeand RotatingStall in AxialFlowCompressors, Part 1: Theoretical Compression System Model," ASME Journal of EngineeringPower, vol. 98, pp. 190--198, April 1976. Greitzer, E. M., "Surge and Rotating Stall in Axial Flow Compressors, Part 2: ExperimentalResults and Comparison with Theory," ASME Journal of EngineeringPower, vol. 98, pp. 199-217, April 1976. 6. Wang,Z. and Guggenbuhl,W., "A Voltage-ControllableLinear MOS TransconductorUsingBias OffsetTechnique,"IEEE Journal of Solid-StateCircuits,vol. 25, no. 1, Februrary1990. 7. Wang, Z., "A CMOS Four-QuadrantAnalog Multiplierwith Single-EndedVoltageOutputand ImprovedTemperaturePerformance,"1EEEJournalof Solid-StateCircuits,vol.26, no. 9, September 1991.

John E Dorsey received his B.A. in creative writing in 1964. After returning from military service in 1967, he entered Michigan State University and received an M.S. in Systems Science in 1969. He worked in both the aerospace and automobile industries for seven years, before returning to Michigan State to obtain his PhD in 1980. Since 1980 be has been a member of the faculty of the Department of Electrical and Computer Engineering at The Georgia Institute of Technology, where he holds the rank of professor. His research interests include the simulation, modeling and control of power systems, with a peripheral interest in control theory.

8. Thomsen, A. and Brooke, M., "A Floating-gateMOSFET with TunnelingInjectorFabricatedUsing a Standard Doublepolysilicon CMOS Process," IEEE Electron Device Letters, vol. 12, no. 3, pp. 111-113, March 1991. 9. Thomsen, A. and Brooke, M., "A ProgrammablePiece Wise LinearLarge SignalCMOSAmplifier,"to appearIEEEin Journal of Solid-StateCircuits. 10. Magill, J., Bond, J., Dorsey, J. and Brooke, M., "Application of Analog Computingto Real Time Simulationof Stall and Surge Dynamics,"AIAA/ASME/SAE/IEE29th Joint Propulsion Conference,paper no. AIAA-93-2231,June 1993, Monterey, CA.

Martin A. Brooke received the B.E. (Elect.) degree (1st Class Honors) from Auckland University in New Zealand in

156

Bond, Dorsey, Brooke, Magill and Tabler

1981. He received the M.S. and Ph.D in Electrical Engineering from the University of Southern California in 1984 and 1988 respectively. His doctoral research focused on reconfigurable analog and digital integrated circuit design. He is currently the Analog Devices Career Development Assistant Professor of Electrical and Computer Engineering at Georgia Institute of Technology. He is developing electronically adjustable parallel analog circuit building blocks that achieve high levels of performance and fault tolerance. Professor Brooke won the only 1990 NSF Research Initiation Award given in the analog signal processing area. Current projects include development of adaptive neural network and analog signal processor integrated circuits.

a Master of Science in Electrical Engineering in 1992 from The Georgia Institute of Technology, where he is presently pursuing his doctoral studies. His primarty interests are the control and simulation of aircraft. He has a U.S. Patent Pending on the Wind Driven Dynamic Model Manipulator for Wind Tunnels. His research focuses on control of manipulators for wind tunnel models.

John "Fabler received the BSEE and MSEE in Electrical En-

John Magill, a native of Chattanooga, TN, received a Bachelor of Aerospace Engineering from Georgia Tech in 1991, and

gineering from the Georgia Institute of Technology in 1989 and 1990, respectively. He is presently pursuing his doctoral studies at Georgia Tech in the area of analog design, concentrating on the design of high speed precision analog signal processing.