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IEEE ELECTRON DEVICE LETTERS, VOL. 23, NO. 2, FEBRUARY 2002
Ferroelectric DRAM (FEDRAM) FET With Metal/SrBi2Ta2O9/SiN/Si Gate Structure Kwang-Ho Kim, Member, IEEE, Jin-Ping Han, Student Member, IEEE, Soon-Won Jung, and Tso-Ping Ma, Fellow, IEEE
Abstract—N-channel ferroelectric dynamic random access memory (FEDRAM) FETs with SrBi2 Ta2 O9 /SiN/Si structure were fabricated and characterized. The estimated switching time ( sw ) of the fabricated FET, measured at applied electric field of 376 kV/cm, was less than 50 ns, which could be significantly reduced upon scaling. Its remnant polarization (2 ) was measured to be about 1.5 C/cm2 , which is more than one order of magnitude higher than that required for FEDRAM operation. The stored information retains more than three orders of magnitude of on/off ratio up to three days at room temperature, with little fatigue after 1011 switching cycles.
Fig. 1. Cross-sectional view of the fabricated n-channel FEDRAM FET using the metal/SBT/nitride/Si gate structure.
Index Terms—Ferroelectric dynamic random access memory (FEDRAM) FET, retention, SiN buffer, SrBi2 Ta2 O9 , switching.
I. INTRODUCTION
T
HE ferroelectric-gate field-effect transistor (FET) structure has been studied for over three decades as a promising candidate for nonvolatile memory [1]–[4]. In principle, such a memory device could be the building block of an ideal memory technology that offers random access, high speed, low power, high density, and nonvolatility. In practice however, so far, none of the reported ferroelectric memory transistors has achieved a memory retention time of more than a few days due to the depolarization field and the gate leakage current. More recently, the concept of a capacitorless ferroelectric DRAM (FEDRAM) [5]–[7] was introduced to get around the problem of its finite retention time. In comparison with nonvolatile semiconductor memory, the FEDRAM can tolerate significant amounts of gate leakage current and depolarization field, owing to its ability to be refreshed. In comparison with the conventional DRAM, it has much longer retention time, simpler circuit design, and higher integration density because of the elimination of the storage capacitor. Previously, the feasibility of the FEDRAM concept was demonstrated by means of a metal–ferroelectric–insulator–semiconductor (MFIS) capacitor [5]. In this paper, we report the results of a set of FEDRAM transistors with SrBi Ta O as the ferroelectric gate material and a record-thin SiN as the buffer layer ( 3 nm EOT). Manuscript received October 3, 2001; revised November 6, 2001. The review of this letter was arranged by S. Kawamura. K.-H. Kim is with the Department of Electrical Engineering, Yale University, New Haven, CT 06520-8284 USA, on leave from the Department of Semiconductor Engineering, Cheongju University, Cheongju, Chungbuk, 360-764, Korea (e-mail:
[email protected]). J.-P. Han and T.-P. Ma are with the Department of Electrical Engineering, Yale University, New Haven, CT 06520-8284 USA. S.-W. Jung is with the Department of Semiconductor Engineering, Cheongju University, Cheongju, Chungbuk, 360-764, Korea. Publisher Item Identifier S 0741-3106(02)01488-X.
Fig. 2. Ferroelectric switching behavior of the FETs measured as the voltage across a 10 load resistor at room temperature. The amplitude, pulse width, and rise time were 376 kV/cm, 1 s, and 50 ns, respectively. The solid curve is the displacement current for the gate when it was undergoing the switching transient, while the dotted one is the charging current for the nonswitching gate capacitor only.
II. EXPERIMENTS AND RESULTS A cross-sectional view of the fabricated n-channel FEDRAM FET used in this study is shown in Fig. 1. Boron doped p-type cm silicon (100) oriented wafers with resistivities of 21–24 were used as substrates. The source and drain regions were formed by P O diffusion for 1 h with 1- m-thick SiO as the diffusion mask. The ferroelectric SBT film was deposited by the MOD method, and the silicon nitride buffer layer was deposited by the JVD method [8]. The thicknesses of the SBT and the silicon nitride films were about 260 nm and 6 nm, respectively. The details of the SBT/nitride formation process and properties of the SBT/nitride/Si structure were described elsewhere [9]. The gate electrode was made of e-beam evaporated Pt, while the source and drain contacts were made of thermally evaporated Al. The channel length and width were 50 m and 500 m, respectively. Some of the samples were postmetal an95 N at 400 C for nealed (PMA) in forming gas 5 H 30 min, and the properties to be reported in the following are practically unaffected by the forming gas anneal. Fig. 2 shows the switching signals that verify the ferroelectric switching behavior of these devices, measured as the voltage across a 10 load resistor at room temperature, although only one part of polar response is shown here. The applied pulse sequence consisted of one negative and two positive pulses fol-
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KIM et al.: FERROELECTRIC DRAM (FEDRAM) FET
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Fig. 3. (Upper curve) ”On”-state drain current and (lower curve) “off”-state drain current for the fabricated FEDRAM FET as a function of time after switching.
lowed by two negative pulses, as shown in the inset. The amplitude, pulse width, and rise time were 376 kV/cm, 1 s, and 50 ns, respectively. The solid curve is the displacement current for the gate when it is undergoing the switching transient (i.e., the current is the sum of both the switching current and the normal gate capacitor charging current), while the dotted one is the charging current for the nonswitching gate capacitor only. Therefore, the switching current of the polarization reversal transient can be obtained by subtracting the dotted curve from the solid curve. for this large-area device is The extracted switching time less than 50 ns. Here, the switching time is defined as the time required to switch 90% of the polarization [10]. The ferroelectric polarization (that is, 2 ), obtained by numerical integration of this current difference, is around 1.5 C/cm , which is consistent with the 2 obtained from – hysteresis curves measured on MFIS capacitors and is more than one order of magnitude higher than the minimum polarization necessary for the FEDRAM transistor [5], [6]. From this measurement, the relative dielectric constant of the SBT was estimated to be 45, which is consistent with that obtained from the – curves for MFIS capacitor structures. It is worth noting that the relative dielectric constant of the SBT film is significantly smaller than those (typically 150–300) of SBT in metal–ferroelectric–metal (MFM) structures [11], probably due to the incomplete crystallization of the SBT film grown on an amorphous SiN buffer layer. A low dielectric constant is desirable for the ferroelectric film in the FEDRAM structure in order to minimize voltage drop across the buffer layer, and to improve the switching speed. Fig. 3 shows the “on”-state drain current (upper curve) and the “off”-state drain current (lower curve) of the fabricated FEDRAM FET as a function of time after switching. The sensing voltage and the programming voltage applied to the gate of the FET were 1.5 V and 10 V, respectively. The drain voltage of the FET was also set at 1.5 V. One can see that the initial on/off ratio of drain current is more than five orders of magnitude, and even after three days (2.6 10 s, the stored information retained more than three orders of magnitude of on/off ratio. Such a retention time is longer than most ferroelectric-gate FETs reported in the literature [3], [12], probably due to the smaller gate leakage currents and/or lower trapping probabilities of the gate stacks of the FEDRAM transistors used in this study. characteristics of the Fig. 4 shows the subthreshold – FEDRAM FET before and after 10 switching cycles at a sine wave frequency of 1 MHz with a 20 V of peak-to-peak voltage.
Fig. 4. Subthreshold I –V characteristics for the FEDRAM FET before and after 10 switching cycles at a sine wave frequency of 1 MHz with a 20 V of peak-to-peak voltage. The inset shows the capacitance–voltage (C –V ) curves for a capacitor next to the FET before and after the same cycling test.
The inset shows the capacitance–voltage – curves for a capacitor next to the FET before and after the same cycling test. One can see that the subthreshold – characteristics before and after cycling remained almost the same, except for some increased off-state current, due probably to the stress-induced leakage current (SILC). The – in the inset indicates some net electron trapping effect after cycling. It should be noted that although the results obtained in this study are based on large-size transistors to demonstrate the FEDRAM concept, it should be possible to make deep-submicron FEDRAM devices as the scaling requirements are very similar to those of conventional CMOS technology. The only possible complication is in the scaling of the ferroelectric film. Here it is worth mentioning that functioning ferroelectric films as thin as 0.9 nm have been experimentally demonstrated [13] and recent theoretical work has predicted a ferroelectric limit down to one unit cell thickness [14]. In addition, lateral dimensions of functioning ferroelectric-gate capacitors as small as 70 nm have also been reported [15]. When the FEDRAM transistors are scaled down to sizes comparable to the CMOS technology, operating voltages of 1.5 V or lower can be envisioned. III. CONCLUSION FEDRAM transistors with high-speed switching, long retention, and good fatigue resistance were fabricated using a SrBi Ta O /SiN/Si gate structure where the SiN buffer layer was only 3 nm in EOT. These transistors could withstand realistic thermal budgets as well as forming-gas anneal conditions that are compatible with CMOS processes. The estimated switching time of the fabricated FET, measured at an applied electric field of 376 kV/cm, was less than 50 ns. The estimated from this measurement, about 1.5 C/cm , polarization 2 is more than one order of magnitude higher than that required for FEDRAM operation. The relative dielectric constant of the SBT was estimated to be 45, which is significantly smaller than those typical of SBT in MFM structures, and is desirable for FEDRAM technology. The stored information retained more than 3 orders of magnitude of on/off ratio up to three days at room temperature. The – characteristics remained largely
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unchanged after 10 cycles of switching events. Since the FEDRAM technology utilizes nondestructive read operation, the 10 cycles of endurance is more than adequate for most, if not all, of its applications.
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