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processing_system7_0 DDR

DDR

FIXED_IO

FIXED_IO USBIND_0 M_AXI_GP0_ACLK M_AXI_GP0 FCLK_CLK0

hailstone

FCLK_RESET0_N s_axi_hstream_io

ZYNQ7 Processing System

in_data out_data ap_clk ap_rst_n

Hailstone (Pre-Production)

rst_ps7_0_100M

ps7_0_axi_periph

slowest_sync_clk

mb_reset S00_AXI

ext_reset_in

bus_struct_reset[0:0]

aux_reset_in

peripheral_reset[0:0]

ACLK ARESETN mb_debug_sys_rst

interconnect_aresetn[0:0] S00_ACLK

dcm_locked

peripheral_aresetn[0:0]

M00_AXI S00_ARESETN M01_AXI

Processor System Reset

M00_ACLK M00_ARESETN

hailstone_dma

M01_ACLK M_AXI_SG

M01_ARESETN

M_AXI_MM2S S_AXI_LITE M_AXI_S2MM S_AXIS_S2MM M_AXIS_MM2S S_AXIS_STS M_AXIS_CNTRL s_axi_lite_aclk mm2s_prmry_reset_out_n m_axi_sg_aclk mm2s_cntrl_reset_out_n m_axi_mm2s_aclk s2mm_prmry_reset_out_n m_axi_s2mm_aclk s2mm_sts_reset_out_n axi_resetn mm2s_introut s2mm_introut

AXI Direct Memory Access

AXI Interconnect