Fully CMOS Memristor Based Chaotic Circuit - Radioengineering

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S. C. YENER, H. H. KUNTMAN, FULLY CMOS MEMRISTOR BASED CHAOTIC CIRCUIT

Fully CMOS Memristor Based Chaotic Circuit Şuayb Çağrı YENER 1, H. Hakan KUNTMAN2 1

2

Dept. of Electrical and Electronics Engineering, Sakarya University, Sakarya, Turkey Dept. of Electronics and Communication Engineering, Istanbul Technical University, Istanbul, Turkey [email protected], [email protected]

Abstract. This paper demonstrates the design of a fully CMOS chaotic circuit consisting of only DDCC based memristor and inductance simulator. Our design is composed of these active blocks using CMOS 0.18 µm process technology with symmetric ±1.25 V supply voltages. A new single DDCC+ based topology is used as the inductance simulator. Simulation results verify that the design proposed satisfies both memristor properties and the chaotic behavior of the circuit. Simulations performed illustrate the success of the proposed design for the realization of CMOS based chaotic applications.

Keywords Memristor, CMOS design, DDCC, Chua's circuit, chaotic oscillators.

1. Introduction In 1971, Leon Chua theoretically claimed that the memristor is the fourth circuit element besides the three well-known circuit elements; namely, resistor, capacitor and inductor [1]. For a long time, it remained just as a theoretical element and rarely appeared in the literature because of having no simple and practical realization. In 2008, a group of researchers from HP laboratories announced the fabrication of a physical implementation behaving as a memristor [2]. Its prototype is based on a TiO2 thin film containing doped and un-doped regions between two metal contacts at nanometer scale. This implementation, realized by HP researchers, has attracted significant attention. It is expected that memristors can be applied and provide new additional features to analog circuits. Various analog and chaotic applications of memristor to analog, chaotic and synaptic circuits are studied in the literature [3]-[11]. Despite large-scale interest on memristor and emerging many studies, no commercially available memristor exists yet. In this sense, a proper physical implementation representing the memristor behavior is of great importance from the point of view of real-world circuit design. SPICE macromodels and memristor emulators exhib-

iting memristor-like behavior are presented in the literature [12]-[22]. SPICE models are useful for modeling characteristics of the memristor, but they have not been an alternative in practical realizations. Emulators can represent the behavior of memristor in a restricted extent and they can be applicable on some real applications. Some inductorless implementations of Chua’s circuit have been presented in the literature [23], [24]. Implementation approach of CMOS memristor employing Differential Difference Current Conveyor (DDCC) based blocks is presented previously [8]. In this paper, we propose a fully CMOS DDCC based scheme to realize memristor. It is pointed out that, this is an appropriate design for circuit. Also physical charge-flux characteristic of memristor. Memristor is constructed to behave convenient to the cubic memristor definition. Beyond our prior work, in this implementation appropriate chaotic behavior is obtained by using fully CMOS DDCC based a new CMOS based inductance simulator is used. Along with that, supply voltages and process technology is selected properly to current CMOS processes. The paper is structured as follows: Section 2, which follows this introduction, summarizes the nonlinear cubic modeling of memristor. Section 3 includes the memristorbased Chua's circuit along with its dynamics with MATLAB simulations. In Section 4 we present the detailed design steps of our DDCC memristor-based chaotic circuit. Also in this section DDCC based inductance simulator is introduced. In Section 5 we present characteristics of memristor-based Chua’s circuit. This section is devoted to the demonstrations of SPICE simulations based on the proposed design. Finally, the conclusions of this work are given in the sixth section.

2. Modeling of Memristor with Cubic Nonlinearity Memristor can be defined with two types of nonlinear constitute relation between the device voltage and current: v  M qi ,

(1)

i  W   v

(2)

where M(q) and W(φ) are nonlinear functions which are

RADIOENGINEERING, VOL. 23, NO. 4, DECEMBER 2014

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called memristance and memductance respectively and they are defined by: d  q  M q  , (3) dq

W   

dq   d

.

(4)

The memristor designed in this work is a flux controlled memristor described by the relation in (2). The relation between the terminal voltage v(t) and the terminal current i(t) of the memristor is obtained by: i t  

dq dq d dq   v  t   W   t   v  t  . dt d dt d

(5)

Nonlinear resistor in Chua's circuit is defined by Zhong with cubic nonlinearity. It has been revealed that, all features of the circuit are captured correctly by this definition [25]. The q(t) - φ(t) function of memristor with cubic nonlinearity is used for implementation of chaotic circuits [26]. The cubic polynomial definition of memristor is defined as follows: q       3 .

(6)

Thus, the memductance function is given by: W   

dq    3 2 . d

(7)

Considering (7) and the flux-voltage relation, we get (8). Our definition in this work, is based this relation. i  t     3 

  v t  dt   v t  . 2

(8)

The memristor circuit introduced employs only DDCC based sub blocks such as mainly integrator, squarer, multiplier and summer. Designs of these active blocks are given in the following sections.

3. Chaos in Memristor-Based Chua’s Circuit Memristor-based Chua’s circuit used in this work is shown in Fig. 1.

+

C2

d `  t 

 `vC1  t  dt dì L L  `vC2  t  dt (9) d`vC1  t  1  C1 `vC  t   `vC1  t   W  `  t   `vC1  t  dt R 2 d`vC2  t  1  C2 `vC  t   `vC2  t   ìL  t  dt R 1









where W(φ(t)) is memristor memductance and is defined by (7). By considering α, β and other circuit parameter values from [25], [26] this unscaled system gives unrealistic currents (up to hundred amps) and voltages (above kilo volts). In traditional op-amp based implementations currents and voltages are scaled about at mA and ten-volt levels [25], [26]. For our CMOS design we need to reduce much lower than these levels. Rescaled current and voltages are defined as: 1   t   `  t   11 vC1  t   `v  t    C1 (10) 11 vC2  t   v t `     C2 11 iL  t   ì  t   L The following set of equations is obtained as our rescaled system. d  t  dt diL  t 



vC1  t 



vC2  t 

 dt L (11) dvC1  t  1  vC2  t   vC1  t   2       3  t   vC1  t  dt C1  R  dvC2  t  1  vC1  t   vC2  t       iL  t  dt C2  R 

where β is also rescaled with

R

L

The dynamical state equations of memristor-based Chua’s circuit can be described by

C1

+

M

Fig. 1. Memristor-based Chua’s circuit.

Note that mathematical background of the memristorbased Chua’s circuit illustrated in Fig. 1 is studied earlier in [26]. We apply the DDCC based CMOS circuit proposed in our work to the realization of the Chua’s circuit.

  `

1

2

(12)

Let δ = 1.6 kΩ × 47 nF = 7.52×10-5, C1 = 7.2 nF, C2 = 70 nF, L = 18 mH, R = 1.97 kΩ. α = -0.662 × 10-3 and β = 18.75 × 10-3. Initial values are φ(0) = 0, iL(0) = 0, vC1(0) = 0.01, vC2(0) = 0.01. This parameter set will be used as design basis synthesizing of the CMOS circuit. The bifurcation diagram of the system with respect to R is shown in Fig. 2. R is very important to create the chaotic behavior. Time domain waveforms and chaotic

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phase portraits from MATLAB simulations are shown in Fig. 3 and Fig. 4, respectively.

10

Y

In a recent work, it has been shown that the type of singularities may be an indication of chaos [27]. Following up in this direction, it may be useful to note that the system in (11) has a single singularity on the origin, i.e. vC1 = vC2 = iL = 0 unlike conventional Chua’s system; thus we think that a detailed study of the system from the perspective introduced in [27] would be useful, while being beyond this paper’s scope.

6 1750

1850

1900

1950 R

2000

2050

2100

2150

-4

0.1

1 iL (V)

2

 (Wb)

1800

Fig. 2. The bifurcation diagram with respect to R.

0.2

0

x 10

0

-1

-0.1

-0.2 0

0.005

0.01 t (s)

0.015

-2 0

0.02

0.06

0.1

0.03 vC2 (V)

0.2

vC1 (V)

8

0

-0.1

0.005

0.01 t (s)

0.015

0.02

0.005

0.01 t (s)

0.015

0.02

0.2

0

-0.03

-0.2 0

0.005

0.01 t (s)

0.015

-0.06 0

0.02

Fig. 3. Time domain waveforms of chaotic signals from MATLAB simulations. -4

2

x 10

0.2

0.1 vC1 (V)

iL (A)

1

0

-0.1

-1

-0.1

0  (Wb)

0.1

-0.2 -0.2

0.2

0.06

0.2

0.03

0.1 vC1 (V)

vC2 (V)

-2 -0.2

0

-0.06 -0.2

0  (Wb)

0.1

-1

0 iL (A)

1

0 vC1 (V)

0.1

0

-0.1

0  (Wb)

0.1

-0.2 -2

0.2

0.06

0.03

0.03 vC2 (V)

0.06

0

-0.03

-0.06 -2

-0.1

-0.1

-0.03

vC2 (V)

0

2 -4

x 10

0

-0.03

-1

0 iL (A)

1

2

-0.06 -0.2

-0.1

-4

x 10

Fig. 4. Phase portraits from the MATLAB simulations.

0.2


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4. Design of Fully CMOS MemristorBased Chaotic Circuit 4.1 DDCC DDCC is a 5-terminal active circuit block. Circuit symbol of DDCC is given in Fig. 5. Its terminal characteristics can be defined by a hybrid matrix giving the output of the five ports in terms of their corresponding inputs as shown in (13) [28].

Four main CMOS stages are used in our memristor design. The first block works as an integrator. Also this block behaves as a buffer and it is used to avoid loading effect and insulate the current from the other stages. The output of the first block is connected both of the inputs of the multiplier and here it is the square of the voltage. The next block is summing block which also incorporates coefficients defined in (8) to the process. This block also makes current-voltage conversion in order to produce the inputs of the multiplier in voltages form. Finally, the current of our active memristor is generated after the output of this last multiplier block.

4.3 Sub-blocks of Memristor 4.3.1 Integrator DDCC based integrator is shown in Fig. 7. For RX = ∞ the output characteristics of the circuit can be derived as follows: V V V VO  1 2 3 . (14) sRC

Fig. 5. Circuit symbol of DDCC.

 iY 1   0 0 i   0 0  Y2    iY 3    0 0     v X  1 1  iZ   0 0

0 0 0 1 0

0   vY 1  0 0  vY 2  0 0   vY 3    0 0   iX  1 0   iZ  0

(13)

Here ± (plus or minus) sign indicates whether DDCC is non-inverting or inverting type denoted as DDCC+ or DDCC- respectively.

V1

Y1

V2

Y2

V3

Y3

DDCC+ Z

VO C

X

+

RX

R Fig. 7. DDCC based integrator.

Only C is used at the output of the integrator. Its parameters are defined as R = 1.6 kΩ and C = 47 nF.

4.2 Block Diagram of Proposed DDCC Based Memristor

4.3.2 Multiplier

The proposed principle block diagram of memristor constructed employing only CMOS DDCC based sub blocks is shown in Fig. 6.

In order to obtain DDCC based multiplier, the combination of two DDCC differential squarer is used [28]. The schematic of differential squarer is given in Fig. 8. V1

I1

VG V3

I2

Y1 Y2

DDCC+

X Y3

Z IO

Fig. 8. DDCC based differential squarer.

In triode region, drain current of a MOS transistor can be expressed as follows: 2  , I D  K  2 VGS  VT  VDS  VDS

K

Fig. 6. Principle block diagram of proposed memristor implementation.

1 W  Cox . 2 L

(15) (16)

Considering the voltage relation of DDCC between X-Y inputs and supposing the transistors are well matched, the output current IO can be derived as

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IO    I1  I2 

Y1

V1

  V V V V   V V     K 2 VG  1 3 VT V1  1 3   V1  1 3   2 2   2     

Y2

2

2   V V V V   V V    K 2 VG  1 3 VT V3  1 3   V3  1 3   2 2   2     



Y3

V1 Fig. 10. DDCC based buffer.

If a DDCC- is used here, the output current would be obtained as follows K 2 2 V1  V3    K s V1  V3  . 2

(18)

DDCC based multiplier [28] can be realized employing two squarers as shown in Fig. 9. Summing the outputs of both squarers, the output characteristics of the multiplier is obtained as given in (19). V1 VG V3

Y1 MM1

Y2

MM2

X

Z

X

(17)

K 2 2 V1 V3   Ks V1 V3  2

IO  

DDCC+

4.3.4 Inverter

As can be seen from Fig. 9 we need an inverter at one of the inputs of the each DDCC multiplier. To obtain an inverter employing DDCC, simply it can be obtained by using the Y2 terminal as input and Z terminal as output. However, this topology is proper if the following stage has buffered input(s). Otherwise, an additional buffer will be needed. As a simpler form, DDCC based inverting buffer shown in Fig. 11 is used in our design.

DDCCZ

Y3 IO

V1

Y1 MM3

Y2

MM4

X Y3

VG -V3

DDCC+ Z

Fig. 9. DDCC multiplier.

K 2 2 K I O   V1  V3   V1  V3    2 KV1V3  K M V1V3 (19) 2 2  

where KM is the multiplying coefficient of the multiplier. Aspect ratios of MOS transistor used at inputs of the multiplier stage are W/L = 40 µm / 1 µm and W/L = 10 µm / 1 µm for multiplier 1 and multiplier 2, respectively. Gate voltages of these transistors are defined as VG = 0.75 V and drain currents are decreased as soon as possible preserving required multiplying situation. It is clear from Fig. 9 that the outputs of multipliers are current. The output current of multiplier 2 corresponds current of memristor. However current at the output of memristor 1 will be converted to voltage as stated in description of the summer block. 4.3.3 Buffer

DDCC has buffered inputs with very high gate impedances. Normally there is no need to additional buffer stages. However, DDCC multipliers have additional draininput MOS transistors. So, DDCC based buffers are used at the input stages of these multipliers as shown in Fig. 10.

Fig. 11. DDCC based inverting buffer.

4.3.5 Summer

A DDCC is a kind of differential summer circuit due to its characteristic. As the DDCC based summing circuit in Fig. 6, two-input DDCC based topology is used as shown in Fig. 12. In this scheme, by considering differentiated inputs which are applied to Y1 and Y2, the output voltage of the circuit is as follows: VO  I1 V1

R1 VD

V2

RZ V1  V2  . RX

(20)

Y1 DDCC+ Y2 Z Y3 X

VO RZ

RX Fig. 12. DDCC based summer topology used in the memristor design.

V1 corresponds produced voltage from the output current of the previous multiplier with resistor R1 = 1.6 kΩ. V2 is a DC voltage with the value of VD = 135 mV. It stands for α with scaled a constant. For weighted summation, RX and RZ is used with values RX = 1 kΩ and RZ = 2.5 kΩ.


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To utilize a lossless inductor, in matching constraint given in (23) the impedance value is obtained as in (24).

4.4 Single DDCC+ Based Inductance Simulator

G1  G3  G4   G3  G2  G4  ,

Inductors are undesired elements in circuits because of their drawbacks such as in the usage of space, cost and adjustability. They cannot be implemented inside a chip. Actively simulating of the inductors offers appropriate design possibilities and in this sense it is more preferable.

Leq 

4.5 CMOS Design of DDCC CMOS design of DDCC± used in this work is shown in Fig. 14. Our DDCC± is constructed based on implementations given in [28], [30]. In the circuit, M1, M2 and M3, M4 are two differential stages. High gain stage is obtained by a current mirror and the differential current is converted to a single-ended output current with the transistors M13, M14, M15. The positive output terminal Z+ is composed with a current source and duplicating elements of the current of the transistor M15 (M8, M9, M16 and M17). At the negative output terminal Z-, the current mirror shaped and the direction of the current is changed by transistors M10, M11, M12 and M18. Offset issue is critical for the multiplier stages in our design. A small DC current has come up at the output of multipliers. It would be solved for multiplier 1 by defining the value of VD in Fig. 12. However, to systematically get rid of this constant DC current offset, M19 is used.

G3

Y1 Y2

Zi

DDCC+ Z

Y3 X

G2

G4

C5 Fig. 13. DDCC based inductance simulator.

By using this topology it is either possible to realize an inductor with series resistance or a lossless inductor. For the grounded inductor with series resistance, equivalent inductance and resistance are defined by Leq 

G1  G3  G4   G3  G4  G2   2sG1C5 G3G4  G1  G8 

G1  G3  G4   G3  G4  G2 

Req 

G3G4  G1  G8 

,

.

(24)

Parameters of inductance simulator are selected as R1 = 1.35 kΩ, R3 = 1.35 kΩ, R4 = 1.35 kΩ, R2 = 450 Ω.

A single CCII+ based inductance simulator was presented by Cicekoglu and Kuntman [30]. Based on this implementation, we have constructed a DDCC+ based new inductance simulator as shown in Fig. 13.

G1

2 sG1C5 . G3G4  G1  G2 

The supply voltages VCC and VSS are +1.25 V and -1.25 V, respectively. Bias voltages are taken as Vb1 = -0.34 V and Vb2 = 0. Aspect ratios of all NMOS and PMOS transistors except M19 are WN/LN = 4 µm / 0.8 µm and WP/LP = 8 µm / 0.8 µm, respectively. Dimensions of M19 are defined as WM19/LM19 = 20 µm / 9 µm.

(21)

(22)

VCC M18

M17 M14

M15

Vb2

M16 M19

M13 M12

Y1

Y2

M1

M2

Y3

M3

X

Z+

Z-

M4

M10 Vb1

M5

M6

M7

(23)

M8

M9

VSS

Fig. 14. CMOS circuit schematic of DDCC.

M11

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5. Simulation Results

Time and corresponding frequency domain waveforms and chaotic phase portraits are shown in Fig. 15 and Fig. 16, respectively. Note that the time domain and phase portrait plots obtained from the CMOS circuit exhibit very good visual agreement with corresponding plot in the MATLAB simulations.

vC2 (V)

vC1 (V)

iL (A)

φ (Wb)

In this section PSPICE simulations of the fully CMOS memristor-based circuit are performed and results are shown. Resistance R in Fig. 1 is still a parameter. It is taken the same as in MATLAB simulations: R = 1.97 kΩ. Setting of parameters properly has emerged as a critical issue. In addition to defining of parameters according to the calculations and design constraints, additional adjust-

ments have been carried out by considering characteristics of the whole system.

Fig. 15. Time domain waveforms of chaotic signals from SPICE simulations.


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Fig. 16. Phase portraits from the SPICE simulations.

The total power consumption of the system is determined as 3.2 mW. This indicates a very low level comparing of other traditional op-amp based realizations. Beyond the prior works and traditional op-amp based implementations, our design is entirely CMOS based and implementable only on a chip. From this perspective, it is obvious that it requires much less area. Along with the current process technology, it promises a considerable reduction in terms of the total number of transistors used in

-5

6

x 10

Theoritical Simulated

4 2 q (C)

Flux-charge cubic characteristics of the memristor is shown in Fig. 17. Theoretical plot is obtained by using predetermined α and β at the beginning of our design. Experimental characteristics are obtained from CMOS chaotic circuit. From the SPICE simulations, the memductance parameters given in (8), are experimentally redetermined as α = -0.698 × 10-3 and β = 16.987 × 10-3.

0 -2 -4 -6 -0.2

-0.1

0  (Wb)

Fig. 17. Theoretical and experimental characteristic curve.

0.1

memristor

0.2

cubic

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the design even except inductor [8], [26]. Unlike the opamp based implementations, the proposed circuit can operate over a wide range of frequencies from Hz to MHz levels.

6. Conclusions In this study, a new fully CMOS memristor-based chaotic Chua’s circuit is presented. Memristor is implemented employing only CMOS DDCCs based blocks and therefore suitable to current VLSI processes. In the frame of the work performed, besides a systematically realizable DDCC-only realization approach to a CMOS-only memristor, a new CMOS-only chaotic oscillator is also presented. This design consumes less power and requires less area comparing other traditional realizations. Simulations performed show that with the memristor model proposed, both memristor characteristics and chaotic behavior of the system is provided accurately. Memristor promises some new features such as reduction in the area used for the same function, lower power consumption etc. Furthermore it can be observed clearly that new possibilities and advantages will be added thanks to its natural nonvolatile and non-linear structure. Since there is no physical sample yet, physically based correct modeling and design of the memristor is important. Proper implementations can be used in practical applications. It is possible to use a real physical memristor in this system when it is available. Memristor can be easily applied to chaotic circuits thanks to its natural nonlinear behavior. It seems reasonable to compose memristor-based chaotic synchronization and chaotic communication applications. In addition it is known that memristors can mimic the behavior of biological synapses. We believe that our implementation and its application to chaotic circuits would benefit the memristorbased chaotic circuits, memristor-based analog signal processing applications.

References

[6] IU, H.H.C., YU, D.S., FITCH, A.L., SREERAM, V., CHEN, H. Controlling chaos in a memristor based circuit using a twin-T notch filter. IEEE Transactions on Circuits and Systems I: Regular Papers, 2011, vol. 58, no. 6, p. 1337–1344. [7] DRISCOLL, T., PERSHIN, Y. V., BASOV, D. N., DI VENTRA, M. Chaotic memristor. Applied Physics A, 2010, vol. 102, no. 4, p. 885-889. [8] YENER, S.C., KUNTMAN, H. A new CMOS based memristor implementation. In Proc. of 2012 International Conference on Applied Electronics. Pilsen (Czech Republic), 2012, p. 345-348. [9] YENER, Ş. Ç., MUTLU, R., KUNTMAN, H. Performance analysis of a memristor-based biquad filter using its dynamic model. Informacije MIDEM - Journal of Microelectronics, Electronic Components and Materials, 2014, vol. 44, no. 2, p. 109–118. [10] YENER, Ş. Ç., MUTLU, R., KUNTMAN, H. A new memristorbased high-pass filter: Its analytical and dynamical analysis. In 24th International Conference Radioelektronika 2014. Bratislava, (Slovak Republic), April 15 – 16, 2014, p. 1–4. [11] YENER, Ş. Ç., MUTLU, R., KUNTMAN, H. Frequency and time domain characteristics of memristor-based filters. In 22nd Signal Processing and Communication Applications Conference (SİU). Karadeniz Technical University, Trabzon, 2014, p. 2027–2030. [12] RAK, A., CSEREY, G. Macromodeling of the memristor in SPICE. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2010, vol. 29, no. 4, p. 632 – 636. [13] BIOLEK, Z., BIOLEK, D., BIOLKOVA, V. SPICE model of memristor with nonlinear dopant drift. Radioengineering, 2009, vol. 18, no. 2, p. 210–214. [14] BATAS, D., FIEDLER, H. A memristor SPICE implementation and a new approach for magnetic flux-controlled memristor modeling. IEEE Transactions on Nanotechnology, 2011, vol. 10, no. 2, p. 250–255. [15] BENDERLI, S., WEY, T. A. On SPICE macromodelling of TiO2 memristors. Electronics Letters, 2009, vol. 45, no. 7, p. 377–379. [16] SHARIFI, M. J., BANAKIDI, Y. M. General SPICE models for memristor and application to circuit simulation of memristor-based synapses and memory cells. Journal to Circuits, Systems and Computers, 2010, vol. 19, no. 2, p. 407–424. [17] PERSHIN, Y. V., DI VENTRA, M. SPICE model of memristive devices with threshold. Radioengineering, 2013, vol. 22, no. 2, p. 485–489. [18] BIOLEK, D., DI VENTRA, M., PERSHIN, Y. V. Reliable SPICE simulations of memristors, memcapacitors and meminductors. Radioengineering, 2013, vol. 22, no. 4, p. 945–968.

[1] CHUA, L. O. Memristor - the missing circuit element. IEEE Trans. on Circuit Theory, 1971, vol. 18, no. 5, p. 507–519.

[19] BIOLEK, Z., BIOLEK, D., BIOLKOVÁ, V. Analytical computation of the area of pinched hysteresis loops of ideal memelements. Radioengineering, 2013, vol. 22, no. 1, p. 132–135.

[2] STRUKOV, D.B., SNIDER, G.S., STEWART, D.R., WILLIAMS, R. S. The missing memristor found. Nature, 2008, vol. 453, 1 May 2008, p. 80–83.

[20] PERSHIN, Y. V., DI VENTRA, M. Practical approach to programmable analog circuits with memristors. IEEE Transactions on Circuits and Systems - I, 2010, vol. 57, no. 8, p. 1857–1864.

[3] KAVEHEI, O., IQBAL, A., KIM, Y., ESHRAGHIAN, K., ALSARAWI, S., ABBOTT, D. The fourth element: characteristics, modelling and electromagnetic theory of the memristor. Proceedings of the Royal Society A: Mathematical, Physical and Engineering Science, 2010, 466 (2120), p. 2175–2202.

[21] KIM, H., SAH, M. P., YANG, C., CHO, S., CHUA, L. O. Memristor emulator for memristor circuit applications. IEEE Transactions on Circuit and Systems – I, 2012, vol. 59, no.10, p. 2422–2431.

[4] SAH, M. P.D., YANG, C., KIM, H., CHUA, L.O. A voltage mode memristor bridge synaptic circuit with memristor emulators. Sensors, 2012, vol. 12, no. 3, p. 3587–3604.

[22] MUTLU, R., KARAKULAK, E. Emulator circuit of TiO2 memristor with linear dopant drift made using analog multiplier. In National Conference on Electrical, Electronics and Computer Engineering (ELECO) 2010. Bursa (Turkey), 2010, p. 380–384.

[5] MUTHUSWAMY, B., CHUA, L. O. Simplest chaotic circuit. International Journal of Bifurcation and Chaos, 2010, vol. 20, no. 5, p. 1567–1580.

[23] RADWAN, A. G., SOLIMAN, A. M., EL-SEDEEK A. An inductorless CMOS realization of Chua’s circuit. Chaos, Solitons and Fractals, 2003, vol. 18, p. 149–158.


[24] GOPAKUMAR, K., PREMBLET, B., GOPCHANDRAN, K. G. Implementation of Chua's circuit using simulated inductance. International Journal of Electronics, 2011, vol. 98, no. 5, p. 667 to 677. [25] ZHONG, G. Implementation of Chua's circuit with a cubic nonlinearity. IEEE Transactions on Circuits and Systems, 1994, vol. 41, no. 12, p. 934–941. [26] MUTHUSWAMY, B. Implementing memristor based chaotic circuits. International Journal of Bifurcation and Chaos, 2010, vol. 20, no. 5, p. 1335–1350. [27] ŠPÁNY, V., GALAJDA, P., GUZAN, M., PIVKA, L., OLEJÁR, M. Chua's singularities: great miracle in circuit theory. International Journal of Bifurcation and Chaos, 2010, vol. 20, no. 10, p. 2993–3006. [28] CHIU, W., LIU, S. I., TSAO, H. W., CHEN, J. J. CMOS differential difference current conveyors and their applications. IEEE Proceedings: Circuits, Devices and Systems, 1996, vol. 143, p. 91–96. [29] CICEKOGLU, O., KUNTMAN, H. Single CCII+ based active simulation of grounded inductors. In ECCTD 2014: European Conference on Circuit Theory and Design. Budapest (Hungary), 1997, p. 105–109. [30] CHANG, C. M., LEE, C. N., HOU, C. L., HORNG, J. W., TU, C. K. High-order DDCC-based general mixed-mode universal filter. IEEE Proceedings: Circuits, Devices and Systems, 2006, vol. 153, p. 511–516.

About Authors... Şuayb Çağrı YENER was born in Sakarya, Turkey in 1982. He received B.Sc. degree from Sakarya University in Electrical and Electronics Engineering in 2004, M.Sc. and

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Ph. D. degree from Istanbul University in Electronics and Communication Engineering in 2007 and 2014, respectively. He is currently a research assistant in Sakarya University. His main research interests are CMOS analog circuits, analog circuit design, circuit and electronic device modeling, modeling of the memristor and memristor based circuits. He is the author or co-author of 26 journal papers published/accepted for publishing and papers presented in national/international conferences. H. Hakan KUNTMAN received his B.Sc., M.Sc. and Ph.D. degrees from Istanbul Technical University in 1974, 1977 and 1982, respectively. In 1974 he joined the Electronics and Communication Engineering Department of Istanbul Technical University. Since 1993 he is a professor of Electronics in the same department. His research interest includes design of electronic circuits, modeling of electron devices and electronic systems, active filters, design of analog IC topologies. Dr. Kuntman has authored many publications on modeling and simulation of electron devices and electronic circuits for computer-aided design, analog VLSI design and active circuit design. He is the author or co-author of 111 journal papers published or accepted for publishing in international journals, 168 conference papers presented or accepted for presentation in international conferences, 156 Turkish conference papers presented in national conferences and 10 books related to the above mentioned areas. Furthermore he advised and completed the work of 13 Ph.D. students and 41 M.Sc students. Currently, he acts as the advisor of 3 Ph.D. and 4 M.Sc. students. Dr. Kuntman is a member of the Chamber of Turkish Electrical Engineers (EMO).